Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
Pierre Ossman | 70f1048 | 2007-07-11 20:04:50 +0200 | [diff] [blame] | 2 | * linux/drivers/mmc/host/pxa.c - PXA MMCI driver |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2003 Russell King, All Rights Reserved. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * This hardware is really sick: |
| 11 | * - No way to clear interrupts. |
| 12 | * - Have to turn off the clock whenever we touch the device. |
| 13 | * - Doesn't tell you how many data blocks were transferred. |
| 14 | * Yuck! |
| 15 | * |
| 16 | * 1 and 3 byte data transfers not supported |
| 17 | * max block length up to 1023 |
| 18 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 19 | #include <linux/module.h> |
| 20 | #include <linux/init.h> |
| 21 | #include <linux/ioport.h> |
Russell King | d052d1b | 2005-10-29 19:07:23 +0100 | [diff] [blame] | 22 | #include <linux/platform_device.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 23 | #include <linux/delay.h> |
| 24 | #include <linux/interrupt.h> |
| 25 | #include <linux/dma-mapping.h> |
Russell King | ebebd9b | 2007-08-20 10:20:03 +0100 | [diff] [blame] | 26 | #include <linux/clk.h> |
| 27 | #include <linux/err.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 28 | #include <linux/mmc/host.h> |
Russell King | 05678a9 | 2008-11-28 16:04:54 +0000 | [diff] [blame] | 29 | #include <linux/io.h> |
Daniel Ribeiro | 8385f9c | 2009-05-21 08:54:18 -0300 | [diff] [blame] | 30 | #include <linux/regulator/consumer.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 31 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 32 | #include <asm/sizes.h> |
| 33 | |
Russell King | 05678a9 | 2008-11-28 16:04:54 +0000 | [diff] [blame] | 34 | #include <mach/hardware.h> |
Eric Miao | 7ebc8d5 | 2009-01-02 19:38:42 +0800 | [diff] [blame] | 35 | #include <mach/dma.h> |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 36 | #include <mach/mmc.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 37 | |
| 38 | #include "pxamci.h" |
| 39 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 40 | #define DRIVER_NAME "pxa2xx-mci" |
| 41 | |
| 42 | #define NR_SG 1 |
Russell King | d8cb70d | 2007-10-26 17:56:40 +0100 | [diff] [blame] | 43 | #define CLKRT_OFF (~0) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 44 | |
| 45 | struct pxamci_host { |
| 46 | struct mmc_host *mmc; |
| 47 | spinlock_t lock; |
| 48 | struct resource *res; |
| 49 | void __iomem *base; |
Russell King | ebebd9b | 2007-08-20 10:20:03 +0100 | [diff] [blame] | 50 | struct clk *clk; |
| 51 | unsigned long clkrate; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 52 | int irq; |
| 53 | int dma; |
| 54 | unsigned int clkrt; |
| 55 | unsigned int cmdat; |
| 56 | unsigned int imask; |
| 57 | unsigned int power_mode; |
| 58 | struct pxamci_platform_data *pdata; |
| 59 | |
| 60 | struct mmc_request *mrq; |
| 61 | struct mmc_command *cmd; |
| 62 | struct mmc_data *data; |
| 63 | |
| 64 | dma_addr_t sg_dma; |
| 65 | struct pxa_dma_desc *sg_cpu; |
| 66 | unsigned int dma_len; |
| 67 | |
| 68 | unsigned int dma_dir; |
Bridge Wu | 9a788c6 | 2007-12-14 10:40:25 +0100 | [diff] [blame] | 69 | unsigned int dma_drcmrrx; |
| 70 | unsigned int dma_drcmrtx; |
Daniel Ribeiro | 8385f9c | 2009-05-21 08:54:18 -0300 | [diff] [blame] | 71 | |
| 72 | struct regulator *vcc; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 73 | }; |
| 74 | |
Daniel Ribeiro | 8385f9c | 2009-05-21 08:54:18 -0300 | [diff] [blame] | 75 | static inline void pxamci_init_ocr(struct pxamci_host *host) |
| 76 | { |
| 77 | #ifdef CONFIG_REGULATOR |
| 78 | host->vcc = regulator_get(mmc_dev(host->mmc), "vmmc"); |
| 79 | |
| 80 | if (IS_ERR(host->vcc)) |
| 81 | host->vcc = NULL; |
| 82 | else { |
| 83 | host->mmc->ocr_avail = mmc_regulator_get_ocrmask(host->vcc); |
| 84 | if (host->pdata && host->pdata->ocr_mask) |
| 85 | dev_warn(mmc_dev(host->mmc), |
| 86 | "ocr_mask/setpower will not be used\n"); |
| 87 | } |
| 88 | #endif |
| 89 | if (host->vcc == NULL) { |
| 90 | /* fall-back to platform data */ |
| 91 | host->mmc->ocr_avail = host->pdata ? |
| 92 | host->pdata->ocr_mask : |
| 93 | MMC_VDD_32_33 | MMC_VDD_33_34; |
| 94 | } |
| 95 | } |
| 96 | |
| 97 | static inline void pxamci_set_power(struct pxamci_host *host, unsigned int vdd) |
| 98 | { |
| 99 | #ifdef CONFIG_REGULATOR |
| 100 | if (host->vcc) |
| 101 | mmc_regulator_set_ocr(host->vcc, vdd); |
| 102 | #endif |
| 103 | if (!host->vcc && host->pdata && host->pdata->setpower) |
| 104 | host->pdata->setpower(mmc_dev(host->mmc), vdd); |
| 105 | } |
| 106 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 107 | static void pxamci_stop_clock(struct pxamci_host *host) |
| 108 | { |
| 109 | if (readl(host->base + MMC_STAT) & STAT_CLK_EN) { |
| 110 | unsigned long timeout = 10000; |
| 111 | unsigned int v; |
| 112 | |
| 113 | writel(STOP_CLOCK, host->base + MMC_STRPCL); |
| 114 | |
| 115 | do { |
| 116 | v = readl(host->base + MMC_STAT); |
| 117 | if (!(v & STAT_CLK_EN)) |
| 118 | break; |
| 119 | udelay(1); |
| 120 | } while (timeout--); |
| 121 | |
| 122 | if (v & STAT_CLK_EN) |
| 123 | dev_err(mmc_dev(host->mmc), "unable to stop clock\n"); |
| 124 | } |
| 125 | } |
| 126 | |
| 127 | static void pxamci_enable_irq(struct pxamci_host *host, unsigned int mask) |
| 128 | { |
| 129 | unsigned long flags; |
| 130 | |
| 131 | spin_lock_irqsave(&host->lock, flags); |
| 132 | host->imask &= ~mask; |
| 133 | writel(host->imask, host->base + MMC_I_MASK); |
| 134 | spin_unlock_irqrestore(&host->lock, flags); |
| 135 | } |
| 136 | |
| 137 | static void pxamci_disable_irq(struct pxamci_host *host, unsigned int mask) |
| 138 | { |
| 139 | unsigned long flags; |
| 140 | |
| 141 | spin_lock_irqsave(&host->lock, flags); |
| 142 | host->imask |= mask; |
| 143 | writel(host->imask, host->base + MMC_I_MASK); |
| 144 | spin_unlock_irqrestore(&host->lock, flags); |
| 145 | } |
| 146 | |
| 147 | static void pxamci_setup_data(struct pxamci_host *host, struct mmc_data *data) |
| 148 | { |
| 149 | unsigned int nob = data->blocks; |
Russell King | 3d63abe | 2006-04-24 11:27:02 +0100 | [diff] [blame] | 150 | unsigned long long clks; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 151 | unsigned int timeout; |
Philipp Zabel | 97f8571 | 2008-07-06 01:15:34 +0200 | [diff] [blame] | 152 | bool dalgn = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 153 | u32 dcmd; |
| 154 | int i; |
| 155 | |
| 156 | host->data = data; |
| 157 | |
| 158 | if (data->flags & MMC_DATA_STREAM) |
| 159 | nob = 0xffff; |
| 160 | |
| 161 | writel(nob, host->base + MMC_NOB); |
Pavel Pisa | 2c171bf | 2006-05-19 21:48:03 +0100 | [diff] [blame] | 162 | writel(data->blksz, host->base + MMC_BLKLEN); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 163 | |
Russell King | ebebd9b | 2007-08-20 10:20:03 +0100 | [diff] [blame] | 164 | clks = (unsigned long long)data->timeout_ns * host->clkrate; |
Russell King | 3d63abe | 2006-04-24 11:27:02 +0100 | [diff] [blame] | 165 | do_div(clks, 1000000000UL); |
| 166 | timeout = (unsigned int)clks + (data->timeout_clks << host->clkrt); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 167 | writel((timeout + 255) / 256, host->base + MMC_RDTO); |
| 168 | |
| 169 | if (data->flags & MMC_DATA_READ) { |
| 170 | host->dma_dir = DMA_FROM_DEVICE; |
Matt Reimer | 7eeff48 | 2009-06-15 13:21:25 -0700 | [diff] [blame] | 171 | dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC; |
Bridge Wu | 9a788c6 | 2007-12-14 10:40:25 +0100 | [diff] [blame] | 172 | DRCMR(host->dma_drcmrtx) = 0; |
| 173 | DRCMR(host->dma_drcmrrx) = host->dma | DRCMR_MAPVLD; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 174 | } else { |
| 175 | host->dma_dir = DMA_TO_DEVICE; |
Matt Reimer | 7eeff48 | 2009-06-15 13:21:25 -0700 | [diff] [blame] | 176 | dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG; |
Bridge Wu | 9a788c6 | 2007-12-14 10:40:25 +0100 | [diff] [blame] | 177 | DRCMR(host->dma_drcmrrx) = 0; |
| 178 | DRCMR(host->dma_drcmrtx) = host->dma | DRCMR_MAPVLD; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 179 | } |
| 180 | |
| 181 | dcmd |= DCMD_BURST32 | DCMD_WIDTH1; |
| 182 | |
| 183 | host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, |
| 184 | host->dma_dir); |
| 185 | |
| 186 | for (i = 0; i < host->dma_len; i++) { |
Nicolas Pitre | c783837 | 2007-10-09 17:07:58 -0400 | [diff] [blame] | 187 | unsigned int length = sg_dma_len(&data->sg[i]); |
| 188 | host->sg_cpu[i].dcmd = dcmd | length; |
| 189 | if (length & 31 && !(data->flags & MMC_DATA_READ)) |
| 190 | host->sg_cpu[i].dcmd |= DCMD_ENDIRQEN; |
Philipp Zabel | 97f8571 | 2008-07-06 01:15:34 +0200 | [diff] [blame] | 191 | /* Not aligned to 8-byte boundary? */ |
| 192 | if (sg_dma_address(&data->sg[i]) & 0x7) |
| 193 | dalgn = 1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 194 | if (data->flags & MMC_DATA_READ) { |
| 195 | host->sg_cpu[i].dsadr = host->res->start + MMC_RXFIFO; |
| 196 | host->sg_cpu[i].dtadr = sg_dma_address(&data->sg[i]); |
| 197 | } else { |
| 198 | host->sg_cpu[i].dsadr = sg_dma_address(&data->sg[i]); |
| 199 | host->sg_cpu[i].dtadr = host->res->start + MMC_TXFIFO; |
| 200 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 201 | host->sg_cpu[i].ddadr = host->sg_dma + (i + 1) * |
| 202 | sizeof(struct pxa_dma_desc); |
| 203 | } |
| 204 | host->sg_cpu[host->dma_len - 1].ddadr = DDADR_STOP; |
| 205 | wmb(); |
| 206 | |
Philipp Zabel | 97f8571 | 2008-07-06 01:15:34 +0200 | [diff] [blame] | 207 | /* |
| 208 | * The PXA27x DMA controller encounters overhead when working with |
| 209 | * unaligned (to 8-byte boundaries) data, so switch on byte alignment |
| 210 | * mode only if we have unaligned data. |
| 211 | */ |
| 212 | if (dalgn) |
| 213 | DALGN |= (1 << host->dma); |
| 214 | else |
Karl Beldan | 4fe1689 | 2008-07-16 18:29:11 +0200 | [diff] [blame] | 215 | DALGN &= ~(1 << host->dma); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 216 | DDADR(host->dma) = host->sg_dma; |
Cliff Brake | b601895 | 2009-01-22 17:07:03 -0500 | [diff] [blame] | 217 | |
| 218 | /* |
| 219 | * workaround for erratum #91: |
| 220 | * only start DMA now if we are doing a read, |
| 221 | * otherwise we wait until CMD/RESP has finished |
| 222 | * before starting DMA. |
| 223 | */ |
| 224 | if (!cpu_is_pxa27x() || data->flags & MMC_DATA_READ) |
| 225 | DCSR(host->dma) = DCSR_RUN; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 226 | } |
| 227 | |
| 228 | static void pxamci_start_cmd(struct pxamci_host *host, struct mmc_command *cmd, unsigned int cmdat) |
| 229 | { |
| 230 | WARN_ON(host->cmd != NULL); |
| 231 | host->cmd = cmd; |
| 232 | |
| 233 | if (cmd->flags & MMC_RSP_BUSY) |
| 234 | cmdat |= CMDAT_BUSY; |
| 235 | |
Russell King | e922517 | 2006-02-02 12:23:12 +0000 | [diff] [blame] | 236 | #define RSP_TYPE(x) ((x) & ~(MMC_RSP_BUSY|MMC_RSP_OPCODE)) |
| 237 | switch (RSP_TYPE(mmc_resp_type(cmd))) { |
Philip Langdale | 6f94990 | 2007-01-04 07:04:47 -0800 | [diff] [blame] | 238 | case RSP_TYPE(MMC_RSP_R1): /* r1, r1b, r6, r7 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 239 | cmdat |= CMDAT_RESP_SHORT; |
| 240 | break; |
Russell King | e922517 | 2006-02-02 12:23:12 +0000 | [diff] [blame] | 241 | case RSP_TYPE(MMC_RSP_R3): |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 242 | cmdat |= CMDAT_RESP_R3; |
| 243 | break; |
Russell King | e922517 | 2006-02-02 12:23:12 +0000 | [diff] [blame] | 244 | case RSP_TYPE(MMC_RSP_R2): |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 245 | cmdat |= CMDAT_RESP_R2; |
| 246 | break; |
| 247 | default: |
| 248 | break; |
| 249 | } |
| 250 | |
| 251 | writel(cmd->opcode, host->base + MMC_CMD); |
| 252 | writel(cmd->arg >> 16, host->base + MMC_ARGH); |
| 253 | writel(cmd->arg & 0xffff, host->base + MMC_ARGL); |
| 254 | writel(cmdat, host->base + MMC_CMDAT); |
| 255 | writel(host->clkrt, host->base + MMC_CLKRT); |
| 256 | |
| 257 | writel(START_CLOCK, host->base + MMC_STRPCL); |
| 258 | |
| 259 | pxamci_enable_irq(host, END_CMD_RES); |
| 260 | } |
| 261 | |
| 262 | static void pxamci_finish_request(struct pxamci_host *host, struct mmc_request *mrq) |
| 263 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 264 | host->mrq = NULL; |
| 265 | host->cmd = NULL; |
| 266 | host->data = NULL; |
| 267 | mmc_request_done(host->mmc, mrq); |
| 268 | } |
| 269 | |
| 270 | static int pxamci_cmd_done(struct pxamci_host *host, unsigned int stat) |
| 271 | { |
| 272 | struct mmc_command *cmd = host->cmd; |
| 273 | int i; |
| 274 | u32 v; |
| 275 | |
| 276 | if (!cmd) |
| 277 | return 0; |
| 278 | |
| 279 | host->cmd = NULL; |
| 280 | |
| 281 | /* |
| 282 | * Did I mention this is Sick. We always need to |
| 283 | * discard the upper 8 bits of the first 16-bit word. |
| 284 | */ |
| 285 | v = readl(host->base + MMC_RES) & 0xffff; |
| 286 | for (i = 0; i < 4; i++) { |
| 287 | u32 w1 = readl(host->base + MMC_RES) & 0xffff; |
| 288 | u32 w2 = readl(host->base + MMC_RES) & 0xffff; |
| 289 | cmd->resp[i] = v << 24 | w1 << 8 | w2 >> 8; |
| 290 | v = w2; |
| 291 | } |
| 292 | |
| 293 | if (stat & STAT_TIME_OUT_RESPONSE) { |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 294 | cmd->error = -ETIMEDOUT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 295 | } else if (stat & STAT_RES_CRC_ERR && cmd->flags & MMC_RSP_CRC) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 296 | /* |
| 297 | * workaround for erratum #42: |
| 298 | * Intel PXA27x Family Processor Specification Update Rev 001 |
Nicolas Pitre | 90e07d9 | 2007-05-13 18:03:08 +0200 | [diff] [blame] | 299 | * A bogus CRC error can appear if the msb of a 136 bit |
| 300 | * response is a one. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 301 | */ |
Cliff Brake | e10a854 | 2009-01-22 16:58:58 -0500 | [diff] [blame] | 302 | if (cpu_is_pxa27x() && |
| 303 | (cmd->flags & MMC_RSP_136 && cmd->resp[0] & 0x80000000)) |
Nicolas Pitre | 90e07d9 | 2007-05-13 18:03:08 +0200 | [diff] [blame] | 304 | pr_debug("ignoring CRC from command %d - *risky*\n", cmd->opcode); |
Cliff Brake | e10a854 | 2009-01-22 16:58:58 -0500 | [diff] [blame] | 305 | else |
| 306 | cmd->error = -EILSEQ; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 307 | } |
| 308 | |
| 309 | pxamci_disable_irq(host, END_CMD_RES); |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 310 | if (host->data && !cmd->error) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 311 | pxamci_enable_irq(host, DATA_TRAN_DONE); |
Cliff Brake | b601895 | 2009-01-22 17:07:03 -0500 | [diff] [blame] | 312 | /* |
| 313 | * workaround for erratum #91, if doing write |
| 314 | * enable DMA late |
| 315 | */ |
| 316 | if (cpu_is_pxa27x() && host->data->flags & MMC_DATA_WRITE) |
| 317 | DCSR(host->dma) = DCSR_RUN; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 318 | } else { |
| 319 | pxamci_finish_request(host, host->mrq); |
| 320 | } |
| 321 | |
| 322 | return 1; |
| 323 | } |
| 324 | |
| 325 | static int pxamci_data_done(struct pxamci_host *host, unsigned int stat) |
| 326 | { |
| 327 | struct mmc_data *data = host->data; |
| 328 | |
| 329 | if (!data) |
| 330 | return 0; |
| 331 | |
| 332 | DCSR(host->dma) = 0; |
Vernon Sauder | c00a46a | 2008-12-29 19:21:28 -0500 | [diff] [blame] | 333 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 334 | host->dma_dir); |
| 335 | |
| 336 | if (stat & STAT_READ_TIME_OUT) |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 337 | data->error = -ETIMEDOUT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 338 | else if (stat & (STAT_CRC_READ_ERROR|STAT_CRC_WRITE_ERROR)) |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 339 | data->error = -EILSEQ; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 340 | |
| 341 | /* |
| 342 | * There appears to be a hardware design bug here. There seems to |
| 343 | * be no way to find out how much data was transferred to the card. |
| 344 | * This means that if there was an error on any block, we mark all |
| 345 | * data blocks as being in error. |
| 346 | */ |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 347 | if (!data->error) |
Pavel Pisa | 2c171bf | 2006-05-19 21:48:03 +0100 | [diff] [blame] | 348 | data->bytes_xfered = data->blocks * data->blksz; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 349 | else |
| 350 | data->bytes_xfered = 0; |
| 351 | |
| 352 | pxamci_disable_irq(host, DATA_TRAN_DONE); |
| 353 | |
| 354 | host->data = NULL; |
Russell King | 58741e8 | 2006-05-02 20:02:39 +0100 | [diff] [blame] | 355 | if (host->mrq->stop) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 356 | pxamci_stop_clock(host); |
Bridge Wu | df456f4 | 2007-09-25 19:09:19 +0200 | [diff] [blame] | 357 | pxamci_start_cmd(host, host->mrq->stop, host->cmdat); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 358 | } else { |
| 359 | pxamci_finish_request(host, host->mrq); |
| 360 | } |
| 361 | |
| 362 | return 1; |
| 363 | } |
| 364 | |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 365 | static irqreturn_t pxamci_irq(int irq, void *devid) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 366 | { |
| 367 | struct pxamci_host *host = devid; |
| 368 | unsigned int ireg; |
| 369 | int handled = 0; |
| 370 | |
Bridge Wu | 81ab570f | 2007-09-25 18:59:07 +0200 | [diff] [blame] | 371 | ireg = readl(host->base + MMC_I_REG) & ~readl(host->base + MMC_I_MASK); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 372 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 373 | if (ireg) { |
| 374 | unsigned stat = readl(host->base + MMC_STAT); |
| 375 | |
Russell King | d78e907 | 2006-05-02 20:18:53 +0100 | [diff] [blame] | 376 | pr_debug("PXAMCI: irq %08x stat %08x\n", ireg, stat); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 377 | |
| 378 | if (ireg & END_CMD_RES) |
| 379 | handled |= pxamci_cmd_done(host, stat); |
| 380 | if (ireg & DATA_TRAN_DONE) |
| 381 | handled |= pxamci_data_done(host, stat); |
Bridge Wu | 5d3ad4e | 2007-09-25 19:11:00 +0200 | [diff] [blame] | 382 | if (ireg & SDIO_INT) { |
| 383 | mmc_signal_sdio_irq(host->mmc); |
| 384 | handled = 1; |
| 385 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 386 | } |
| 387 | |
| 388 | return IRQ_RETVAL(handled); |
| 389 | } |
| 390 | |
| 391 | static void pxamci_request(struct mmc_host *mmc, struct mmc_request *mrq) |
| 392 | { |
| 393 | struct pxamci_host *host = mmc_priv(mmc); |
| 394 | unsigned int cmdat; |
| 395 | |
| 396 | WARN_ON(host->mrq != NULL); |
| 397 | |
| 398 | host->mrq = mrq; |
| 399 | |
| 400 | pxamci_stop_clock(host); |
| 401 | |
| 402 | cmdat = host->cmdat; |
| 403 | host->cmdat &= ~CMDAT_INIT; |
| 404 | |
| 405 | if (mrq->data) { |
| 406 | pxamci_setup_data(host, mrq->data); |
| 407 | |
| 408 | cmdat &= ~CMDAT_BUSY; |
| 409 | cmdat |= CMDAT_DATAEN | CMDAT_DMAEN; |
| 410 | if (mrq->data->flags & MMC_DATA_WRITE) |
| 411 | cmdat |= CMDAT_WRITE; |
| 412 | |
| 413 | if (mrq->data->flags & MMC_DATA_STREAM) |
| 414 | cmdat |= CMDAT_STREAM; |
| 415 | } |
| 416 | |
| 417 | pxamci_start_cmd(host, mrq->cmd, cmdat); |
| 418 | } |
| 419 | |
Richard Purdie | e619524 | 2005-09-06 15:18:56 -0700 | [diff] [blame] | 420 | static int pxamci_get_ro(struct mmc_host *mmc) |
| 421 | { |
| 422 | struct pxamci_host *host = mmc_priv(mmc); |
| 423 | |
| 424 | if (host->pdata && host->pdata->get_ro) |
Anton Vorontsov | 08f80bb | 2008-06-17 18:17:39 +0400 | [diff] [blame] | 425 | return !!host->pdata->get_ro(mmc_dev(mmc)); |
| 426 | /* |
| 427 | * Board doesn't support read only detection; let the mmc core |
| 428 | * decide what to do. |
| 429 | */ |
| 430 | return -ENOSYS; |
Richard Purdie | e619524 | 2005-09-06 15:18:56 -0700 | [diff] [blame] | 431 | } |
| 432 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 433 | static void pxamci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) |
| 434 | { |
| 435 | struct pxamci_host *host = mmc_priv(mmc); |
| 436 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 437 | if (ios->clock) { |
Russell King | ebebd9b | 2007-08-20 10:20:03 +0100 | [diff] [blame] | 438 | unsigned long rate = host->clkrate; |
| 439 | unsigned int clk = rate / ios->clock; |
| 440 | |
Russell King | d8cb70d | 2007-10-26 17:56:40 +0100 | [diff] [blame] | 441 | if (host->clkrt == CLKRT_OFF) |
| 442 | clk_enable(host->clk); |
| 443 | |
Bridge Wu | 64eb036 | 2007-12-13 07:24:30 +0100 | [diff] [blame] | 444 | if (ios->clock == 26000000) { |
| 445 | /* to support 26MHz on pxa300/pxa310 */ |
| 446 | host->clkrt = 7; |
| 447 | } else { |
| 448 | /* to handle (19.5MHz, 26MHz) */ |
| 449 | if (!clk) |
| 450 | clk = 1; |
| 451 | |
| 452 | /* |
| 453 | * clk might result in a lower divisor than we |
| 454 | * desire. check for that condition and adjust |
| 455 | * as appropriate. |
| 456 | */ |
| 457 | if (rate / clk > ios->clock) |
| 458 | clk <<= 1; |
| 459 | host->clkrt = fls(clk) - 1; |
| 460 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 461 | |
| 462 | /* |
| 463 | * we write clkrt on the next command |
| 464 | */ |
| 465 | } else { |
| 466 | pxamci_stop_clock(host); |
Russell King | d8cb70d | 2007-10-26 17:56:40 +0100 | [diff] [blame] | 467 | if (host->clkrt != CLKRT_OFF) { |
| 468 | host->clkrt = CLKRT_OFF; |
| 469 | clk_disable(host->clk); |
| 470 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 471 | } |
| 472 | |
| 473 | if (host->power_mode != ios->power_mode) { |
| 474 | host->power_mode = ios->power_mode; |
| 475 | |
Daniel Ribeiro | 8385f9c | 2009-05-21 08:54:18 -0300 | [diff] [blame] | 476 | pxamci_set_power(host, ios->vdd); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 477 | |
| 478 | if (ios->power_mode == MMC_POWER_ON) |
| 479 | host->cmdat |= CMDAT_INIT; |
| 480 | } |
| 481 | |
Bridge Wu | df456f4 | 2007-09-25 19:09:19 +0200 | [diff] [blame] | 482 | if (ios->bus_width == MMC_BUS_WIDTH_4) |
| 483 | host->cmdat |= CMDAT_SD_4DAT; |
| 484 | else |
| 485 | host->cmdat &= ~CMDAT_SD_4DAT; |
| 486 | |
Russell King | d78e907 | 2006-05-02 20:18:53 +0100 | [diff] [blame] | 487 | pr_debug("PXAMCI: clkrt = %x cmdat = %x\n", |
Russell King | c656317 | 2006-03-29 09:30:20 +0100 | [diff] [blame] | 488 | host->clkrt, host->cmdat); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 489 | } |
| 490 | |
Bridge Wu | 5d3ad4e | 2007-09-25 19:11:00 +0200 | [diff] [blame] | 491 | static void pxamci_enable_sdio_irq(struct mmc_host *host, int enable) |
| 492 | { |
| 493 | struct pxamci_host *pxa_host = mmc_priv(host); |
| 494 | |
| 495 | if (enable) |
| 496 | pxamci_enable_irq(pxa_host, SDIO_INT); |
| 497 | else |
| 498 | pxamci_disable_irq(pxa_host, SDIO_INT); |
| 499 | } |
| 500 | |
David Brownell | ab7aefd | 2006-11-12 17:55:30 -0800 | [diff] [blame] | 501 | static const struct mmc_host_ops pxamci_ops = { |
Bridge Wu | 5d3ad4e | 2007-09-25 19:11:00 +0200 | [diff] [blame] | 502 | .request = pxamci_request, |
| 503 | .get_ro = pxamci_get_ro, |
| 504 | .set_ios = pxamci_set_ios, |
| 505 | .enable_sdio_irq = pxamci_enable_sdio_irq, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 506 | }; |
| 507 | |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 508 | static void pxamci_dma_irq(int dma, void *devid) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 509 | { |
Nicolas Pitre | c783837 | 2007-10-09 17:07:58 -0400 | [diff] [blame] | 510 | struct pxamci_host *host = devid; |
| 511 | int dcsr = DCSR(dma); |
| 512 | DCSR(dma) = dcsr & ~DCSR_STOPIRQEN; |
| 513 | |
| 514 | if (dcsr & DCSR_ENDINTR) { |
| 515 | writel(BUF_PART_FULL, host->base + MMC_PRTBUF); |
| 516 | } else { |
| 517 | printk(KERN_ERR "%s: DMA error on channel %d (DCSR=%#x)\n", |
| 518 | mmc_hostname(host->mmc), dma, dcsr); |
| 519 | host->data->error = -EIO; |
| 520 | pxamci_data_done(host, 0); |
| 521 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 522 | } |
| 523 | |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 524 | static irqreturn_t pxamci_detect_irq(int irq, void *devid) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 525 | { |
Richard Purdie | c26971c | 2005-09-08 22:48:16 +0100 | [diff] [blame] | 526 | struct pxamci_host *host = mmc_priv(devid); |
| 527 | |
| 528 | mmc_detect_change(devid, host->pdata->detect_delay); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 529 | return IRQ_HANDLED; |
| 530 | } |
| 531 | |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 532 | static int pxamci_probe(struct platform_device *pdev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 533 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 534 | struct mmc_host *mmc; |
| 535 | struct pxamci_host *host = NULL; |
Bridge Wu | 9a788c6 | 2007-12-14 10:40:25 +0100 | [diff] [blame] | 536 | struct resource *r, *dmarx, *dmatx; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 537 | int ret, irq; |
| 538 | |
| 539 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 540 | irq = platform_get_irq(pdev, 0); |
David Vrabel | 4894473 | 2006-01-19 17:56:29 +0000 | [diff] [blame] | 541 | if (!r || irq < 0) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 542 | return -ENXIO; |
| 543 | |
| 544 | r = request_mem_region(r->start, SZ_4K, DRIVER_NAME); |
| 545 | if (!r) |
| 546 | return -EBUSY; |
| 547 | |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 548 | mmc = mmc_alloc_host(sizeof(struct pxamci_host), &pdev->dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 549 | if (!mmc) { |
| 550 | ret = -ENOMEM; |
| 551 | goto out; |
| 552 | } |
| 553 | |
| 554 | mmc->ops = &pxamci_ops; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 555 | |
| 556 | /* |
| 557 | * We can do SG-DMA, but we don't because we never know how much |
| 558 | * data we successfully wrote to the card. |
| 559 | */ |
| 560 | mmc->max_phys_segs = NR_SG; |
| 561 | |
| 562 | /* |
| 563 | * Our hardware DMA can handle a maximum of one page per SG entry. |
| 564 | */ |
| 565 | mmc->max_seg_size = PAGE_SIZE; |
| 566 | |
Pierre Ossman | fe4a3c7 | 2006-11-21 17:54:23 +0100 | [diff] [blame] | 567 | /* |
Nicolas Pitre | fe2dc44 | 2007-09-24 15:47:18 -0400 | [diff] [blame] | 568 | * Block length register is only 10 bits before PXA27x. |
Pierre Ossman | fe4a3c7 | 2006-11-21 17:54:23 +0100 | [diff] [blame] | 569 | */ |
Eric Miao | 0ffcbfd | 2008-09-11 10:27:30 +0800 | [diff] [blame] | 570 | mmc->max_blk_size = cpu_is_pxa25x() ? 1023 : 2048; |
Pierre Ossman | fe4a3c7 | 2006-11-21 17:54:23 +0100 | [diff] [blame] | 571 | |
Pierre Ossman | 55db890 | 2006-11-21 17:55:45 +0100 | [diff] [blame] | 572 | /* |
| 573 | * Block count register is 16 bits. |
| 574 | */ |
| 575 | mmc->max_blk_count = 65535; |
| 576 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 577 | host = mmc_priv(mmc); |
| 578 | host->mmc = mmc; |
| 579 | host->dma = -1; |
| 580 | host->pdata = pdev->dev.platform_data; |
Russell King | d8cb70d | 2007-10-26 17:56:40 +0100 | [diff] [blame] | 581 | host->clkrt = CLKRT_OFF; |
Russell King | ebebd9b | 2007-08-20 10:20:03 +0100 | [diff] [blame] | 582 | |
Russell King | e0d8b13 | 2008-11-11 17:52:32 +0000 | [diff] [blame] | 583 | host->clk = clk_get(&pdev->dev, NULL); |
Russell King | ebebd9b | 2007-08-20 10:20:03 +0100 | [diff] [blame] | 584 | if (IS_ERR(host->clk)) { |
| 585 | ret = PTR_ERR(host->clk); |
| 586 | host->clk = NULL; |
| 587 | goto out; |
| 588 | } |
| 589 | |
| 590 | host->clkrate = clk_get_rate(host->clk); |
| 591 | |
| 592 | /* |
| 593 | * Calculate minimum clock rate, rounding up. |
| 594 | */ |
| 595 | mmc->f_min = (host->clkrate + 63) / 64; |
Bridge Wu | 64eb036 | 2007-12-13 07:24:30 +0100 | [diff] [blame] | 596 | mmc->f_max = (cpu_is_pxa300() || cpu_is_pxa310()) ? 26000000 |
| 597 | : host->clkrate; |
Russell King | ebebd9b | 2007-08-20 10:20:03 +0100 | [diff] [blame] | 598 | |
Daniel Ribeiro | 8385f9c | 2009-05-21 08:54:18 -0300 | [diff] [blame] | 599 | pxamci_init_ocr(host); |
| 600 | |
Bridge Wu | df456f4 | 2007-09-25 19:09:19 +0200 | [diff] [blame] | 601 | mmc->caps = 0; |
Bridge Wu | 5d3ad4e | 2007-09-25 19:11:00 +0200 | [diff] [blame] | 602 | host->cmdat = 0; |
Eric Miao | 0ffcbfd | 2008-09-11 10:27:30 +0800 | [diff] [blame] | 603 | if (!cpu_is_pxa25x()) { |
Bridge Wu | 5d3ad4e | 2007-09-25 19:11:00 +0200 | [diff] [blame] | 604 | mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ; |
| 605 | host->cmdat |= CMDAT_SDIO_INT_EN; |
Bridge Wu | 64eb036 | 2007-12-13 07:24:30 +0100 | [diff] [blame] | 606 | if (cpu_is_pxa300() || cpu_is_pxa310()) |
| 607 | mmc->caps |= MMC_CAP_MMC_HIGHSPEED | |
| 608 | MMC_CAP_SD_HIGHSPEED; |
Bridge Wu | 5d3ad4e | 2007-09-25 19:11:00 +0200 | [diff] [blame] | 609 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 610 | |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 611 | host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, &host->sg_dma, GFP_KERNEL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 612 | if (!host->sg_cpu) { |
| 613 | ret = -ENOMEM; |
| 614 | goto out; |
| 615 | } |
| 616 | |
| 617 | spin_lock_init(&host->lock); |
| 618 | host->res = r; |
| 619 | host->irq = irq; |
| 620 | host->imask = MMC_I_MASK_ALL; |
| 621 | |
| 622 | host->base = ioremap(r->start, SZ_4K); |
| 623 | if (!host->base) { |
| 624 | ret = -ENOMEM; |
| 625 | goto out; |
| 626 | } |
| 627 | |
| 628 | /* |
| 629 | * Ensure that the host controller is shut down, and setup |
| 630 | * with our defaults. |
| 631 | */ |
| 632 | pxamci_stop_clock(host); |
| 633 | writel(0, host->base + MMC_SPI); |
| 634 | writel(64, host->base + MMC_RESTO); |
| 635 | writel(host->imask, host->base + MMC_I_MASK); |
| 636 | |
| 637 | host->dma = pxa_request_dma(DRIVER_NAME, DMA_PRIO_LOW, |
| 638 | pxamci_dma_irq, host); |
| 639 | if (host->dma < 0) { |
| 640 | ret = -EBUSY; |
| 641 | goto out; |
| 642 | } |
| 643 | |
| 644 | ret = request_irq(host->irq, pxamci_irq, 0, DRIVER_NAME, host); |
| 645 | if (ret) |
| 646 | goto out; |
| 647 | |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 648 | platform_set_drvdata(pdev, mmc); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 649 | |
Bridge Wu | 9a788c6 | 2007-12-14 10:40:25 +0100 | [diff] [blame] | 650 | dmarx = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
| 651 | if (!dmarx) { |
| 652 | ret = -ENXIO; |
| 653 | goto out; |
| 654 | } |
| 655 | host->dma_drcmrrx = dmarx->start; |
| 656 | |
| 657 | dmatx = platform_get_resource(pdev, IORESOURCE_DMA, 1); |
| 658 | if (!dmatx) { |
| 659 | ret = -ENXIO; |
| 660 | goto out; |
| 661 | } |
| 662 | host->dma_drcmrtx = dmatx->start; |
| 663 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 664 | if (host->pdata && host->pdata->init) |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 665 | host->pdata->init(&pdev->dev, pxamci_detect_irq, mmc); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 666 | |
| 667 | mmc_add_host(mmc); |
| 668 | |
| 669 | return 0; |
| 670 | |
| 671 | out: |
| 672 | if (host) { |
| 673 | if (host->dma >= 0) |
| 674 | pxa_free_dma(host->dma); |
| 675 | if (host->base) |
| 676 | iounmap(host->base); |
| 677 | if (host->sg_cpu) |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 678 | dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma); |
Russell King | ebebd9b | 2007-08-20 10:20:03 +0100 | [diff] [blame] | 679 | if (host->clk) |
| 680 | clk_put(host->clk); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 681 | } |
| 682 | if (mmc) |
| 683 | mmc_free_host(mmc); |
| 684 | release_resource(r); |
| 685 | return ret; |
| 686 | } |
| 687 | |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 688 | static int pxamci_remove(struct platform_device *pdev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 689 | { |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 690 | struct mmc_host *mmc = platform_get_drvdata(pdev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 691 | |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 692 | platform_set_drvdata(pdev, NULL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 693 | |
| 694 | if (mmc) { |
| 695 | struct pxamci_host *host = mmc_priv(mmc); |
| 696 | |
Daniel Ribeiro | 8385f9c | 2009-05-21 08:54:18 -0300 | [diff] [blame] | 697 | if (host->vcc) |
| 698 | regulator_put(host->vcc); |
| 699 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 700 | if (host->pdata && host->pdata->exit) |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 701 | host->pdata->exit(&pdev->dev, mmc); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 702 | |
| 703 | mmc_remove_host(mmc); |
| 704 | |
| 705 | pxamci_stop_clock(host); |
| 706 | writel(TXFIFO_WR_REQ|RXFIFO_RD_REQ|CLK_IS_OFF|STOP_CMD| |
| 707 | END_CMD_RES|PRG_DONE|DATA_TRAN_DONE, |
| 708 | host->base + MMC_I_MASK); |
| 709 | |
Bridge Wu | 9a788c6 | 2007-12-14 10:40:25 +0100 | [diff] [blame] | 710 | DRCMR(host->dma_drcmrrx) = 0; |
| 711 | DRCMR(host->dma_drcmrtx) = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 712 | |
| 713 | free_irq(host->irq, host); |
| 714 | pxa_free_dma(host->dma); |
| 715 | iounmap(host->base); |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 716 | dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 717 | |
Russell King | ebebd9b | 2007-08-20 10:20:03 +0100 | [diff] [blame] | 718 | clk_put(host->clk); |
| 719 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 720 | release_resource(host->res); |
| 721 | |
| 722 | mmc_free_host(mmc); |
| 723 | } |
| 724 | return 0; |
| 725 | } |
| 726 | |
| 727 | #ifdef CONFIG_PM |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 728 | static int pxamci_suspend(struct platform_device *dev, pm_message_t state) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 729 | { |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 730 | struct mmc_host *mmc = platform_get_drvdata(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 731 | int ret = 0; |
| 732 | |
Russell King | 9480e30 | 2005-10-28 09:52:56 -0700 | [diff] [blame] | 733 | if (mmc) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 734 | ret = mmc_suspend_host(mmc, state); |
| 735 | |
| 736 | return ret; |
| 737 | } |
| 738 | |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 739 | static int pxamci_resume(struct platform_device *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 740 | { |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 741 | struct mmc_host *mmc = platform_get_drvdata(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 742 | int ret = 0; |
| 743 | |
Russell King | 9480e30 | 2005-10-28 09:52:56 -0700 | [diff] [blame] | 744 | if (mmc) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 745 | ret = mmc_resume_host(mmc); |
| 746 | |
| 747 | return ret; |
| 748 | } |
| 749 | #else |
| 750 | #define pxamci_suspend NULL |
| 751 | #define pxamci_resume NULL |
| 752 | #endif |
| 753 | |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 754 | static struct platform_driver pxamci_driver = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 755 | .probe = pxamci_probe, |
| 756 | .remove = pxamci_remove, |
| 757 | .suspend = pxamci_suspend, |
| 758 | .resume = pxamci_resume, |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 759 | .driver = { |
| 760 | .name = DRIVER_NAME, |
Kay Sievers | bc65c72 | 2008-04-15 14:34:28 -0700 | [diff] [blame] | 761 | .owner = THIS_MODULE, |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 762 | }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 763 | }; |
| 764 | |
| 765 | static int __init pxamci_init(void) |
| 766 | { |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 767 | return platform_driver_register(&pxamci_driver); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 768 | } |
| 769 | |
| 770 | static void __exit pxamci_exit(void) |
| 771 | { |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 772 | platform_driver_unregister(&pxamci_driver); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 773 | } |
| 774 | |
| 775 | module_init(pxamci_init); |
| 776 | module_exit(pxamci_exit); |
| 777 | |
| 778 | MODULE_DESCRIPTION("PXA Multimedia Card Interface Driver"); |
| 779 | MODULE_LICENSE("GPL"); |
Kay Sievers | bc65c72 | 2008-04-15 14:34:28 -0700 | [diff] [blame] | 780 | MODULE_ALIAS("platform:pxa2xx-mci"); |