Wan ZongShun | a50a97d | 2009-07-16 02:55:05 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2008-2009 Nuvoton technology corporation. |
| 3 | * |
| 4 | * Wan ZongShun <mcuos.com@gmail.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation;version 2 of the License. |
| 9 | * |
| 10 | */ |
| 11 | |
| 12 | #include <linux/module.h> |
| 13 | #include <linux/init.h> |
| 14 | #include <linux/mii.h> |
| 15 | #include <linux/netdevice.h> |
| 16 | #include <linux/etherdevice.h> |
| 17 | #include <linux/skbuff.h> |
| 18 | #include <linux/ethtool.h> |
| 19 | #include <linux/platform_device.h> |
| 20 | #include <linux/clk.h> |
| 21 | |
| 22 | #define DRV_MODULE_NAME "w90p910-emc" |
| 23 | #define DRV_MODULE_VERSION "0.1" |
| 24 | |
| 25 | /* Ethernet MAC Registers */ |
| 26 | #define REG_CAMCMR 0x00 |
| 27 | #define REG_CAMEN 0x04 |
| 28 | #define REG_CAMM_BASE 0x08 |
| 29 | #define REG_CAML_BASE 0x0c |
| 30 | #define REG_TXDLSA 0x88 |
| 31 | #define REG_RXDLSA 0x8C |
| 32 | #define REG_MCMDR 0x90 |
| 33 | #define REG_MIID 0x94 |
| 34 | #define REG_MIIDA 0x98 |
| 35 | #define REG_FFTCR 0x9C |
| 36 | #define REG_TSDR 0xa0 |
| 37 | #define REG_RSDR 0xa4 |
| 38 | #define REG_DMARFC 0xa8 |
| 39 | #define REG_MIEN 0xac |
| 40 | #define REG_MISTA 0xb0 |
| 41 | #define REG_CTXDSA 0xcc |
| 42 | #define REG_CTXBSA 0xd0 |
| 43 | #define REG_CRXDSA 0xd4 |
| 44 | #define REG_CRXBSA 0xd8 |
| 45 | |
| 46 | /* mac controller bit */ |
| 47 | #define MCMDR_RXON 0x01 |
| 48 | #define MCMDR_ACP (0x01 << 3) |
| 49 | #define MCMDR_SPCRC (0x01 << 5) |
| 50 | #define MCMDR_TXON (0x01 << 8) |
| 51 | #define MCMDR_FDUP (0x01 << 18) |
| 52 | #define MCMDR_ENMDC (0x01 << 19) |
| 53 | #define MCMDR_OPMOD (0x01 << 20) |
| 54 | #define SWR (0x01 << 24) |
| 55 | |
| 56 | /* cam command regiser */ |
| 57 | #define CAMCMR_AUP 0x01 |
| 58 | #define CAMCMR_AMP (0x01 << 1) |
| 59 | #define CAMCMR_ABP (0x01 << 2) |
| 60 | #define CAMCMR_CCAM (0x01 << 3) |
| 61 | #define CAMCMR_ECMP (0x01 << 4) |
| 62 | #define CAM0EN 0x01 |
| 63 | |
| 64 | /* mac mii controller bit */ |
| 65 | #define MDCCR (0x0a << 20) |
| 66 | #define PHYAD (0x01 << 8) |
| 67 | #define PHYWR (0x01 << 16) |
| 68 | #define PHYBUSY (0x01 << 17) |
| 69 | #define PHYPRESP (0x01 << 18) |
| 70 | #define CAM_ENTRY_SIZE 0x08 |
| 71 | |
| 72 | /* rx and tx status */ |
| 73 | #define TXDS_TXCP (0x01 << 19) |
| 74 | #define RXDS_CRCE (0x01 << 17) |
| 75 | #define RXDS_PTLE (0x01 << 19) |
| 76 | #define RXDS_RXGD (0x01 << 20) |
| 77 | #define RXDS_ALIE (0x01 << 21) |
| 78 | #define RXDS_RP (0x01 << 22) |
| 79 | |
| 80 | /* mac interrupt status*/ |
| 81 | #define MISTA_EXDEF (0x01 << 19) |
| 82 | #define MISTA_TXBERR (0x01 << 24) |
| 83 | #define MISTA_TDU (0x01 << 23) |
| 84 | #define MISTA_RDU (0x01 << 10) |
| 85 | #define MISTA_RXBERR (0x01 << 11) |
| 86 | |
| 87 | #define ENSTART 0x01 |
| 88 | #define ENRXINTR 0x01 |
| 89 | #define ENRXGD (0x01 << 4) |
| 90 | #define ENRXBERR (0x01 << 11) |
| 91 | #define ENTXINTR (0x01 << 16) |
| 92 | #define ENTXCP (0x01 << 18) |
| 93 | #define ENTXABT (0x01 << 21) |
| 94 | #define ENTXBERR (0x01 << 24) |
| 95 | #define ENMDC (0x01 << 19) |
| 96 | #define PHYBUSY (0x01 << 17) |
| 97 | #define MDCCR_VAL 0xa00000 |
| 98 | |
| 99 | /* rx and tx owner bit */ |
| 100 | #define RX_OWEN_DMA (0x01 << 31) |
| 101 | #define RX_OWEN_CPU (~(0x03 << 30)) |
| 102 | #define TX_OWEN_DMA (0x01 << 31) |
| 103 | #define TX_OWEN_CPU (~(0x01 << 31)) |
| 104 | |
| 105 | /* tx frame desc controller bit */ |
| 106 | #define MACTXINTEN 0x04 |
| 107 | #define CRCMODE 0x02 |
| 108 | #define PADDINGMODE 0x01 |
| 109 | |
| 110 | /* fftcr controller bit */ |
| 111 | #define TXTHD (0x03 << 8) |
| 112 | #define BLENGTH (0x01 << 20) |
| 113 | |
| 114 | /* global setting for driver */ |
| 115 | #define RX_DESC_SIZE 50 |
| 116 | #define TX_DESC_SIZE 10 |
| 117 | #define MAX_RBUFF_SZ 0x600 |
| 118 | #define MAX_TBUFF_SZ 0x600 |
| 119 | #define TX_TIMEOUT 50 |
| 120 | #define DELAY 1000 |
| 121 | #define CAM0 0x0 |
| 122 | |
| 123 | static int w90p910_mdio_read(struct net_device *dev, int phy_id, int reg); |
| 124 | |
| 125 | struct w90p910_rxbd { |
| 126 | unsigned int sl; |
| 127 | unsigned int buffer; |
| 128 | unsigned int reserved; |
| 129 | unsigned int next; |
| 130 | }; |
| 131 | |
| 132 | struct w90p910_txbd { |
| 133 | unsigned int mode; |
| 134 | unsigned int buffer; |
| 135 | unsigned int sl; |
| 136 | unsigned int next; |
| 137 | }; |
| 138 | |
| 139 | struct recv_pdesc { |
| 140 | struct w90p910_rxbd desclist[RX_DESC_SIZE]; |
| 141 | char recv_buf[RX_DESC_SIZE][MAX_RBUFF_SZ]; |
| 142 | }; |
| 143 | |
| 144 | struct tran_pdesc { |
| 145 | struct w90p910_txbd desclist[TX_DESC_SIZE]; |
| 146 | char tran_buf[RX_DESC_SIZE][MAX_TBUFF_SZ]; |
| 147 | }; |
| 148 | |
| 149 | struct w90p910_ether { |
| 150 | struct recv_pdesc *rdesc; |
| 151 | struct recv_pdesc *rdesc_phys; |
| 152 | struct tran_pdesc *tdesc; |
| 153 | struct tran_pdesc *tdesc_phys; |
| 154 | struct net_device_stats stats; |
| 155 | struct platform_device *pdev; |
| 156 | struct sk_buff *skb; |
| 157 | struct clk *clk; |
| 158 | struct clk *rmiiclk; |
| 159 | struct mii_if_info mii; |
| 160 | struct timer_list check_timer; |
| 161 | void __iomem *reg; |
| 162 | unsigned int rxirq; |
| 163 | unsigned int txirq; |
| 164 | unsigned int cur_tx; |
| 165 | unsigned int cur_rx; |
| 166 | unsigned int finish_tx; |
| 167 | unsigned int rx_packets; |
| 168 | unsigned int rx_bytes; |
| 169 | unsigned int start_tx_ptr; |
| 170 | unsigned int start_rx_ptr; |
| 171 | unsigned int linkflag; |
| 172 | spinlock_t lock; |
| 173 | }; |
| 174 | |
| 175 | static void update_linkspeed_register(struct net_device *dev, |
| 176 | unsigned int speed, unsigned int duplex) |
| 177 | { |
| 178 | struct w90p910_ether *ether = netdev_priv(dev); |
| 179 | unsigned int val; |
| 180 | |
| 181 | val = __raw_readl(ether->reg + REG_MCMDR); |
| 182 | |
| 183 | if (speed == SPEED_100) { |
| 184 | /* 100 full/half duplex */ |
| 185 | if (duplex == DUPLEX_FULL) { |
| 186 | val |= (MCMDR_OPMOD | MCMDR_FDUP); |
| 187 | } else { |
| 188 | val |= MCMDR_OPMOD; |
| 189 | val &= ~MCMDR_FDUP; |
| 190 | } |
| 191 | } else { |
| 192 | /* 10 full/half duplex */ |
| 193 | if (duplex == DUPLEX_FULL) { |
| 194 | val |= MCMDR_FDUP; |
| 195 | val &= ~MCMDR_OPMOD; |
| 196 | } else { |
| 197 | val &= ~(MCMDR_FDUP | MCMDR_OPMOD); |
| 198 | } |
| 199 | } |
| 200 | |
| 201 | __raw_writel(val, ether->reg + REG_MCMDR); |
| 202 | } |
| 203 | |
| 204 | static void update_linkspeed(struct net_device *dev) |
| 205 | { |
| 206 | struct w90p910_ether *ether = netdev_priv(dev); |
| 207 | struct platform_device *pdev; |
| 208 | unsigned int bmsr, bmcr, lpa, speed, duplex; |
| 209 | |
| 210 | pdev = ether->pdev; |
| 211 | |
| 212 | if (!mii_link_ok(ðer->mii)) { |
| 213 | ether->linkflag = 0x0; |
| 214 | netif_carrier_off(dev); |
| 215 | dev_warn(&pdev->dev, "%s: Link down.\n", dev->name); |
| 216 | return; |
| 217 | } |
| 218 | |
| 219 | if (ether->linkflag == 1) |
| 220 | return; |
| 221 | |
| 222 | bmsr = w90p910_mdio_read(dev, ether->mii.phy_id, MII_BMSR); |
| 223 | bmcr = w90p910_mdio_read(dev, ether->mii.phy_id, MII_BMCR); |
| 224 | |
| 225 | if (bmcr & BMCR_ANENABLE) { |
| 226 | if (!(bmsr & BMSR_ANEGCOMPLETE)) |
| 227 | return; |
| 228 | |
| 229 | lpa = w90p910_mdio_read(dev, ether->mii.phy_id, MII_LPA); |
| 230 | |
| 231 | if ((lpa & LPA_100FULL) || (lpa & LPA_100HALF)) |
| 232 | speed = SPEED_100; |
| 233 | else |
| 234 | speed = SPEED_10; |
| 235 | |
| 236 | if ((lpa & LPA_100FULL) || (lpa & LPA_10FULL)) |
| 237 | duplex = DUPLEX_FULL; |
| 238 | else |
| 239 | duplex = DUPLEX_HALF; |
| 240 | |
| 241 | } else { |
| 242 | speed = (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10; |
| 243 | duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF; |
| 244 | } |
| 245 | |
| 246 | update_linkspeed_register(dev, speed, duplex); |
| 247 | |
| 248 | dev_info(&pdev->dev, "%s: Link now %i-%s\n", dev->name, speed, |
| 249 | (duplex == DUPLEX_FULL) ? "FullDuplex" : "HalfDuplex"); |
| 250 | ether->linkflag = 0x01; |
| 251 | |
| 252 | netif_carrier_on(dev); |
| 253 | } |
| 254 | |
| 255 | static void w90p910_check_link(unsigned long dev_id) |
| 256 | { |
| 257 | struct net_device *dev = (struct net_device *) dev_id; |
| 258 | struct w90p910_ether *ether = netdev_priv(dev); |
| 259 | |
| 260 | update_linkspeed(dev); |
| 261 | mod_timer(ðer->check_timer, jiffies + msecs_to_jiffies(1000)); |
| 262 | } |
| 263 | |
| 264 | static void w90p910_write_cam(struct net_device *dev, |
| 265 | unsigned int x, unsigned char *pval) |
| 266 | { |
| 267 | struct w90p910_ether *ether = netdev_priv(dev); |
| 268 | unsigned int msw, lsw; |
| 269 | |
| 270 | msw = (pval[0] << 24) | (pval[1] << 16) | (pval[2] << 8) | pval[3]; |
| 271 | |
| 272 | lsw = (pval[4] << 24) | (pval[5] << 16); |
| 273 | |
| 274 | __raw_writel(lsw, ether->reg + REG_CAML_BASE + x * CAM_ENTRY_SIZE); |
| 275 | __raw_writel(msw, ether->reg + REG_CAMM_BASE + x * CAM_ENTRY_SIZE); |
| 276 | } |
| 277 | |
| 278 | static void w90p910_init_desc(struct net_device *dev) |
| 279 | { |
| 280 | struct w90p910_ether *ether; |
| 281 | struct w90p910_txbd *tdesc, *tdesc_phys; |
| 282 | struct w90p910_rxbd *rdesc, *rdesc_phys; |
| 283 | unsigned int i, j; |
| 284 | |
| 285 | ether = netdev_priv(dev); |
| 286 | |
| 287 | ether->tdesc = (struct tran_pdesc *) |
| 288 | dma_alloc_coherent(NULL, sizeof(struct tran_pdesc), |
| 289 | (dma_addr_t *) ðer->tdesc_phys, GFP_KERNEL); |
| 290 | |
| 291 | ether->rdesc = (struct recv_pdesc *) |
| 292 | dma_alloc_coherent(NULL, sizeof(struct recv_pdesc), |
| 293 | (dma_addr_t *) ðer->rdesc_phys, GFP_KERNEL); |
| 294 | |
| 295 | for (i = 0; i < TX_DESC_SIZE; i++) { |
| 296 | tdesc = &(ether->tdesc->desclist[i]); |
| 297 | |
| 298 | j = ((i + 1) / TX_DESC_SIZE); |
| 299 | |
| 300 | if (j != 0) { |
| 301 | tdesc_phys = &(ether->tdesc_phys->desclist[0]); |
| 302 | ether->start_tx_ptr = (unsigned int)tdesc_phys; |
| 303 | tdesc->next = (unsigned int)ether->start_tx_ptr; |
| 304 | } else { |
| 305 | tdesc_phys = &(ether->tdesc_phys->desclist[i+1]); |
| 306 | tdesc->next = (unsigned int)tdesc_phys; |
| 307 | } |
| 308 | |
| 309 | tdesc->buffer = (unsigned int)ether->tdesc_phys->tran_buf[i]; |
| 310 | tdesc->sl = 0; |
| 311 | tdesc->mode = 0; |
| 312 | } |
| 313 | |
| 314 | for (i = 0; i < RX_DESC_SIZE; i++) { |
| 315 | rdesc = &(ether->rdesc->desclist[i]); |
| 316 | |
| 317 | j = ((i + 1) / RX_DESC_SIZE); |
| 318 | |
| 319 | if (j != 0) { |
| 320 | rdesc_phys = &(ether->rdesc_phys->desclist[0]); |
| 321 | ether->start_rx_ptr = (unsigned int)rdesc_phys; |
| 322 | rdesc->next = (unsigned int)ether->start_rx_ptr; |
| 323 | } else { |
| 324 | rdesc_phys = &(ether->rdesc_phys->desclist[i+1]); |
| 325 | rdesc->next = (unsigned int)rdesc_phys; |
| 326 | } |
| 327 | |
| 328 | rdesc->sl = RX_OWEN_DMA; |
| 329 | rdesc->buffer = (unsigned int)ether->rdesc_phys->recv_buf[i]; |
| 330 | } |
| 331 | } |
| 332 | |
| 333 | static void w90p910_set_fifo_threshold(struct net_device *dev) |
| 334 | { |
| 335 | struct w90p910_ether *ether = netdev_priv(dev); |
| 336 | unsigned int val; |
| 337 | |
| 338 | val = TXTHD | BLENGTH; |
| 339 | __raw_writel(val, ether->reg + REG_FFTCR); |
| 340 | } |
| 341 | |
| 342 | static void w90p910_return_default_idle(struct net_device *dev) |
| 343 | { |
| 344 | struct w90p910_ether *ether = netdev_priv(dev); |
| 345 | unsigned int val; |
| 346 | |
| 347 | val = __raw_readl(ether->reg + REG_MCMDR); |
| 348 | val |= SWR; |
| 349 | __raw_writel(val, ether->reg + REG_MCMDR); |
| 350 | } |
| 351 | |
| 352 | static void w90p910_trigger_rx(struct net_device *dev) |
| 353 | { |
| 354 | struct w90p910_ether *ether = netdev_priv(dev); |
| 355 | |
| 356 | __raw_writel(ENSTART, ether->reg + REG_RSDR); |
| 357 | } |
| 358 | |
| 359 | static void w90p910_trigger_tx(struct net_device *dev) |
| 360 | { |
| 361 | struct w90p910_ether *ether = netdev_priv(dev); |
| 362 | |
| 363 | __raw_writel(ENSTART, ether->reg + REG_TSDR); |
| 364 | } |
| 365 | |
| 366 | static void w90p910_enable_mac_interrupt(struct net_device *dev) |
| 367 | { |
| 368 | struct w90p910_ether *ether = netdev_priv(dev); |
| 369 | unsigned int val; |
| 370 | |
| 371 | val = ENTXINTR | ENRXINTR | ENRXGD | ENTXCP; |
| 372 | val |= ENTXBERR | ENRXBERR | ENTXABT; |
| 373 | |
| 374 | __raw_writel(val, ether->reg + REG_MIEN); |
| 375 | } |
| 376 | |
| 377 | static void w90p910_get_and_clear_int(struct net_device *dev, |
| 378 | unsigned int *val) |
| 379 | { |
| 380 | struct w90p910_ether *ether = netdev_priv(dev); |
| 381 | |
| 382 | *val = __raw_readl(ether->reg + REG_MISTA); |
| 383 | __raw_writel(*val, ether->reg + REG_MISTA); |
| 384 | } |
| 385 | |
| 386 | static void w90p910_set_global_maccmd(struct net_device *dev) |
| 387 | { |
| 388 | struct w90p910_ether *ether = netdev_priv(dev); |
| 389 | unsigned int val; |
| 390 | |
| 391 | val = __raw_readl(ether->reg + REG_MCMDR); |
| 392 | val |= MCMDR_SPCRC | MCMDR_ENMDC | MCMDR_ACP | ENMDC; |
| 393 | __raw_writel(val, ether->reg + REG_MCMDR); |
| 394 | } |
| 395 | |
| 396 | static void w90p910_enable_cam(struct net_device *dev) |
| 397 | { |
| 398 | struct w90p910_ether *ether = netdev_priv(dev); |
| 399 | unsigned int val; |
| 400 | |
| 401 | w90p910_write_cam(dev, CAM0, dev->dev_addr); |
| 402 | |
| 403 | val = __raw_readl(ether->reg + REG_CAMEN); |
| 404 | val |= CAM0EN; |
| 405 | __raw_writel(val, ether->reg + REG_CAMEN); |
| 406 | } |
| 407 | |
| 408 | static void w90p910_enable_cam_command(struct net_device *dev) |
| 409 | { |
| 410 | struct w90p910_ether *ether = netdev_priv(dev); |
| 411 | unsigned int val; |
| 412 | |
| 413 | val = CAMCMR_ECMP | CAMCMR_ABP | CAMCMR_AMP; |
| 414 | __raw_writel(val, ether->reg + REG_CAMCMR); |
| 415 | } |
| 416 | |
| 417 | static void w90p910_enable_tx(struct net_device *dev, unsigned int enable) |
| 418 | { |
| 419 | struct w90p910_ether *ether = netdev_priv(dev); |
| 420 | unsigned int val; |
| 421 | |
| 422 | val = __raw_readl(ether->reg + REG_MCMDR); |
| 423 | |
| 424 | if (enable) |
| 425 | val |= MCMDR_TXON; |
| 426 | else |
| 427 | val &= ~MCMDR_TXON; |
| 428 | |
| 429 | __raw_writel(val, ether->reg + REG_MCMDR); |
| 430 | } |
| 431 | |
| 432 | static void w90p910_enable_rx(struct net_device *dev, unsigned int enable) |
| 433 | { |
| 434 | struct w90p910_ether *ether = netdev_priv(dev); |
| 435 | unsigned int val; |
| 436 | |
| 437 | val = __raw_readl(ether->reg + REG_MCMDR); |
| 438 | |
| 439 | if (enable) |
| 440 | val |= MCMDR_RXON; |
| 441 | else |
| 442 | val &= ~MCMDR_RXON; |
| 443 | |
| 444 | __raw_writel(val, ether->reg + REG_MCMDR); |
| 445 | } |
| 446 | |
| 447 | static void w90p910_set_curdest(struct net_device *dev) |
| 448 | { |
| 449 | struct w90p910_ether *ether = netdev_priv(dev); |
| 450 | |
| 451 | __raw_writel(ether->start_rx_ptr, ether->reg + REG_RXDLSA); |
| 452 | __raw_writel(ether->start_tx_ptr, ether->reg + REG_TXDLSA); |
| 453 | } |
| 454 | |
| 455 | static void w90p910_reset_mac(struct net_device *dev) |
| 456 | { |
| 457 | struct w90p910_ether *ether = netdev_priv(dev); |
| 458 | |
| 459 | spin_lock(ðer->lock); |
| 460 | |
| 461 | w90p910_enable_tx(dev, 0); |
| 462 | w90p910_enable_rx(dev, 0); |
| 463 | w90p910_set_fifo_threshold(dev); |
| 464 | w90p910_return_default_idle(dev); |
| 465 | |
| 466 | if (!netif_queue_stopped(dev)) |
| 467 | netif_stop_queue(dev); |
| 468 | |
| 469 | w90p910_init_desc(dev); |
| 470 | |
| 471 | dev->trans_start = jiffies; |
| 472 | ether->cur_tx = 0x0; |
| 473 | ether->finish_tx = 0x0; |
| 474 | ether->cur_rx = 0x0; |
| 475 | |
| 476 | w90p910_set_curdest(dev); |
| 477 | w90p910_enable_cam(dev); |
| 478 | w90p910_enable_cam_command(dev); |
| 479 | w90p910_enable_mac_interrupt(dev); |
| 480 | w90p910_enable_tx(dev, 1); |
| 481 | w90p910_enable_rx(dev, 1); |
| 482 | w90p910_trigger_tx(dev); |
| 483 | w90p910_trigger_rx(dev); |
| 484 | |
| 485 | dev->trans_start = jiffies; |
| 486 | |
| 487 | if (netif_queue_stopped(dev)) |
| 488 | netif_wake_queue(dev); |
| 489 | |
| 490 | spin_unlock(ðer->lock); |
| 491 | } |
| 492 | |
| 493 | static void w90p910_mdio_write(struct net_device *dev, |
| 494 | int phy_id, int reg, int data) |
| 495 | { |
| 496 | struct w90p910_ether *ether = netdev_priv(dev); |
| 497 | struct platform_device *pdev; |
| 498 | unsigned int val, i; |
| 499 | |
| 500 | pdev = ether->pdev; |
| 501 | |
| 502 | __raw_writel(data, ether->reg + REG_MIID); |
| 503 | |
| 504 | val = (phy_id << 0x08) | reg; |
| 505 | val |= PHYBUSY | PHYWR | MDCCR_VAL; |
| 506 | __raw_writel(val, ether->reg + REG_MIIDA); |
| 507 | |
| 508 | for (i = 0; i < DELAY; i++) { |
| 509 | if ((__raw_readl(ether->reg + REG_MIIDA) & PHYBUSY) == 0) |
| 510 | break; |
| 511 | } |
| 512 | |
| 513 | if (i == DELAY) |
| 514 | dev_warn(&pdev->dev, "mdio write timed out\n"); |
| 515 | } |
| 516 | |
| 517 | static int w90p910_mdio_read(struct net_device *dev, int phy_id, int reg) |
| 518 | { |
| 519 | struct w90p910_ether *ether = netdev_priv(dev); |
| 520 | struct platform_device *pdev; |
| 521 | unsigned int val, i, data; |
| 522 | |
| 523 | pdev = ether->pdev; |
| 524 | |
| 525 | val = (phy_id << 0x08) | reg; |
| 526 | val |= PHYBUSY | MDCCR_VAL; |
| 527 | __raw_writel(val, ether->reg + REG_MIIDA); |
| 528 | |
| 529 | for (i = 0; i < DELAY; i++) { |
| 530 | if ((__raw_readl(ether->reg + REG_MIIDA) & PHYBUSY) == 0) |
| 531 | break; |
| 532 | } |
| 533 | |
| 534 | if (i == DELAY) { |
| 535 | dev_warn(&pdev->dev, "mdio read timed out\n"); |
| 536 | data = 0xffff; |
| 537 | } else { |
| 538 | data = __raw_readl(ether->reg + REG_MIID); |
| 539 | } |
| 540 | |
| 541 | return data; |
| 542 | } |
| 543 | |
| 544 | static int set_mac_address(struct net_device *dev, void *addr) |
| 545 | { |
| 546 | struct sockaddr *address = addr; |
| 547 | |
| 548 | if (!is_valid_ether_addr(address->sa_data)) |
| 549 | return -EADDRNOTAVAIL; |
| 550 | |
| 551 | memcpy(dev->dev_addr, address->sa_data, dev->addr_len); |
| 552 | w90p910_write_cam(dev, CAM0, dev->dev_addr); |
| 553 | |
| 554 | return 0; |
| 555 | } |
| 556 | |
| 557 | static int w90p910_ether_close(struct net_device *dev) |
| 558 | { |
| 559 | struct w90p910_ether *ether = netdev_priv(dev); |
| 560 | |
| 561 | dma_free_writecombine(NULL, sizeof(struct w90p910_rxbd), |
| 562 | ether->rdesc, (dma_addr_t)ether->rdesc_phys); |
| 563 | dma_free_writecombine(NULL, sizeof(struct w90p910_txbd), |
| 564 | ether->tdesc, (dma_addr_t)ether->tdesc_phys); |
| 565 | |
| 566 | netif_stop_queue(dev); |
| 567 | |
| 568 | del_timer_sync(ðer->check_timer); |
| 569 | clk_disable(ether->rmiiclk); |
| 570 | clk_disable(ether->clk); |
| 571 | |
| 572 | free_irq(ether->txirq, dev); |
| 573 | free_irq(ether->rxirq, dev); |
| 574 | |
| 575 | return 0; |
| 576 | } |
| 577 | |
| 578 | static struct net_device_stats *w90p910_ether_stats(struct net_device *dev) |
| 579 | { |
| 580 | struct w90p910_ether *ether; |
| 581 | |
| 582 | ether = netdev_priv(dev); |
| 583 | |
| 584 | return ðer->stats; |
| 585 | } |
| 586 | |
| 587 | static int w90p910_send_frame(struct net_device *dev, |
| 588 | unsigned char *data, int length) |
| 589 | { |
| 590 | struct w90p910_ether *ether; |
| 591 | struct w90p910_txbd *txbd; |
| 592 | struct platform_device *pdev; |
| 593 | unsigned char *buffer; |
| 594 | |
| 595 | ether = netdev_priv(dev); |
| 596 | pdev = ether->pdev; |
| 597 | |
| 598 | txbd = ðer->tdesc->desclist[ether->cur_tx]; |
| 599 | buffer = ether->tdesc->tran_buf[ether->cur_tx]; |
| 600 | if (length > 1514) { |
| 601 | dev_err(&pdev->dev, "send data %d bytes, check it\n", length); |
| 602 | length = 1514; |
| 603 | } |
| 604 | |
| 605 | txbd->sl = length & 0xFFFF; |
| 606 | |
| 607 | memcpy(buffer, data, length); |
| 608 | |
| 609 | txbd->mode = TX_OWEN_DMA | PADDINGMODE | CRCMODE | MACTXINTEN; |
| 610 | |
| 611 | w90p910_enable_tx(dev, 1); |
| 612 | |
| 613 | w90p910_trigger_tx(dev); |
| 614 | |
| 615 | ether->cur_tx = (ether->cur_tx+1) % TX_DESC_SIZE; |
| 616 | txbd = ðer->tdesc->desclist[ether->cur_tx]; |
| 617 | |
| 618 | dev->trans_start = jiffies; |
| 619 | |
| 620 | if (txbd->mode & TX_OWEN_DMA) |
| 621 | netif_stop_queue(dev); |
| 622 | |
| 623 | return 0; |
| 624 | } |
| 625 | |
| 626 | static int w90p910_ether_start_xmit(struct sk_buff *skb, struct net_device *dev) |
| 627 | { |
| 628 | struct w90p910_ether *ether = netdev_priv(dev); |
| 629 | |
| 630 | if (!(w90p910_send_frame(dev, skb->data, skb->len))) { |
| 631 | ether->skb = skb; |
| 632 | dev_kfree_skb_irq(skb); |
| 633 | return 0; |
| 634 | } |
| 635 | return -1; |
| 636 | } |
| 637 | |
| 638 | static irqreturn_t w90p910_tx_interrupt(int irq, void *dev_id) |
| 639 | { |
| 640 | struct w90p910_ether *ether; |
| 641 | struct w90p910_txbd *txbd; |
| 642 | struct platform_device *pdev; |
| 643 | struct tran_pdesc *tran_pdesc; |
| 644 | struct net_device *dev; |
| 645 | unsigned int cur_entry, entry, status; |
| 646 | |
| 647 | dev = (struct net_device *)dev_id; |
| 648 | ether = netdev_priv(dev); |
| 649 | pdev = ether->pdev; |
| 650 | |
| 651 | spin_lock(ðer->lock); |
| 652 | |
| 653 | w90p910_get_and_clear_int(dev, &status); |
| 654 | |
| 655 | cur_entry = __raw_readl(ether->reg + REG_CTXDSA); |
| 656 | |
| 657 | tran_pdesc = ether->tdesc_phys; |
| 658 | entry = (unsigned int)(&tran_pdesc->desclist[ether->finish_tx]); |
| 659 | |
| 660 | while (entry != cur_entry) { |
| 661 | txbd = ðer->tdesc->desclist[ether->finish_tx]; |
| 662 | |
| 663 | ether->finish_tx = (ether->finish_tx + 1) % TX_DESC_SIZE; |
| 664 | |
| 665 | if (txbd->sl & TXDS_TXCP) { |
| 666 | ether->stats.tx_packets++; |
| 667 | ether->stats.tx_bytes += txbd->sl & 0xFFFF; |
| 668 | } else { |
| 669 | ether->stats.tx_errors++; |
| 670 | } |
| 671 | |
| 672 | txbd->sl = 0x0; |
| 673 | txbd->mode = 0x0; |
| 674 | |
| 675 | if (netif_queue_stopped(dev)) |
| 676 | netif_wake_queue(dev); |
| 677 | |
| 678 | entry = (unsigned int)(&tran_pdesc->desclist[ether->finish_tx]); |
| 679 | } |
| 680 | |
| 681 | if (status & MISTA_EXDEF) { |
| 682 | dev_err(&pdev->dev, "emc defer exceed interrupt\n"); |
| 683 | } else if (status & MISTA_TXBERR) { |
| 684 | dev_err(&pdev->dev, "emc bus error interrupt\n"); |
| 685 | w90p910_reset_mac(dev); |
| 686 | } else if (status & MISTA_TDU) { |
| 687 | if (netif_queue_stopped(dev)) |
| 688 | netif_wake_queue(dev); |
| 689 | } |
| 690 | |
| 691 | spin_unlock(ðer->lock); |
| 692 | |
| 693 | return IRQ_HANDLED; |
| 694 | } |
| 695 | |
| 696 | static void netdev_rx(struct net_device *dev) |
| 697 | { |
| 698 | struct w90p910_ether *ether; |
| 699 | struct w90p910_rxbd *rxbd; |
| 700 | struct platform_device *pdev; |
| 701 | struct recv_pdesc *rdesc_phys; |
| 702 | struct sk_buff *skb; |
| 703 | unsigned char *data; |
| 704 | unsigned int length, status, val, entry; |
| 705 | |
| 706 | ether = netdev_priv(dev); |
| 707 | pdev = ether->pdev; |
| 708 | rdesc_phys = ether->rdesc_phys; |
| 709 | |
| 710 | rxbd = ðer->rdesc->desclist[ether->cur_rx]; |
| 711 | |
| 712 | do { |
| 713 | val = __raw_readl(ether->reg + REG_CRXDSA); |
| 714 | entry = (unsigned int)&rdesc_phys->desclist[ether->cur_rx]; |
| 715 | |
| 716 | if (val == entry) |
| 717 | break; |
| 718 | |
| 719 | status = rxbd->sl; |
| 720 | length = status & 0xFFFF; |
| 721 | |
| 722 | if (status & RXDS_RXGD) { |
| 723 | data = ether->rdesc->recv_buf[ether->cur_rx]; |
| 724 | skb = dev_alloc_skb(length+2); |
| 725 | if (!skb) { |
| 726 | dev_err(&pdev->dev, "get skb buffer error\n"); |
| 727 | ether->stats.rx_dropped++; |
| 728 | return; |
| 729 | } |
| 730 | |
| 731 | skb->dev = dev; |
| 732 | skb_reserve(skb, 2); |
| 733 | skb_put(skb, length); |
| 734 | skb_copy_to_linear_data(skb, data, length); |
| 735 | skb->protocol = eth_type_trans(skb, dev); |
| 736 | ether->stats.rx_packets++; |
| 737 | ether->stats.rx_bytes += length; |
| 738 | netif_rx(skb); |
| 739 | } else { |
| 740 | ether->stats.rx_errors++; |
| 741 | |
| 742 | if (status & RXDS_RP) { |
| 743 | dev_err(&pdev->dev, "rx runt err\n"); |
| 744 | ether->stats.rx_length_errors++; |
| 745 | } else if (status & RXDS_CRCE) { |
| 746 | dev_err(&pdev->dev, "rx crc err\n"); |
| 747 | ether->stats.rx_crc_errors++; |
| 748 | } |
| 749 | |
| 750 | if (status & RXDS_ALIE) { |
| 751 | dev_err(&pdev->dev, "rx aligment err\n"); |
| 752 | ether->stats.rx_frame_errors++; |
| 753 | } else if (status & RXDS_PTLE) { |
| 754 | dev_err(&pdev->dev, "rx longer err\n"); |
| 755 | ether->stats.rx_over_errors++; |
| 756 | } |
| 757 | } |
| 758 | |
| 759 | rxbd->sl = RX_OWEN_DMA; |
| 760 | rxbd->reserved = 0x0; |
| 761 | ether->cur_rx = (ether->cur_rx+1) % RX_DESC_SIZE; |
| 762 | rxbd = ðer->rdesc->desclist[ether->cur_rx]; |
| 763 | |
| 764 | dev->last_rx = jiffies; |
| 765 | } while (1); |
| 766 | } |
| 767 | |
| 768 | static irqreturn_t w90p910_rx_interrupt(int irq, void *dev_id) |
| 769 | { |
| 770 | struct net_device *dev; |
| 771 | struct w90p910_ether *ether; |
| 772 | struct platform_device *pdev; |
| 773 | unsigned int status; |
| 774 | |
| 775 | dev = (struct net_device *)dev_id; |
| 776 | ether = netdev_priv(dev); |
| 777 | pdev = ether->pdev; |
| 778 | |
| 779 | spin_lock(ðer->lock); |
| 780 | |
| 781 | w90p910_get_and_clear_int(dev, &status); |
| 782 | |
| 783 | if (status & MISTA_RDU) { |
| 784 | netdev_rx(dev); |
| 785 | |
| 786 | w90p910_trigger_rx(dev); |
| 787 | |
| 788 | spin_unlock(ðer->lock); |
| 789 | return IRQ_HANDLED; |
| 790 | } else if (status & MISTA_RXBERR) { |
| 791 | dev_err(&pdev->dev, "emc rx bus error\n"); |
| 792 | w90p910_reset_mac(dev); |
| 793 | } |
| 794 | |
| 795 | netdev_rx(dev); |
| 796 | spin_unlock(ðer->lock); |
| 797 | return IRQ_HANDLED; |
| 798 | } |
| 799 | |
| 800 | static int w90p910_ether_open(struct net_device *dev) |
| 801 | { |
| 802 | struct w90p910_ether *ether; |
| 803 | struct platform_device *pdev; |
| 804 | |
| 805 | ether = netdev_priv(dev); |
| 806 | pdev = ether->pdev; |
| 807 | |
| 808 | w90p910_reset_mac(dev); |
| 809 | w90p910_set_fifo_threshold(dev); |
| 810 | w90p910_set_curdest(dev); |
| 811 | w90p910_enable_cam(dev); |
| 812 | w90p910_enable_cam_command(dev); |
| 813 | w90p910_enable_mac_interrupt(dev); |
| 814 | w90p910_set_global_maccmd(dev); |
| 815 | w90p910_enable_rx(dev, 1); |
| 816 | |
| 817 | ether->rx_packets = 0x0; |
| 818 | ether->rx_bytes = 0x0; |
| 819 | |
| 820 | if (request_irq(ether->txirq, w90p910_tx_interrupt, |
| 821 | 0x0, pdev->name, dev)) { |
| 822 | dev_err(&pdev->dev, "register irq tx failed\n"); |
| 823 | return -EAGAIN; |
| 824 | } |
| 825 | |
| 826 | if (request_irq(ether->rxirq, w90p910_rx_interrupt, |
| 827 | 0x0, pdev->name, dev)) { |
| 828 | dev_err(&pdev->dev, "register irq rx failed\n"); |
| 829 | return -EAGAIN; |
| 830 | } |
| 831 | |
| 832 | mod_timer(ðer->check_timer, jiffies + msecs_to_jiffies(1000)); |
| 833 | netif_start_queue(dev); |
| 834 | w90p910_trigger_rx(dev); |
| 835 | |
| 836 | dev_info(&pdev->dev, "%s is OPENED\n", dev->name); |
| 837 | |
| 838 | return 0; |
| 839 | } |
| 840 | |
| 841 | static void w90p910_ether_set_multicast_list(struct net_device *dev) |
| 842 | { |
| 843 | struct w90p910_ether *ether; |
| 844 | unsigned int rx_mode; |
| 845 | |
| 846 | ether = netdev_priv(dev); |
| 847 | |
| 848 | if (dev->flags & IFF_PROMISC) |
| 849 | rx_mode = CAMCMR_AUP | CAMCMR_AMP | CAMCMR_ABP | CAMCMR_ECMP; |
| 850 | else if ((dev->flags & IFF_ALLMULTI) || dev->mc_list) |
| 851 | rx_mode = CAMCMR_AMP | CAMCMR_ABP | CAMCMR_ECMP; |
| 852 | else |
| 853 | rx_mode = CAMCMR_ECMP | CAMCMR_ABP; |
| 854 | __raw_writel(rx_mode, ether->reg + REG_CAMCMR); |
| 855 | } |
| 856 | |
| 857 | static int w90p910_ether_ioctl(struct net_device *dev, |
| 858 | struct ifreq *ifr, int cmd) |
| 859 | { |
| 860 | struct w90p910_ether *ether = netdev_priv(dev); |
| 861 | struct mii_ioctl_data *data = if_mii(ifr); |
| 862 | |
| 863 | return generic_mii_ioctl(ðer->mii, data, cmd, NULL); |
| 864 | } |
| 865 | |
| 866 | static void w90p910_get_drvinfo(struct net_device *dev, |
| 867 | struct ethtool_drvinfo *info) |
| 868 | { |
| 869 | strcpy(info->driver, DRV_MODULE_NAME); |
| 870 | strcpy(info->version, DRV_MODULE_VERSION); |
| 871 | } |
| 872 | |
| 873 | static int w90p910_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
| 874 | { |
| 875 | struct w90p910_ether *ether = netdev_priv(dev); |
| 876 | return mii_ethtool_gset(ðer->mii, cmd); |
| 877 | } |
| 878 | |
| 879 | static int w90p910_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
| 880 | { |
| 881 | struct w90p910_ether *ether = netdev_priv(dev); |
| 882 | return mii_ethtool_sset(ðer->mii, cmd); |
| 883 | } |
| 884 | |
| 885 | static int w90p910_nway_reset(struct net_device *dev) |
| 886 | { |
| 887 | struct w90p910_ether *ether = netdev_priv(dev); |
| 888 | return mii_nway_restart(ðer->mii); |
| 889 | } |
| 890 | |
| 891 | static u32 w90p910_get_link(struct net_device *dev) |
| 892 | { |
| 893 | struct w90p910_ether *ether = netdev_priv(dev); |
| 894 | return mii_link_ok(ðer->mii); |
| 895 | } |
| 896 | |
| 897 | static const struct ethtool_ops w90p910_ether_ethtool_ops = { |
| 898 | .get_settings = w90p910_get_settings, |
| 899 | .set_settings = w90p910_set_settings, |
| 900 | .get_drvinfo = w90p910_get_drvinfo, |
| 901 | .nway_reset = w90p910_nway_reset, |
| 902 | .get_link = w90p910_get_link, |
| 903 | }; |
| 904 | |
| 905 | static const struct net_device_ops w90p910_ether_netdev_ops = { |
| 906 | .ndo_open = w90p910_ether_open, |
| 907 | .ndo_stop = w90p910_ether_close, |
| 908 | .ndo_start_xmit = w90p910_ether_start_xmit, |
| 909 | .ndo_get_stats = w90p910_ether_stats, |
| 910 | .ndo_set_multicast_list = w90p910_ether_set_multicast_list, |
| 911 | .ndo_set_mac_address = set_mac_address, |
| 912 | .ndo_do_ioctl = w90p910_ether_ioctl, |
| 913 | .ndo_validate_addr = eth_validate_addr, |
| 914 | .ndo_change_mtu = eth_change_mtu, |
| 915 | }; |
| 916 | |
| 917 | static void __init get_mac_address(struct net_device *dev) |
| 918 | { |
| 919 | struct w90p910_ether *ether = netdev_priv(dev); |
| 920 | struct platform_device *pdev; |
| 921 | char addr[6]; |
| 922 | |
| 923 | pdev = ether->pdev; |
| 924 | |
| 925 | addr[0] = 0x00; |
| 926 | addr[1] = 0x02; |
| 927 | addr[2] = 0xac; |
| 928 | addr[3] = 0x55; |
| 929 | addr[4] = 0x88; |
| 930 | addr[5] = 0xa8; |
| 931 | |
| 932 | if (is_valid_ether_addr(addr)) |
| 933 | memcpy(dev->dev_addr, &addr, 0x06); |
| 934 | else |
| 935 | dev_err(&pdev->dev, "invalid mac address\n"); |
| 936 | } |
| 937 | |
| 938 | static int w90p910_ether_setup(struct net_device *dev) |
| 939 | { |
| 940 | struct w90p910_ether *ether = netdev_priv(dev); |
| 941 | |
| 942 | ether_setup(dev); |
| 943 | dev->netdev_ops = &w90p910_ether_netdev_ops; |
| 944 | dev->ethtool_ops = &w90p910_ether_ethtool_ops; |
| 945 | |
| 946 | dev->tx_queue_len = 16; |
| 947 | dev->dma = 0x0; |
| 948 | dev->watchdog_timeo = TX_TIMEOUT; |
| 949 | |
| 950 | get_mac_address(dev); |
| 951 | |
| 952 | spin_lock_init(ðer->lock); |
| 953 | |
| 954 | ether->cur_tx = 0x0; |
| 955 | ether->cur_rx = 0x0; |
| 956 | ether->finish_tx = 0x0; |
| 957 | ether->linkflag = 0x0; |
| 958 | ether->mii.phy_id = 0x01; |
| 959 | ether->mii.phy_id_mask = 0x1f; |
| 960 | ether->mii.reg_num_mask = 0x1f; |
| 961 | ether->mii.dev = dev; |
| 962 | ether->mii.mdio_read = w90p910_mdio_read; |
| 963 | ether->mii.mdio_write = w90p910_mdio_write; |
| 964 | |
| 965 | setup_timer(ðer->check_timer, w90p910_check_link, |
| 966 | (unsigned long)dev); |
| 967 | |
| 968 | return 0; |
| 969 | } |
| 970 | |
| 971 | static int __devinit w90p910_ether_probe(struct platform_device *pdev) |
| 972 | { |
| 973 | struct w90p910_ether *ether; |
| 974 | struct net_device *dev; |
| 975 | struct resource *res; |
| 976 | int error; |
| 977 | |
| 978 | dev = alloc_etherdev(sizeof(struct w90p910_ether)); |
| 979 | if (!dev) |
| 980 | return -ENOMEM; |
| 981 | |
| 982 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 983 | if (res == NULL) { |
| 984 | dev_err(&pdev->dev, "failed to get I/O memory\n"); |
| 985 | error = -ENXIO; |
| 986 | goto failed_free; |
| 987 | } |
| 988 | |
| 989 | res = request_mem_region(res->start, resource_size(res), pdev->name); |
| 990 | if (res == NULL) { |
| 991 | dev_err(&pdev->dev, "failed to request I/O memory\n"); |
| 992 | error = -EBUSY; |
| 993 | goto failed_free; |
| 994 | } |
| 995 | |
| 996 | ether = netdev_priv(dev); |
| 997 | |
| 998 | ether->reg = ioremap(res->start, resource_size(res)); |
| 999 | if (ether->reg == NULL) { |
| 1000 | dev_err(&pdev->dev, "failed to remap I/O memory\n"); |
| 1001 | error = -ENXIO; |
| 1002 | goto failed_free_mem; |
| 1003 | } |
| 1004 | |
| 1005 | ether->txirq = platform_get_irq(pdev, 0); |
| 1006 | if (ether->txirq < 0) { |
| 1007 | dev_err(&pdev->dev, "failed to get ether tx irq\n"); |
| 1008 | error = -ENXIO; |
| 1009 | goto failed_free_io; |
| 1010 | } |
| 1011 | |
| 1012 | ether->rxirq = platform_get_irq(pdev, 1); |
| 1013 | if (ether->rxirq < 0) { |
| 1014 | dev_err(&pdev->dev, "failed to get ether rx irq\n"); |
| 1015 | error = -ENXIO; |
| 1016 | goto failed_free_txirq; |
| 1017 | } |
| 1018 | |
| 1019 | platform_set_drvdata(pdev, dev); |
| 1020 | |
| 1021 | ether->clk = clk_get(&pdev->dev, NULL); |
| 1022 | if (IS_ERR(ether->clk)) { |
| 1023 | dev_err(&pdev->dev, "failed to get ether clock\n"); |
| 1024 | error = PTR_ERR(ether->clk); |
| 1025 | goto failed_free_rxirq; |
| 1026 | } |
| 1027 | |
| 1028 | ether->rmiiclk = clk_get(&pdev->dev, "RMII"); |
| 1029 | if (IS_ERR(ether->rmiiclk)) { |
| 1030 | dev_err(&pdev->dev, "failed to get ether clock\n"); |
| 1031 | error = PTR_ERR(ether->rmiiclk); |
| 1032 | goto failed_put_clk; |
| 1033 | } |
| 1034 | |
| 1035 | ether->pdev = pdev; |
| 1036 | |
| 1037 | w90p910_ether_setup(dev); |
| 1038 | |
| 1039 | error = register_netdev(dev); |
| 1040 | if (error != 0) { |
| 1041 | dev_err(&pdev->dev, "Regiter EMC w90p910 FAILED\n"); |
| 1042 | error = -ENODEV; |
| 1043 | goto failed_put_rmiiclk; |
| 1044 | } |
| 1045 | |
| 1046 | return 0; |
| 1047 | failed_put_rmiiclk: |
| 1048 | clk_put(ether->rmiiclk); |
| 1049 | failed_put_clk: |
| 1050 | clk_put(ether->clk); |
| 1051 | failed_free_rxirq: |
| 1052 | free_irq(ether->rxirq, pdev); |
| 1053 | platform_set_drvdata(pdev, NULL); |
| 1054 | failed_free_txirq: |
| 1055 | free_irq(ether->txirq, pdev); |
| 1056 | failed_free_io: |
| 1057 | iounmap(ether->reg); |
| 1058 | failed_free_mem: |
| 1059 | release_mem_region(res->start, resource_size(res)); |
| 1060 | failed_free: |
| 1061 | free_netdev(dev); |
| 1062 | return error; |
| 1063 | } |
| 1064 | |
| 1065 | static int __devexit w90p910_ether_remove(struct platform_device *pdev) |
| 1066 | { |
| 1067 | struct net_device *dev = platform_get_drvdata(pdev); |
| 1068 | struct w90p910_ether *ether = netdev_priv(dev); |
| 1069 | |
| 1070 | unregister_netdev(dev); |
| 1071 | clk_put(ether->rmiiclk); |
| 1072 | clk_put(ether->clk); |
| 1073 | del_timer_sync(ðer->check_timer); |
| 1074 | platform_set_drvdata(pdev, NULL); |
| 1075 | free_netdev(dev); |
| 1076 | return 0; |
| 1077 | } |
| 1078 | |
| 1079 | static struct platform_driver w90p910_ether_driver = { |
| 1080 | .probe = w90p910_ether_probe, |
| 1081 | .remove = __devexit_p(w90p910_ether_remove), |
| 1082 | .driver = { |
| 1083 | .name = "w90p910-emc", |
| 1084 | .owner = THIS_MODULE, |
| 1085 | }, |
| 1086 | }; |
| 1087 | |
| 1088 | static int __init w90p910_ether_init(void) |
| 1089 | { |
| 1090 | return platform_driver_register(&w90p910_ether_driver); |
| 1091 | } |
| 1092 | |
| 1093 | static void __exit w90p910_ether_exit(void) |
| 1094 | { |
| 1095 | platform_driver_unregister(&w90p910_ether_driver); |
| 1096 | } |
| 1097 | |
| 1098 | module_init(w90p910_ether_init); |
| 1099 | module_exit(w90p910_ether_exit); |
| 1100 | |
| 1101 | MODULE_AUTHOR("Wan ZongShun <mcuos.com@gmail.com>"); |
| 1102 | MODULE_DESCRIPTION("w90p910 MAC driver!"); |
| 1103 | MODULE_LICENSE("GPL"); |
| 1104 | MODULE_ALIAS("platform:w90p910-emc"); |
| 1105 | |