Adrian Bunk | b00dc83 | 2008-05-19 16:52:27 -0700 | [diff] [blame] | 1 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2 | * ultra.S: Don't expand these all over the place... |
| 3 | * |
David S. Miller | 93dae5b | 2008-05-19 23:46:00 -0700 | [diff] [blame] | 4 | * Copyright (C) 1997, 2000, 2008 David S. Miller (davem@davemloft.net) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5 | */ |
| 6 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7 | #include <asm/asi.h> |
| 8 | #include <asm/pgtable.h> |
| 9 | #include <asm/page.h> |
| 10 | #include <asm/spitfire.h> |
| 11 | #include <asm/mmu_context.h> |
David S. Miller | 2ef2777 | 2005-08-30 20:21:34 -0700 | [diff] [blame] | 12 | #include <asm/mmu.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13 | #include <asm/pil.h> |
| 14 | #include <asm/head.h> |
| 15 | #include <asm/thread_info.h> |
| 16 | #include <asm/cacheflush.h> |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 17 | #include <asm/hypervisor.h> |
David S. Miller | 93dae5b | 2008-05-19 23:46:00 -0700 | [diff] [blame] | 18 | #include <asm/cpudata.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 19 | |
| 20 | /* Basically, most of the Spitfire vs. Cheetah madness |
| 21 | * has to do with the fact that Cheetah does not support |
| 22 | * IMMU flushes out of the secondary context. Someone needs |
| 23 | * to throw a south lake birthday party for the folks |
| 24 | * in Microelectronics who refused to fix this shit. |
| 25 | */ |
| 26 | |
| 27 | /* This file is meant to be read efficiently by the CPU, not humans. |
| 28 | * Staraj sie tego nikomu nie pierdolnac... |
| 29 | */ |
| 30 | .text |
| 31 | .align 32 |
| 32 | .globl __flush_tlb_mm |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 33 | __flush_tlb_mm: /* 18 insns */ |
| 34 | /* %o0=(ctx & TAG_CONTEXT_BITS), %o1=SECONDARY_CONTEXT */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 35 | ldxa [%o1] ASI_DMMU, %g2 |
| 36 | cmp %g2, %o0 |
| 37 | bne,pn %icc, __spitfire_flush_tlb_mm_slow |
| 38 | mov 0x50, %g3 |
| 39 | stxa %g0, [%g3] ASI_DMMU_DEMAP |
| 40 | stxa %g0, [%g3] ASI_IMMU_DEMAP |
David S. Miller | 4da808c | 2006-01-31 18:33:00 -0800 | [diff] [blame] | 41 | sethi %hi(KERNBASE), %g3 |
| 42 | flush %g3 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 43 | retl |
David S. Miller | 4da808c | 2006-01-31 18:33:00 -0800 | [diff] [blame] | 44 | nop |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 45 | nop |
| 46 | nop |
| 47 | nop |
| 48 | nop |
| 49 | nop |
| 50 | nop |
| 51 | nop |
David S. Miller | 2ef2777 | 2005-08-30 20:21:34 -0700 | [diff] [blame] | 52 | nop |
| 53 | nop |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 54 | |
| 55 | .align 32 |
| 56 | .globl __flush_tlb_pending |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 57 | __flush_tlb_pending: /* 26 insns */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 58 | /* %o0 = context, %o1 = nr, %o2 = vaddrs[] */ |
| 59 | rdpr %pstate, %g7 |
| 60 | sllx %o1, 3, %o1 |
| 61 | andn %g7, PSTATE_IE, %g2 |
| 62 | wrpr %g2, %pstate |
| 63 | mov SECONDARY_CONTEXT, %o4 |
| 64 | ldxa [%o4] ASI_DMMU, %g2 |
| 65 | stxa %o0, [%o4] ASI_DMMU |
| 66 | 1: sub %o1, (1 << 3), %o1 |
| 67 | ldx [%o2 + %o1], %o3 |
| 68 | andcc %o3, 1, %g0 |
| 69 | andn %o3, 1, %o3 |
| 70 | be,pn %icc, 2f |
| 71 | or %o3, 0x10, %o3 |
| 72 | stxa %g0, [%o3] ASI_IMMU_DEMAP |
| 73 | 2: stxa %g0, [%o3] ASI_DMMU_DEMAP |
| 74 | membar #Sync |
| 75 | brnz,pt %o1, 1b |
| 76 | nop |
| 77 | stxa %g2, [%o4] ASI_DMMU |
David S. Miller | 4da808c | 2006-01-31 18:33:00 -0800 | [diff] [blame] | 78 | sethi %hi(KERNBASE), %o4 |
| 79 | flush %o4 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 80 | retl |
| 81 | wrpr %g7, 0x0, %pstate |
David S. Miller | fef43da | 2005-07-05 19:45:24 -0700 | [diff] [blame] | 82 | nop |
David S. Miller | 2ef2777 | 2005-08-30 20:21:34 -0700 | [diff] [blame] | 83 | nop |
| 84 | nop |
| 85 | nop |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 86 | |
| 87 | .align 32 |
| 88 | .globl __flush_tlb_kernel_range |
David S. Miller | 1daef08 | 2006-02-15 20:35:10 -0800 | [diff] [blame] | 89 | __flush_tlb_kernel_range: /* 16 insns */ |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 90 | /* %o0=start, %o1=end */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 91 | cmp %o0, %o1 |
| 92 | be,pn %xcc, 2f |
| 93 | sethi %hi(PAGE_SIZE), %o4 |
| 94 | sub %o1, %o0, %o3 |
| 95 | sub %o3, %o4, %o3 |
| 96 | or %o0, 0x20, %o0 ! Nucleus |
| 97 | 1: stxa %g0, [%o0 + %o3] ASI_DMMU_DEMAP |
| 98 | stxa %g0, [%o0 + %o3] ASI_IMMU_DEMAP |
| 99 | membar #Sync |
| 100 | brnz,pt %o3, 1b |
| 101 | sub %o3, %o4, %o3 |
David S. Miller | 4da808c | 2006-01-31 18:33:00 -0800 | [diff] [blame] | 102 | 2: sethi %hi(KERNBASE), %o3 |
| 103 | flush %o3 |
| 104 | retl |
| 105 | nop |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 106 | nop |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 107 | |
| 108 | __spitfire_flush_tlb_mm_slow: |
| 109 | rdpr %pstate, %g1 |
| 110 | wrpr %g1, PSTATE_IE, %pstate |
| 111 | stxa %o0, [%o1] ASI_DMMU |
| 112 | stxa %g0, [%g3] ASI_DMMU_DEMAP |
| 113 | stxa %g0, [%g3] ASI_IMMU_DEMAP |
| 114 | flush %g6 |
| 115 | stxa %g2, [%o1] ASI_DMMU |
David S. Miller | 4da808c | 2006-01-31 18:33:00 -0800 | [diff] [blame] | 116 | sethi %hi(KERNBASE), %o1 |
| 117 | flush %o1 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 118 | retl |
| 119 | wrpr %g1, 0, %pstate |
| 120 | |
| 121 | /* |
| 122 | * The following code flushes one page_size worth. |
| 123 | */ |
Prasanna S Panchamukhi | 8300516 | 2005-09-06 15:19:31 -0700 | [diff] [blame] | 124 | .section .kprobes.text, "ax" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 125 | .align 32 |
| 126 | .globl __flush_icache_page |
| 127 | __flush_icache_page: /* %o0 = phys_page */ |
| 128 | membar #StoreStore |
| 129 | srlx %o0, PAGE_SHIFT, %o0 |
| 130 | sethi %uhi(PAGE_OFFSET), %g1 |
| 131 | sllx %o0, PAGE_SHIFT, %o0 |
| 132 | sethi %hi(PAGE_SIZE), %g2 |
| 133 | sllx %g1, 32, %g1 |
| 134 | add %o0, %g1, %o0 |
| 135 | 1: subcc %g2, 32, %g2 |
| 136 | bne,pt %icc, 1b |
| 137 | flush %o0 + %g2 |
| 138 | retl |
| 139 | nop |
| 140 | |
| 141 | #ifdef DCACHE_ALIASING_POSSIBLE |
| 142 | |
| 143 | #if (PAGE_SHIFT != 13) |
| 144 | #error only page shift of 13 is supported by dcache flush |
| 145 | #endif |
| 146 | |
| 147 | #define DTAG_MASK 0x3 |
| 148 | |
David S. Miller | c5bd50a | 2005-09-26 16:06:03 -0700 | [diff] [blame] | 149 | /* This routine is Spitfire specific so the hardcoded |
| 150 | * D-cache size and line-size are OK. |
| 151 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 152 | .align 64 |
| 153 | .globl __flush_dcache_page |
| 154 | __flush_dcache_page: /* %o0=kaddr, %o1=flush_icache */ |
| 155 | sethi %uhi(PAGE_OFFSET), %g1 |
| 156 | sllx %g1, 32, %g1 |
David S. Miller | c5bd50a | 2005-09-26 16:06:03 -0700 | [diff] [blame] | 157 | sub %o0, %g1, %o0 ! physical address |
| 158 | srlx %o0, 11, %o0 ! make D-cache TAG |
| 159 | sethi %hi(1 << 14), %o2 ! D-cache size |
| 160 | sub %o2, (1 << 5), %o2 ! D-cache line size |
| 161 | 1: ldxa [%o2] ASI_DCACHE_TAG, %o3 ! load D-cache TAG |
| 162 | andcc %o3, DTAG_MASK, %g0 ! Valid? |
| 163 | be,pn %xcc, 2f ! Nope, branch |
| 164 | andn %o3, DTAG_MASK, %o3 ! Clear valid bits |
| 165 | cmp %o3, %o0 ! TAG match? |
| 166 | bne,pt %xcc, 2f ! Nope, branch |
| 167 | nop |
| 168 | stxa %g0, [%o2] ASI_DCACHE_TAG ! Invalidate TAG |
| 169 | membar #Sync |
| 170 | 2: brnz,pt %o2, 1b |
| 171 | sub %o2, (1 << 5), %o2 ! D-cache line size |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 172 | |
| 173 | /* The I-cache does not snoop local stores so we |
| 174 | * better flush that too when necessary. |
| 175 | */ |
| 176 | brnz,pt %o1, __flush_icache_page |
| 177 | sllx %o0, 11, %o0 |
| 178 | retl |
| 179 | nop |
| 180 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 181 | #endif /* DCACHE_ALIASING_POSSIBLE */ |
| 182 | |
David S. Miller | c5bd50a | 2005-09-26 16:06:03 -0700 | [diff] [blame] | 183 | .previous |
| 184 | |
David S. Miller | 2ef2777 | 2005-08-30 20:21:34 -0700 | [diff] [blame] | 185 | /* Cheetah specific versions, patched at boot time. */ |
David S. Miller | 4da808c | 2006-01-31 18:33:00 -0800 | [diff] [blame] | 186 | __cheetah_flush_tlb_mm: /* 19 insns */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 187 | rdpr %pstate, %g7 |
| 188 | andn %g7, PSTATE_IE, %g2 |
| 189 | wrpr %g2, 0x0, %pstate |
| 190 | wrpr %g0, 1, %tl |
| 191 | mov PRIMARY_CONTEXT, %o2 |
| 192 | mov 0x40, %g3 |
| 193 | ldxa [%o2] ASI_DMMU, %g2 |
David S. Miller | 2ef2777 | 2005-08-30 20:21:34 -0700 | [diff] [blame] | 194 | srlx %g2, CTX_PGSZ1_NUC_SHIFT, %o1 |
| 195 | sllx %o1, CTX_PGSZ1_NUC_SHIFT, %o1 |
| 196 | or %o0, %o1, %o0 /* Preserve nucleus page size fields */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 197 | stxa %o0, [%o2] ASI_DMMU |
| 198 | stxa %g0, [%g3] ASI_DMMU_DEMAP |
| 199 | stxa %g0, [%g3] ASI_IMMU_DEMAP |
| 200 | stxa %g2, [%o2] ASI_DMMU |
David S. Miller | 4da808c | 2006-01-31 18:33:00 -0800 | [diff] [blame] | 201 | sethi %hi(KERNBASE), %o2 |
| 202 | flush %o2 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 203 | wrpr %g0, 0, %tl |
| 204 | retl |
| 205 | wrpr %g7, 0x0, %pstate |
| 206 | |
David S. Miller | 4da808c | 2006-01-31 18:33:00 -0800 | [diff] [blame] | 207 | __cheetah_flush_tlb_pending: /* 27 insns */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 208 | /* %o0 = context, %o1 = nr, %o2 = vaddrs[] */ |
| 209 | rdpr %pstate, %g7 |
| 210 | sllx %o1, 3, %o1 |
| 211 | andn %g7, PSTATE_IE, %g2 |
| 212 | wrpr %g2, 0x0, %pstate |
| 213 | wrpr %g0, 1, %tl |
| 214 | mov PRIMARY_CONTEXT, %o4 |
| 215 | ldxa [%o4] ASI_DMMU, %g2 |
David S. Miller | 2ef2777 | 2005-08-30 20:21:34 -0700 | [diff] [blame] | 216 | srlx %g2, CTX_PGSZ1_NUC_SHIFT, %o3 |
| 217 | sllx %o3, CTX_PGSZ1_NUC_SHIFT, %o3 |
| 218 | or %o0, %o3, %o0 /* Preserve nucleus page size fields */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 219 | stxa %o0, [%o4] ASI_DMMU |
| 220 | 1: sub %o1, (1 << 3), %o1 |
| 221 | ldx [%o2 + %o1], %o3 |
| 222 | andcc %o3, 1, %g0 |
| 223 | be,pn %icc, 2f |
| 224 | andn %o3, 1, %o3 |
| 225 | stxa %g0, [%o3] ASI_IMMU_DEMAP |
| 226 | 2: stxa %g0, [%o3] ASI_DMMU_DEMAP |
David S. Miller | b445e26 | 2005-06-27 15:42:04 -0700 | [diff] [blame] | 227 | membar #Sync |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 228 | brnz,pt %o1, 1b |
David S. Miller | b445e26 | 2005-06-27 15:42:04 -0700 | [diff] [blame] | 229 | nop |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 230 | stxa %g2, [%o4] ASI_DMMU |
David S. Miller | 4da808c | 2006-01-31 18:33:00 -0800 | [diff] [blame] | 231 | sethi %hi(KERNBASE), %o4 |
| 232 | flush %o4 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 233 | wrpr %g0, 0, %tl |
| 234 | retl |
| 235 | wrpr %g7, 0x0, %pstate |
| 236 | |
| 237 | #ifdef DCACHE_ALIASING_POSSIBLE |
David S. Miller | c5bd50a | 2005-09-26 16:06:03 -0700 | [diff] [blame] | 238 | __cheetah_flush_dcache_page: /* 11 insns */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 239 | sethi %uhi(PAGE_OFFSET), %g1 |
| 240 | sllx %g1, 32, %g1 |
| 241 | sub %o0, %g1, %o0 |
| 242 | sethi %hi(PAGE_SIZE), %o4 |
| 243 | 1: subcc %o4, (1 << 5), %o4 |
| 244 | stxa %g0, [%o0 + %o4] ASI_DCACHE_INVALIDATE |
| 245 | membar #Sync |
| 246 | bne,pt %icc, 1b |
| 247 | nop |
| 248 | retl /* I-cache flush never needed on Cheetah, see callers. */ |
| 249 | nop |
| 250 | #endif /* DCACHE_ALIASING_POSSIBLE */ |
| 251 | |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 252 | /* Hypervisor specific versions, patched at boot time. */ |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 253 | __hypervisor_tlb_tl0_error: |
| 254 | save %sp, -192, %sp |
| 255 | mov %i0, %o0 |
| 256 | call hypervisor_tlbop_error |
| 257 | mov %i1, %o1 |
| 258 | ret |
| 259 | restore |
| 260 | |
| 261 | __hypervisor_flush_tlb_mm: /* 10 insns */ |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 262 | mov %o0, %o2 /* ARG2: mmu context */ |
| 263 | mov 0, %o0 /* ARG0: CPU lists unimplemented */ |
| 264 | mov 0, %o1 /* ARG1: CPU lists unimplemented */ |
| 265 | mov HV_MMU_ALL, %o3 /* ARG3: flags */ |
| 266 | mov HV_FAST_MMU_DEMAP_CTX, %o5 |
| 267 | ta HV_FAST_TRAP |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 268 | brnz,pn %o0, __hypervisor_tlb_tl0_error |
| 269 | mov HV_FAST_MMU_DEMAP_CTX, %o1 |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 270 | retl |
| 271 | nop |
| 272 | |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 273 | __hypervisor_flush_tlb_pending: /* 16 insns */ |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 274 | /* %o0 = context, %o1 = nr, %o2 = vaddrs[] */ |
| 275 | sllx %o1, 3, %g1 |
| 276 | mov %o2, %g2 |
| 277 | mov %o0, %g3 |
| 278 | 1: sub %g1, (1 << 3), %g1 |
| 279 | ldx [%g2 + %g1], %o0 /* ARG0: vaddr + IMMU-bit */ |
| 280 | mov %g3, %o1 /* ARG1: mmu context */ |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 281 | mov HV_MMU_ALL, %o2 /* ARG2: flags */ |
| 282 | srlx %o0, PAGE_SHIFT, %o0 |
| 283 | sllx %o0, PAGE_SHIFT, %o0 |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 284 | ta HV_MMU_UNMAP_ADDR_TRAP |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 285 | brnz,pn %o0, __hypervisor_tlb_tl0_error |
| 286 | mov HV_MMU_UNMAP_ADDR_TRAP, %o1 |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 287 | brnz,pt %g1, 1b |
| 288 | nop |
| 289 | retl |
| 290 | nop |
| 291 | |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 292 | __hypervisor_flush_tlb_kernel_range: /* 16 insns */ |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 293 | /* %o0=start, %o1=end */ |
| 294 | cmp %o0, %o1 |
| 295 | be,pn %xcc, 2f |
| 296 | sethi %hi(PAGE_SIZE), %g3 |
| 297 | mov %o0, %g1 |
| 298 | sub %o1, %g1, %g2 |
| 299 | sub %g2, %g3, %g2 |
| 300 | 1: add %g1, %g2, %o0 /* ARG0: virtual address */ |
| 301 | mov 0, %o1 /* ARG1: mmu context */ |
| 302 | mov HV_MMU_ALL, %o2 /* ARG2: flags */ |
| 303 | ta HV_MMU_UNMAP_ADDR_TRAP |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 304 | brnz,pn %o0, __hypervisor_tlb_tl0_error |
| 305 | mov HV_MMU_UNMAP_ADDR_TRAP, %o1 |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 306 | brnz,pt %g2, 1b |
| 307 | sub %g2, %g3, %g2 |
| 308 | 2: retl |
| 309 | nop |
| 310 | |
| 311 | #ifdef DCACHE_ALIASING_POSSIBLE |
| 312 | /* XXX Niagara and friends have an 8K cache, so no aliasing is |
| 313 | * XXX possible, but nothing explicit in the Hypervisor API |
| 314 | * XXX guarantees this. |
| 315 | */ |
| 316 | __hypervisor_flush_dcache_page: /* 2 insns */ |
| 317 | retl |
| 318 | nop |
| 319 | #endif |
| 320 | |
| 321 | tlb_patch_one: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 322 | 1: lduw [%o1], %g1 |
| 323 | stw %g1, [%o0] |
| 324 | flush %o0 |
| 325 | subcc %o2, 1, %o2 |
| 326 | add %o1, 4, %o1 |
| 327 | bne,pt %icc, 1b |
| 328 | add %o0, 4, %o0 |
| 329 | retl |
| 330 | nop |
| 331 | |
| 332 | .globl cheetah_patch_cachetlbops |
| 333 | cheetah_patch_cachetlbops: |
| 334 | save %sp, -128, %sp |
| 335 | |
| 336 | sethi %hi(__flush_tlb_mm), %o0 |
| 337 | or %o0, %lo(__flush_tlb_mm), %o0 |
| 338 | sethi %hi(__cheetah_flush_tlb_mm), %o1 |
| 339 | or %o1, %lo(__cheetah_flush_tlb_mm), %o1 |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 340 | call tlb_patch_one |
David S. Miller | 4da808c | 2006-01-31 18:33:00 -0800 | [diff] [blame] | 341 | mov 19, %o2 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 342 | |
| 343 | sethi %hi(__flush_tlb_pending), %o0 |
| 344 | or %o0, %lo(__flush_tlb_pending), %o0 |
| 345 | sethi %hi(__cheetah_flush_tlb_pending), %o1 |
| 346 | or %o1, %lo(__cheetah_flush_tlb_pending), %o1 |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 347 | call tlb_patch_one |
David S. Miller | 4da808c | 2006-01-31 18:33:00 -0800 | [diff] [blame] | 348 | mov 27, %o2 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 349 | |
| 350 | #ifdef DCACHE_ALIASING_POSSIBLE |
| 351 | sethi %hi(__flush_dcache_page), %o0 |
| 352 | or %o0, %lo(__flush_dcache_page), %o0 |
David S. Miller | c5bd50a | 2005-09-26 16:06:03 -0700 | [diff] [blame] | 353 | sethi %hi(__cheetah_flush_dcache_page), %o1 |
| 354 | or %o1, %lo(__cheetah_flush_dcache_page), %o1 |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 355 | call tlb_patch_one |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 356 | mov 11, %o2 |
| 357 | #endif /* DCACHE_ALIASING_POSSIBLE */ |
| 358 | |
| 359 | ret |
| 360 | restore |
| 361 | |
| 362 | #ifdef CONFIG_SMP |
| 363 | /* These are all called by the slaves of a cross call, at |
| 364 | * trap level 1, with interrupts fully disabled. |
| 365 | * |
| 366 | * Register usage: |
| 367 | * %g5 mm->context (all tlb flushes) |
| 368 | * %g1 address arg 1 (tlb page and range flushes) |
| 369 | * %g7 address arg 2 (tlb range flush only) |
| 370 | * |
David S. Miller | 56fb4df | 2006-02-26 23:24:22 -0800 | [diff] [blame] | 371 | * %g6 scratch 1 |
| 372 | * %g2 scratch 2 |
| 373 | * %g3 scratch 3 |
| 374 | * %g4 scratch 4 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 375 | */ |
| 376 | .align 32 |
| 377 | .globl xcall_flush_tlb_mm |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 378 | xcall_flush_tlb_mm: /* 21 insns */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 379 | mov PRIMARY_CONTEXT, %g2 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 380 | ldxa [%g2] ASI_DMMU, %g3 |
David S. Miller | 2ef2777 | 2005-08-30 20:21:34 -0700 | [diff] [blame] | 381 | srlx %g3, CTX_PGSZ1_NUC_SHIFT, %g4 |
| 382 | sllx %g4, CTX_PGSZ1_NUC_SHIFT, %g4 |
| 383 | or %g5, %g4, %g5 /* Preserve nucleus page size fields */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 384 | stxa %g5, [%g2] ASI_DMMU |
David S. Miller | 2ef2777 | 2005-08-30 20:21:34 -0700 | [diff] [blame] | 385 | mov 0x40, %g4 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 386 | stxa %g0, [%g4] ASI_DMMU_DEMAP |
| 387 | stxa %g0, [%g4] ASI_IMMU_DEMAP |
| 388 | stxa %g3, [%g2] ASI_DMMU |
| 389 | retry |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 390 | nop |
| 391 | nop |
| 392 | nop |
| 393 | nop |
| 394 | nop |
| 395 | nop |
| 396 | nop |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 397 | nop |
| 398 | nop |
| 399 | nop |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 400 | |
| 401 | .globl xcall_flush_tlb_pending |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 402 | xcall_flush_tlb_pending: /* 21 insns */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 403 | /* %g5=context, %g1=nr, %g7=vaddrs[] */ |
| 404 | sllx %g1, 3, %g1 |
| 405 | mov PRIMARY_CONTEXT, %g4 |
| 406 | ldxa [%g4] ASI_DMMU, %g2 |
David S. Miller | 2ef2777 | 2005-08-30 20:21:34 -0700 | [diff] [blame] | 407 | srlx %g2, CTX_PGSZ1_NUC_SHIFT, %g4 |
| 408 | sllx %g4, CTX_PGSZ1_NUC_SHIFT, %g4 |
| 409 | or %g5, %g4, %g5 |
| 410 | mov PRIMARY_CONTEXT, %g4 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 411 | stxa %g5, [%g4] ASI_DMMU |
| 412 | 1: sub %g1, (1 << 3), %g1 |
| 413 | ldx [%g7 + %g1], %g5 |
| 414 | andcc %g5, 0x1, %g0 |
| 415 | be,pn %icc, 2f |
| 416 | |
| 417 | andn %g5, 0x1, %g5 |
| 418 | stxa %g0, [%g5] ASI_IMMU_DEMAP |
| 419 | 2: stxa %g0, [%g5] ASI_DMMU_DEMAP |
| 420 | membar #Sync |
| 421 | brnz,pt %g1, 1b |
| 422 | nop |
| 423 | stxa %g2, [%g4] ASI_DMMU |
| 424 | retry |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 425 | nop |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 426 | |
| 427 | .globl xcall_flush_tlb_kernel_range |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 428 | xcall_flush_tlb_kernel_range: /* 25 insns */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 429 | sethi %hi(PAGE_SIZE - 1), %g2 |
| 430 | or %g2, %lo(PAGE_SIZE - 1), %g2 |
| 431 | andn %g1, %g2, %g1 |
| 432 | andn %g7, %g2, %g7 |
| 433 | sub %g7, %g1, %g3 |
| 434 | add %g2, 1, %g2 |
| 435 | sub %g3, %g2, %g3 |
| 436 | or %g1, 0x20, %g1 ! Nucleus |
| 437 | 1: stxa %g0, [%g1 + %g3] ASI_DMMU_DEMAP |
| 438 | stxa %g0, [%g1 + %g3] ASI_IMMU_DEMAP |
| 439 | membar #Sync |
| 440 | brnz,pt %g3, 1b |
| 441 | sub %g3, %g2, %g3 |
| 442 | retry |
| 443 | nop |
| 444 | nop |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 445 | nop |
| 446 | nop |
| 447 | nop |
| 448 | nop |
| 449 | nop |
| 450 | nop |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 451 | nop |
| 452 | nop |
| 453 | nop |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 454 | |
| 455 | /* This runs in a very controlled environment, so we do |
| 456 | * not need to worry about BH races etc. |
| 457 | */ |
| 458 | .globl xcall_sync_tick |
| 459 | xcall_sync_tick: |
David S. Miller | 45fec05 | 2006-02-05 22:27:28 -0800 | [diff] [blame] | 460 | |
| 461 | 661: rdpr %pstate, %g2 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 462 | wrpr %g2, PSTATE_IG | PSTATE_AG, %pstate |
David S. Miller | df7d6ae | 2006-02-07 00:00:16 -0800 | [diff] [blame] | 463 | .section .sun4v_2insn_patch, "ax" |
David S. Miller | 45fec05 | 2006-02-05 22:27:28 -0800 | [diff] [blame] | 464 | .word 661b |
| 465 | nop |
| 466 | nop |
| 467 | .previous |
| 468 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 469 | rdpr %pil, %g2 |
| 470 | wrpr %g0, 15, %pil |
| 471 | sethi %hi(109f), %g7 |
| 472 | b,pt %xcc, etrap_irq |
| 473 | 109: or %g7, %lo(109b), %g7 |
David S. Miller | 10e2672 | 2006-11-16 13:38:57 -0800 | [diff] [blame] | 474 | #ifdef CONFIG_TRACE_IRQFLAGS |
| 475 | call trace_hardirqs_off |
| 476 | nop |
| 477 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 478 | call smp_synchronize_tick_client |
| 479 | nop |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 480 | b rtrap_xcall |
| 481 | ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1 |
| 482 | |
David S. Miller | 93dae5b | 2008-05-19 23:46:00 -0700 | [diff] [blame] | 483 | #ifdef CONFIG_MAGIC_SYSRQ |
| 484 | .globl xcall_fetch_glob_regs |
| 485 | xcall_fetch_glob_regs: |
| 486 | sethi %hi(global_reg_snapshot), %g1 |
| 487 | or %g1, %lo(global_reg_snapshot), %g1 |
| 488 | __GET_CPUID(%g2) |
| 489 | sllx %g2, 6, %g3 |
| 490 | add %g1, %g3, %g1 |
| 491 | rdpr %tstate, %g7 |
| 492 | stx %g7, [%g1 + GR_SNAP_TSTATE] |
| 493 | rdpr %tpc, %g7 |
| 494 | stx %g7, [%g1 + GR_SNAP_TPC] |
| 495 | rdpr %tnpc, %g7 |
| 496 | stx %g7, [%g1 + GR_SNAP_TNPC] |
| 497 | stx %o7, [%g1 + GR_SNAP_O7] |
| 498 | stx %i7, [%g1 + GR_SNAP_I7] |
David S. Miller | 5afe273 | 2008-07-30 21:57:59 -0700 | [diff] [blame] | 499 | /* Don't try this at home kids... */ |
| 500 | rdpr %cwp, %g2 |
| 501 | sub %g2, 1, %g7 |
| 502 | wrpr %g7, %cwp |
| 503 | mov %i7, %g7 |
| 504 | wrpr %g2, %cwp |
| 505 | stx %g7, [%g1 + GR_SNAP_RPC] |
David S. Miller | 93dae5b | 2008-05-19 23:46:00 -0700 | [diff] [blame] | 506 | sethi %hi(trap_block), %g7 |
| 507 | or %g7, %lo(trap_block), %g7 |
| 508 | sllx %g2, TRAP_BLOCK_SZ_SHIFT, %g2 |
| 509 | add %g7, %g2, %g7 |
| 510 | ldx [%g7 + TRAP_PER_CPU_THREAD], %g3 |
| 511 | membar #StoreStore |
| 512 | stx %g3, [%g1 + GR_SNAP_THREAD] |
| 513 | retry |
| 514 | #endif /* CONFIG_MAGIC_SYSRQ */ |
| 515 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 516 | #ifdef DCACHE_ALIASING_POSSIBLE |
| 517 | .align 32 |
| 518 | .globl xcall_flush_dcache_page_cheetah |
| 519 | xcall_flush_dcache_page_cheetah: /* %g1 == physical page address */ |
| 520 | sethi %hi(PAGE_SIZE), %g3 |
| 521 | 1: subcc %g3, (1 << 5), %g3 |
| 522 | stxa %g0, [%g1 + %g3] ASI_DCACHE_INVALIDATE |
| 523 | membar #Sync |
| 524 | bne,pt %icc, 1b |
| 525 | nop |
| 526 | retry |
| 527 | nop |
| 528 | #endif /* DCACHE_ALIASING_POSSIBLE */ |
| 529 | |
| 530 | .globl xcall_flush_dcache_page_spitfire |
| 531 | xcall_flush_dcache_page_spitfire: /* %g1 == physical page address |
| 532 | %g7 == kernel page virtual address |
| 533 | %g5 == (page->mapping != NULL) */ |
| 534 | #ifdef DCACHE_ALIASING_POSSIBLE |
| 535 | srlx %g1, (13 - 2), %g1 ! Form tag comparitor |
| 536 | sethi %hi(L1DCACHE_SIZE), %g3 ! D$ size == 16K |
| 537 | sub %g3, (1 << 5), %g3 ! D$ linesize == 32 |
| 538 | 1: ldxa [%g3] ASI_DCACHE_TAG, %g2 |
| 539 | andcc %g2, 0x3, %g0 |
| 540 | be,pn %xcc, 2f |
| 541 | andn %g2, 0x3, %g2 |
| 542 | cmp %g2, %g1 |
| 543 | |
| 544 | bne,pt %xcc, 2f |
| 545 | nop |
| 546 | stxa %g0, [%g3] ASI_DCACHE_TAG |
| 547 | membar #Sync |
| 548 | 2: cmp %g3, 0 |
| 549 | bne,pt %xcc, 1b |
| 550 | sub %g3, (1 << 5), %g3 |
| 551 | |
| 552 | brz,pn %g5, 2f |
| 553 | #endif /* DCACHE_ALIASING_POSSIBLE */ |
| 554 | sethi %hi(PAGE_SIZE), %g3 |
| 555 | |
| 556 | 1: flush %g7 |
| 557 | subcc %g3, (1 << 5), %g3 |
| 558 | bne,pt %icc, 1b |
| 559 | add %g7, (1 << 5), %g7 |
| 560 | |
| 561 | 2: retry |
| 562 | nop |
| 563 | nop |
| 564 | |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 565 | /* %g5: error |
| 566 | * %g6: tlb op |
| 567 | */ |
| 568 | __hypervisor_tlb_xcall_error: |
| 569 | mov %g5, %g4 |
| 570 | mov %g6, %g5 |
| 571 | ba,pt %xcc, etrap |
| 572 | rd %pc, %g7 |
| 573 | mov %l4, %o0 |
| 574 | call hypervisor_tlbop_error_xcall |
| 575 | mov %l5, %o1 |
David S. Miller | 7697daa | 2008-04-24 03:15:22 -0700 | [diff] [blame] | 576 | ba,a,pt %xcc, rtrap |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 577 | |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 578 | .globl __hypervisor_xcall_flush_tlb_mm |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 579 | __hypervisor_xcall_flush_tlb_mm: /* 21 insns */ |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 580 | /* %g5=ctx, g1,g2,g3,g4,g7=scratch, %g6=unusable */ |
| 581 | mov %o0, %g2 |
| 582 | mov %o1, %g3 |
| 583 | mov %o2, %g4 |
| 584 | mov %o3, %g1 |
| 585 | mov %o5, %g7 |
| 586 | clr %o0 /* ARG0: CPU lists unimplemented */ |
| 587 | clr %o1 /* ARG1: CPU lists unimplemented */ |
| 588 | mov %g5, %o2 /* ARG2: mmu context */ |
| 589 | mov HV_MMU_ALL, %o3 /* ARG3: flags */ |
| 590 | mov HV_FAST_MMU_DEMAP_CTX, %o5 |
| 591 | ta HV_FAST_TRAP |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 592 | mov HV_FAST_MMU_DEMAP_CTX, %g6 |
| 593 | brnz,pn %o0, __hypervisor_tlb_xcall_error |
| 594 | mov %o0, %g5 |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 595 | mov %g2, %o0 |
| 596 | mov %g3, %o1 |
| 597 | mov %g4, %o2 |
| 598 | mov %g1, %o3 |
| 599 | mov %g7, %o5 |
| 600 | membar #Sync |
| 601 | retry |
| 602 | |
| 603 | .globl __hypervisor_xcall_flush_tlb_pending |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 604 | __hypervisor_xcall_flush_tlb_pending: /* 21 insns */ |
| 605 | /* %g5=ctx, %g1=nr, %g7=vaddrs[], %g2,%g3,%g4,g6=scratch */ |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 606 | sllx %g1, 3, %g1 |
| 607 | mov %o0, %g2 |
| 608 | mov %o1, %g3 |
| 609 | mov %o2, %g4 |
| 610 | 1: sub %g1, (1 << 3), %g1 |
| 611 | ldx [%g7 + %g1], %o0 /* ARG0: virtual address */ |
| 612 | mov %g5, %o1 /* ARG1: mmu context */ |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 613 | mov HV_MMU_ALL, %o2 /* ARG2: flags */ |
| 614 | srlx %o0, PAGE_SHIFT, %o0 |
| 615 | sllx %o0, PAGE_SHIFT, %o0 |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 616 | ta HV_MMU_UNMAP_ADDR_TRAP |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 617 | mov HV_MMU_UNMAP_ADDR_TRAP, %g6 |
| 618 | brnz,a,pn %o0, __hypervisor_tlb_xcall_error |
| 619 | mov %o0, %g5 |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 620 | brnz,pt %g1, 1b |
| 621 | nop |
| 622 | mov %g2, %o0 |
| 623 | mov %g3, %o1 |
| 624 | mov %g4, %o2 |
| 625 | membar #Sync |
| 626 | retry |
| 627 | |
| 628 | .globl __hypervisor_xcall_flush_tlb_kernel_range |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 629 | __hypervisor_xcall_flush_tlb_kernel_range: /* 25 insns */ |
| 630 | /* %g1=start, %g7=end, g2,g3,g4,g5,g6=scratch */ |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 631 | sethi %hi(PAGE_SIZE - 1), %g2 |
| 632 | or %g2, %lo(PAGE_SIZE - 1), %g2 |
| 633 | andn %g1, %g2, %g1 |
| 634 | andn %g7, %g2, %g7 |
| 635 | sub %g7, %g1, %g3 |
| 636 | add %g2, 1, %g2 |
| 637 | sub %g3, %g2, %g3 |
| 638 | mov %o0, %g2 |
| 639 | mov %o1, %g4 |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 640 | mov %o2, %g7 |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 641 | 1: add %g1, %g3, %o0 /* ARG0: virtual address */ |
| 642 | mov 0, %o1 /* ARG1: mmu context */ |
| 643 | mov HV_MMU_ALL, %o2 /* ARG2: flags */ |
| 644 | ta HV_MMU_UNMAP_ADDR_TRAP |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 645 | mov HV_MMU_UNMAP_ADDR_TRAP, %g6 |
| 646 | brnz,pn %o0, __hypervisor_tlb_xcall_error |
| 647 | mov %o0, %g5 |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 648 | sethi %hi(PAGE_SIZE), %o2 |
| 649 | brnz,pt %g3, 1b |
| 650 | sub %g3, %o2, %g3 |
| 651 | mov %g2, %o0 |
| 652 | mov %g4, %o1 |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 653 | mov %g7, %o2 |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 654 | membar #Sync |
| 655 | retry |
| 656 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 657 | /* These just get rescheduled to PIL vectors. */ |
| 658 | .globl xcall_call_function |
| 659 | xcall_call_function: |
| 660 | wr %g0, (1 << PIL_SMP_CALL_FUNC), %set_softint |
| 661 | retry |
| 662 | |
David S. Miller | d172ad1 | 2008-07-17 23:44:50 -0700 | [diff] [blame] | 663 | .globl xcall_call_function_single |
| 664 | xcall_call_function_single: |
| 665 | wr %g0, (1 << PIL_SMP_CALL_FUNC_SNGL), %set_softint |
| 666 | retry |
| 667 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 668 | .globl xcall_receive_signal |
| 669 | xcall_receive_signal: |
| 670 | wr %g0, (1 << PIL_SMP_RECEIVE_SIGNAL), %set_softint |
| 671 | retry |
| 672 | |
| 673 | .globl xcall_capture |
| 674 | xcall_capture: |
| 675 | wr %g0, (1 << PIL_SMP_CAPTURE), %set_softint |
| 676 | retry |
| 677 | |
David S. Miller | ee29074 | 2006-03-06 22:50:44 -0800 | [diff] [blame] | 678 | .globl xcall_new_mmu_context_version |
| 679 | xcall_new_mmu_context_version: |
| 680 | wr %g0, (1 << PIL_SMP_CTX_NEW_VERSION), %set_softint |
| 681 | retry |
| 682 | |
David S. Miller | e2fdd7f | 2008-04-29 02:38:50 -0700 | [diff] [blame] | 683 | #ifdef CONFIG_KGDB |
| 684 | .globl xcall_kgdb_capture |
| 685 | xcall_kgdb_capture: |
| 686 | 661: rdpr %pstate, %g2 |
| 687 | wrpr %g2, PSTATE_IG | PSTATE_AG, %pstate |
| 688 | .section .sun4v_2insn_patch, "ax" |
| 689 | .word 661b |
| 690 | nop |
| 691 | nop |
| 692 | .previous |
| 693 | |
| 694 | rdpr %pil, %g2 |
| 695 | wrpr %g0, 15, %pil |
| 696 | sethi %hi(109f), %g7 |
| 697 | ba,pt %xcc, etrap_irq |
| 698 | 109: or %g7, %lo(109b), %g7 |
| 699 | #ifdef CONFIG_TRACE_IRQFLAGS |
| 700 | call trace_hardirqs_off |
| 701 | nop |
| 702 | #endif |
| 703 | call smp_kgdb_capture_client |
| 704 | add %sp, PTREGS_OFF, %o0 |
| 705 | /* Has to be a non-v9 branch due to the large distance. */ |
| 706 | ba rtrap_xcall |
| 707 | ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1 |
| 708 | #endif |
| 709 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 710 | #endif /* CONFIG_SMP */ |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 711 | |
| 712 | |
| 713 | .globl hypervisor_patch_cachetlbops |
| 714 | hypervisor_patch_cachetlbops: |
| 715 | save %sp, -128, %sp |
| 716 | |
| 717 | sethi %hi(__flush_tlb_mm), %o0 |
| 718 | or %o0, %lo(__flush_tlb_mm), %o0 |
| 719 | sethi %hi(__hypervisor_flush_tlb_mm), %o1 |
| 720 | or %o1, %lo(__hypervisor_flush_tlb_mm), %o1 |
| 721 | call tlb_patch_one |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 722 | mov 10, %o2 |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 723 | |
| 724 | sethi %hi(__flush_tlb_pending), %o0 |
| 725 | or %o0, %lo(__flush_tlb_pending), %o0 |
| 726 | sethi %hi(__hypervisor_flush_tlb_pending), %o1 |
| 727 | or %o1, %lo(__hypervisor_flush_tlb_pending), %o1 |
| 728 | call tlb_patch_one |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 729 | mov 16, %o2 |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 730 | |
| 731 | sethi %hi(__flush_tlb_kernel_range), %o0 |
| 732 | or %o0, %lo(__flush_tlb_kernel_range), %o0 |
| 733 | sethi %hi(__hypervisor_flush_tlb_kernel_range), %o1 |
| 734 | or %o1, %lo(__hypervisor_flush_tlb_kernel_range), %o1 |
| 735 | call tlb_patch_one |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 736 | mov 16, %o2 |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 737 | |
| 738 | #ifdef DCACHE_ALIASING_POSSIBLE |
| 739 | sethi %hi(__flush_dcache_page), %o0 |
| 740 | or %o0, %lo(__flush_dcache_page), %o0 |
| 741 | sethi %hi(__hypervisor_flush_dcache_page), %o1 |
| 742 | or %o1, %lo(__hypervisor_flush_dcache_page), %o1 |
| 743 | call tlb_patch_one |
| 744 | mov 2, %o2 |
| 745 | #endif /* DCACHE_ALIASING_POSSIBLE */ |
| 746 | |
| 747 | #ifdef CONFIG_SMP |
| 748 | sethi %hi(xcall_flush_tlb_mm), %o0 |
| 749 | or %o0, %lo(xcall_flush_tlb_mm), %o0 |
| 750 | sethi %hi(__hypervisor_xcall_flush_tlb_mm), %o1 |
| 751 | or %o1, %lo(__hypervisor_xcall_flush_tlb_mm), %o1 |
| 752 | call tlb_patch_one |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 753 | mov 21, %o2 |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 754 | |
| 755 | sethi %hi(xcall_flush_tlb_pending), %o0 |
| 756 | or %o0, %lo(xcall_flush_tlb_pending), %o0 |
| 757 | sethi %hi(__hypervisor_xcall_flush_tlb_pending), %o1 |
| 758 | or %o1, %lo(__hypervisor_xcall_flush_tlb_pending), %o1 |
| 759 | call tlb_patch_one |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 760 | mov 21, %o2 |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 761 | |
| 762 | sethi %hi(xcall_flush_tlb_kernel_range), %o0 |
| 763 | or %o0, %lo(xcall_flush_tlb_kernel_range), %o0 |
| 764 | sethi %hi(__hypervisor_xcall_flush_tlb_kernel_range), %o1 |
| 765 | or %o1, %lo(__hypervisor_xcall_flush_tlb_kernel_range), %o1 |
| 766 | call tlb_patch_one |
David S. Miller | 2a3a5f5 | 2006-02-26 19:31:49 -0800 | [diff] [blame] | 767 | mov 25, %o2 |
David S. Miller | 52bf082 | 2006-02-04 03:08:37 -0800 | [diff] [blame] | 768 | #endif /* CONFIG_SMP */ |
| 769 | |
| 770 | ret |
| 771 | restore |