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Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001/* bnx2x_hsi.h: Broadcom Everest network driver.
2 *
Eliezer Tamirf1410642008-02-28 11:51:50 -08003 * Copyright (c) 2007-2008 Broadcom Corporation
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 */
9
10
Eliezer Tamirf1410642008-02-28 11:51:50 -080011#define PORT_0 0
12#define PORT_1 1
13#define PORT_MAX 2
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020014
15/****************************************************************************
16 * Shared HW configuration *
17 ****************************************************************************/
18struct shared_hw_cfg { /* NVRAM Offset */
19 /* Up to 16 bytes of NULL-terminated string */
20 u8 part_num[16]; /* 0x104 */
21
22 u32 config; /* 0x114 */
23#define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001
24#define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0
25#define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000
26#define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001
27#define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN 0x00000002
28
29#define SHARED_HW_CFG_PORT_SWAP 0x00000004
30
31#define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008
32
33#define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700
34#define SHARED_HW_CFG_MFW_SELECT_SHIFT 8
35 /* Whatever MFW found in NVM
36 (if multiple found, priority order is: NC-SI, UMP, IPMI) */
37#define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000
38#define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100
39#define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200
40#define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300
41 /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI
42 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
43#define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400
44 /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI
45 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
46#define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500
47 /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP
48 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
49#define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600
50
51#define SHARED_HW_CFG_LED_MODE_MASK 0x000f0000
52#define SHARED_HW_CFG_LED_MODE_SHIFT 16
53#define SHARED_HW_CFG_LED_MAC1 0x00000000
54#define SHARED_HW_CFG_LED_PHY1 0x00010000
55#define SHARED_HW_CFG_LED_PHY2 0x00020000
56#define SHARED_HW_CFG_LED_PHY3 0x00030000
57#define SHARED_HW_CFG_LED_MAC2 0x00040000
58#define SHARED_HW_CFG_LED_PHY4 0x00050000
59#define SHARED_HW_CFG_LED_PHY5 0x00060000
60#define SHARED_HW_CFG_LED_PHY6 0x00070000
61#define SHARED_HW_CFG_LED_MAC3 0x00080000
62#define SHARED_HW_CFG_LED_PHY7 0x00090000
63#define SHARED_HW_CFG_LED_PHY9 0x000a0000
64#define SHARED_HW_CFG_LED_PHY11 0x000b0000
65#define SHARED_HW_CFG_LED_MAC4 0x000c0000
66#define SHARED_HW_CFG_LED_PHY8 0x000d0000
67
68#define SHARED_HW_CFG_AN_ENABLE_MASK 0x3f000000
69#define SHARED_HW_CFG_AN_ENABLE_SHIFT 24
70#define SHARED_HW_CFG_AN_ENABLE_CL37 0x01000000
71#define SHARED_HW_CFG_AN_ENABLE_CL73 0x02000000
72#define SHARED_HW_CFG_AN_ENABLE_BAM 0x04000000
73#define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 0x08000000
74#define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 0x10000000
75#define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 0x20000000
76
77 u32 config2; /* 0x118 */
78 /* one time auto detect grace period (in sec) */
79#define SHARED_HW_CFG_GRACE_PERIOD_MASK 0x000000ff
80#define SHARED_HW_CFG_GRACE_PERIOD_SHIFT 0
81
82#define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100
83
84 /* The default value for the core clock is 250MHz and it is
85 achieved by setting the clock change to 4 */
86#define SHARED_HW_CFG_CLOCK_CHANGE_MASK 0x00000e00
87#define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT 9
88
89#define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000
90#define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000
91
Eliezer Tamirf1410642008-02-28 11:51:50 -080092#define SHARED_HW_CFG_HIDE_PORT1 0x00002000
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020093
94 u32 power_dissipated; /* 0x11c */
95#define SHARED_HW_CFG_POWER_DIS_CMN_MASK 0xff000000
96#define SHARED_HW_CFG_POWER_DIS_CMN_SHIFT 24
97
98#define SHARED_HW_CFG_POWER_MGNT_SCALE_MASK 0x00ff0000
99#define SHARED_HW_CFG_POWER_MGNT_SCALE_SHIFT 16
100#define SHARED_HW_CFG_POWER_MGNT_UNKNOWN_SCALE 0x00000000
101#define SHARED_HW_CFG_POWER_MGNT_DOT_1_WATT 0x00010000
102#define SHARED_HW_CFG_POWER_MGNT_DOT_01_WATT 0x00020000
103#define SHARED_HW_CFG_POWER_MGNT_DOT_001_WATT 0x00030000
104
105 u32 ump_nc_si_config; /* 0x120 */
106#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003
107#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0
108#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000
109#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001
110#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000
111#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002
112
113#define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK 0x00000f00
114#define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT 8
115
116#define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK 0x00ff0000
117#define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT 16
118#define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE 0x00000000
119#define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000
120
121 u32 board; /* 0x124 */
122#define SHARED_HW_CFG_BOARD_TYPE_MASK 0x0000ffff
123#define SHARED_HW_CFG_BOARD_TYPE_SHIFT 0
124#define SHARED_HW_CFG_BOARD_TYPE_NONE 0x00000000
125#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1000 0x00000001
126#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1001 0x00000002
127#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1002G 0x00000003
128#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1004G 0x00000004
129#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1007G 0x00000005
130#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1015G 0x00000006
131#define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1020G 0x00000007
132#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1003G 0x00000008
Eliezer Tamirf1410642008-02-28 11:51:50 -0800133#define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G 0x00000009
134#define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1021G 0x0000000a
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700135#define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1023G 0x0000000b
136#define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1033G 0x0000000c
137#define SHARED_HW_CFG_BOARD_TYPE_BCM957711T1101 0x0000000d
138#define SHARED_HW_CFG_BOARD_TYPE_BCM957711ET1201 0x0000000e
139#define SHARED_HW_CFG_BOARD_TYPE_BCM957711A1133G 0x0000000f
140#define SHARED_HW_CFG_BOARD_TYPE_BCM957711EA1233G 0x00000010
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200141
142#define SHARED_HW_CFG_BOARD_VER_MASK 0xffff0000
143#define SHARED_HW_CFG_BOARD_VER_SHIFT 16
144#define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0xf0000000
145#define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 28
146#define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0x0f000000
147#define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 24
148#define SHARED_HW_CFG_BOARD_REV_MASK 0x00ff0000
149#define SHARED_HW_CFG_BOARD_REV_SHIFT 16
150
151 u32 reserved; /* 0x128 */
152
153};
154
Eliezer Tamirf1410642008-02-28 11:51:50 -0800155
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200156/****************************************************************************
157 * Port HW configuration *
158 ****************************************************************************/
Eliezer Tamirf1410642008-02-28 11:51:50 -0800159struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200160
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200161 u32 pci_id;
162#define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xffff0000
163#define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000ffff
164
165 u32 pci_sub_id;
166#define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xffff0000
167#define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000ffff
168
169 u32 power_dissipated;
170#define PORT_HW_CFG_POWER_DIS_D3_MASK 0xff000000
171#define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24
172#define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00ff0000
173#define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16
174#define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000ff00
175#define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8
176#define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000ff
177#define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0
178
179 u32 power_consumed;
180#define PORT_HW_CFG_POWER_CONS_D3_MASK 0xff000000
181#define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24
182#define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00ff0000
183#define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16
184#define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000ff00
185#define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8
186#define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000ff
187#define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0
188
189 u32 mac_upper;
190#define PORT_HW_CFG_UPPERMAC_MASK 0x0000ffff
191#define PORT_HW_CFG_UPPERMAC_SHIFT 0
192 u32 mac_lower;
193
194 u32 iscsi_mac_upper; /* Upper 16 bits are always zeroes */
195 u32 iscsi_mac_lower;
196
197 u32 rdma_mac_upper; /* Upper 16 bits are always zeroes */
198 u32 rdma_mac_lower;
199
200 u32 serdes_config;
201 /* for external PHY, or forced mode or during AN */
202#define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0xffff0000
203#define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 16
204
205#define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0x0000ffff
206#define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 0
207
208 u16 serdes_tx_driver_pre_emphasis[16];
209 u16 serdes_rx_driver_equalizer[16];
210
211 u32 xgxs_config_lane0;
212 u32 xgxs_config_lane1;
213 u32 xgxs_config_lane2;
214 u32 xgxs_config_lane3;
215 /* for external PHY, or forced mode or during AN */
216#define PORT_HW_CFG_XGXS_TX_DRV_PRE_EMPHASIS_MASK 0xffff0000
217#define PORT_HW_CFG_XGXS_TX_DRV_PRE_EMPHASIS_SHIFT 16
218
219#define PORT_HW_CFG_XGXS_RX_DRV_EQUALIZER_MASK 0x0000ffff
220#define PORT_HW_CFG_XGXS_RX_DRV_EQUALIZER_SHIFT 0
221
222 u16 xgxs_tx_driver_pre_emphasis_lane0[16];
223 u16 xgxs_tx_driver_pre_emphasis_lane1[16];
224 u16 xgxs_tx_driver_pre_emphasis_lane2[16];
225 u16 xgxs_tx_driver_pre_emphasis_lane3[16];
226
227 u16 xgxs_rx_driver_equalizer_lane0[16];
228 u16 xgxs_rx_driver_equalizer_lane1[16];
229 u16 xgxs_rx_driver_equalizer_lane2[16];
230 u16 xgxs_rx_driver_equalizer_lane3[16];
231
232 u32 lane_config;
233#define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000ffff
234#define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0
235#define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000ff
236#define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0
237#define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000ff00
238#define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8
239#define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000c000
240#define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14
241 /* AN and forced */
242#define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b
243 /* forced only */
244#define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4
245 /* forced only */
246#define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8
247 /* forced only */
248#define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4
249
250 u32 external_phy_config;
251#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xff000000
252#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24
253#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000
254#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000
255#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000
256
257#define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00ff0000
258#define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16
259
260#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000ff00
261#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8
262#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000
263#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100
264#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200
265#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300
266#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400
267#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500
268#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8276 0x00000600
269#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700
Eliezer Tamirf1410642008-02-28 11:51:50 -0800270#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800
271#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200272#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00
273
274#define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000ff
275#define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0
276
277 u32 speed_capability_mask;
278#define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xffff0000
279#define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16
280#define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000
281#define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000
282#define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000
283#define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000
284#define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000
285#define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000
286#define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000
287#define PORT_HW_CFG_SPEED_CAPABILITY_D0_12G 0x00800000
288#define PORT_HW_CFG_SPEED_CAPABILITY_D0_12_5G 0x01000000
289#define PORT_HW_CFG_SPEED_CAPABILITY_D0_13G 0x02000000
290#define PORT_HW_CFG_SPEED_CAPABILITY_D0_15G 0x04000000
291#define PORT_HW_CFG_SPEED_CAPABILITY_D0_16G 0x08000000
292#define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000
293
294#define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000ffff
295#define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0
296#define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001
297#define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002
298#define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004
299#define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008
300#define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010
301#define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020
302#define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040
303#define PORT_HW_CFG_SPEED_CAPABILITY_D3_12G 0x00000080
304#define PORT_HW_CFG_SPEED_CAPABILITY_D3_12_5G 0x00000100
305#define PORT_HW_CFG_SPEED_CAPABILITY_D3_13G 0x00000200
306#define PORT_HW_CFG_SPEED_CAPABILITY_D3_15G 0x00000400
307#define PORT_HW_CFG_SPEED_CAPABILITY_D3_16G 0x00000800
308#define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000
309
310 u32 reserved[2];
311
312};
313
Eliezer Tamirf1410642008-02-28 11:51:50 -0800314
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200315/****************************************************************************
316 * Shared Feature configuration *
317 ****************************************************************************/
318struct shared_feat_cfg { /* NVRAM Offset */
Eliezer Tamirf1410642008-02-28 11:51:50 -0800319
320 u32 config; /* 0x450 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200321#define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700322#define SHARED_FEATURE_MF_MODE_DISABLED 0x00000100
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200323
324};
325
326
327/****************************************************************************
328 * Port Feature configuration *
329 ****************************************************************************/
Eliezer Tamirf1410642008-02-28 11:51:50 -0800330struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */
331
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200332 u32 config;
333#define PORT_FEATURE_BAR1_SIZE_MASK 0x0000000f
334#define PORT_FEATURE_BAR1_SIZE_SHIFT 0
335#define PORT_FEATURE_BAR1_SIZE_DISABLED 0x00000000
336#define PORT_FEATURE_BAR1_SIZE_64K 0x00000001
337#define PORT_FEATURE_BAR1_SIZE_128K 0x00000002
338#define PORT_FEATURE_BAR1_SIZE_256K 0x00000003
339#define PORT_FEATURE_BAR1_SIZE_512K 0x00000004
340#define PORT_FEATURE_BAR1_SIZE_1M 0x00000005
341#define PORT_FEATURE_BAR1_SIZE_2M 0x00000006
342#define PORT_FEATURE_BAR1_SIZE_4M 0x00000007
343#define PORT_FEATURE_BAR1_SIZE_8M 0x00000008
344#define PORT_FEATURE_BAR1_SIZE_16M 0x00000009
345#define PORT_FEATURE_BAR1_SIZE_32M 0x0000000a
346#define PORT_FEATURE_BAR1_SIZE_64M 0x0000000b
347#define PORT_FEATURE_BAR1_SIZE_128M 0x0000000c
348#define PORT_FEATURE_BAR1_SIZE_256M 0x0000000d
349#define PORT_FEATURE_BAR1_SIZE_512M 0x0000000e
350#define PORT_FEATURE_BAR1_SIZE_1G 0x0000000f
351#define PORT_FEATURE_BAR2_SIZE_MASK 0x000000f0
352#define PORT_FEATURE_BAR2_SIZE_SHIFT 4
353#define PORT_FEATURE_BAR2_SIZE_DISABLED 0x00000000
354#define PORT_FEATURE_BAR2_SIZE_64K 0x00000010
355#define PORT_FEATURE_BAR2_SIZE_128K 0x00000020
356#define PORT_FEATURE_BAR2_SIZE_256K 0x00000030
357#define PORT_FEATURE_BAR2_SIZE_512K 0x00000040
358#define PORT_FEATURE_BAR2_SIZE_1M 0x00000050
359#define PORT_FEATURE_BAR2_SIZE_2M 0x00000060
360#define PORT_FEATURE_BAR2_SIZE_4M 0x00000070
361#define PORT_FEATURE_BAR2_SIZE_8M 0x00000080
362#define PORT_FEATURE_BAR2_SIZE_16M 0x00000090
363#define PORT_FEATURE_BAR2_SIZE_32M 0x000000a0
364#define PORT_FEATURE_BAR2_SIZE_64M 0x000000b0
365#define PORT_FEATURE_BAR2_SIZE_128M 0x000000c0
366#define PORT_FEATURE_BAR2_SIZE_256M 0x000000d0
367#define PORT_FEATURE_BAR2_SIZE_512M 0x000000e0
368#define PORT_FEATURE_BAR2_SIZE_1G 0x000000f0
369#define PORT_FEATURE_EN_SIZE_MASK 0x07000000
370#define PORT_FEATURE_EN_SIZE_SHIFT 24
371#define PORT_FEATURE_WOL_ENABLED 0x01000000
372#define PORT_FEATURE_MBA_ENABLED 0x02000000
373#define PORT_FEATURE_MFW_ENABLED 0x04000000
374
375 u32 wol_config;
376 /* Default is used when driver sets to "auto" mode */
377#define PORT_FEATURE_WOL_DEFAULT_MASK 0x00000003
378#define PORT_FEATURE_WOL_DEFAULT_SHIFT 0
379#define PORT_FEATURE_WOL_DEFAULT_DISABLE 0x00000000
380#define PORT_FEATURE_WOL_DEFAULT_MAGIC 0x00000001
381#define PORT_FEATURE_WOL_DEFAULT_ACPI 0x00000002
382#define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x00000003
383#define PORT_FEATURE_WOL_RES_PAUSE_CAP 0x00000004
384#define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP 0x00000008
385#define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010
386
387 u32 mba_config;
388#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000003
389#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0
390#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000
391#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001
392#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002
393#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003
394#define PORT_FEATURE_MBA_RES_PAUSE_CAP 0x00000100
395#define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP 0x00000200
396#define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400
397#define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000
398#define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800
399#define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000ff000
400#define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12
401#define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000
402#define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000
403#define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000
404#define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000
405#define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000
406#define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000
407#define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000
408#define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000
409#define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000
410#define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000
411#define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000
412#define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000
413#define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000
414#define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000
415#define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000
416#define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000
417#define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00f00000
418#define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20
419#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000
420#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24
421#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000
422#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000
423#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000
424#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000
425#define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c000000
426#define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26
427#define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000
428#define PORT_FEATURE_MBA_LINK_SPEED_10HD 0x04000000
429#define PORT_FEATURE_MBA_LINK_SPEED_10FD 0x08000000
430#define PORT_FEATURE_MBA_LINK_SPEED_100HD 0x0c000000
431#define PORT_FEATURE_MBA_LINK_SPEED_100FD 0x10000000
432#define PORT_FEATURE_MBA_LINK_SPEED_1GBPS 0x14000000
433#define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS 0x18000000
434#define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4 0x1c000000
435#define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KX4 0x20000000
436#define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KR 0x24000000
437#define PORT_FEATURE_MBA_LINK_SPEED_12GBPS 0x28000000
438#define PORT_FEATURE_MBA_LINK_SPEED_12_5GBPS 0x2c000000
439#define PORT_FEATURE_MBA_LINK_SPEED_13GBPS 0x30000000
440#define PORT_FEATURE_MBA_LINK_SPEED_15GBPS 0x34000000
441#define PORT_FEATURE_MBA_LINK_SPEED_16GBPS 0x38000000
442
443 u32 bmc_config;
444#define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT 0x00000000
445#define PORT_FEATURE_BMC_LINK_OVERRIDE_EN 0x00000001
446
447 u32 mba_vlan_cfg;
448#define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000ffff
449#define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0
450#define PORT_FEATURE_MBA_VLAN_EN 0x00010000
451
452 u32 resource_cfg;
453#define PORT_FEATURE_RESOURCE_CFG_VALID 0x00000001
454#define PORT_FEATURE_RESOURCE_CFG_DIAG 0x00000002
455#define PORT_FEATURE_RESOURCE_CFG_L2 0x00000004
456#define PORT_FEATURE_RESOURCE_CFG_ISCSI 0x00000008
457#define PORT_FEATURE_RESOURCE_CFG_RDMA 0x00000010
458
459 u32 smbus_config;
460 /* Obsolete */
461#define PORT_FEATURE_SMBUS_EN 0x00000001
462#define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe
463#define PORT_FEATURE_SMBUS_ADDR_SHIFT 1
464
Eliezer Tamirf1410642008-02-28 11:51:50 -0800465 u32 reserved1;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200466
467 u32 link_config; /* Used as HW defaults for the driver */
468#define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000
469#define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24
470 /* (forced) low speed switch (< 10G) */
471#define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000
472 /* (forced) high speed switch (>= 10G) */
473#define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000
474#define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000
475#define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000
476
477#define PORT_FEATURE_LINK_SPEED_MASK 0x000f0000
478#define PORT_FEATURE_LINK_SPEED_SHIFT 16
479#define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000
480#define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00010000
481#define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00020000
482#define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000
483#define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000
484#define PORT_FEATURE_LINK_SPEED_1G 0x00050000
485#define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000
486#define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000
487#define PORT_FEATURE_LINK_SPEED_10G_KX4 0x00080000
488#define PORT_FEATURE_LINK_SPEED_10G_KR 0x00090000
489#define PORT_FEATURE_LINK_SPEED_12G 0x000a0000
490#define PORT_FEATURE_LINK_SPEED_12_5G 0x000b0000
491#define PORT_FEATURE_LINK_SPEED_13G 0x000c0000
492#define PORT_FEATURE_LINK_SPEED_15G 0x000d0000
493#define PORT_FEATURE_LINK_SPEED_16G 0x000e0000
494
495#define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700
496#define PORT_FEATURE_FLOW_CONTROL_SHIFT 8
497#define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000
498#define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100
499#define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200
500#define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300
501#define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400
502
503 /* The default for MCP link configuration,
504 uses the same defines as link_config */
505 u32 mfw_wol_link_cfg;
506
507 u32 reserved[19];
508
509};
510
511
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700512/****************************************************************************
513 * Device Information *
514 ****************************************************************************/
515struct dev_info { /* size */
Eliezer Tamirf1410642008-02-28 11:51:50 -0800516
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700517 u32 bc_rev; /* 8 bits each: major, minor, build */ /* 4 */
Eliezer Tamirf1410642008-02-28 11:51:50 -0800518
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700519 struct shared_hw_cfg shared_hw_config; /* 40 */
Eliezer Tamirf1410642008-02-28 11:51:50 -0800520
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700521 struct port_hw_cfg port_hw_config[PORT_MAX]; /* 400*2=800 */
Eliezer Tamirf1410642008-02-28 11:51:50 -0800522
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700523 struct shared_feat_cfg shared_feature_config; /* 4 */
Eliezer Tamirf1410642008-02-28 11:51:50 -0800524
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700525 struct port_feat_cfg port_feature_config[PORT_MAX];/* 116*2=232 */
Eliezer Tamirf1410642008-02-28 11:51:50 -0800526
527};
528
529
530#define FUNC_0 0
531#define FUNC_1 1
Eilon Greensteinad8d3942008-06-23 20:29:02 -0700532#define FUNC_2 2
533#define FUNC_3 3
534#define FUNC_4 4
535#define FUNC_5 5
536#define FUNC_6 6
537#define FUNC_7 7
Eliezer Tamirf1410642008-02-28 11:51:50 -0800538#define E1_FUNC_MAX 2
Eilon Greensteinad8d3942008-06-23 20:29:02 -0700539#define E1H_FUNC_MAX 8
540
541#define VN_0 0
542#define VN_1 1
543#define VN_2 2
544#define VN_3 3
545#define E1VN_MAX 1
546#define E1HVN_MAX 4
Eliezer Tamirf1410642008-02-28 11:51:50 -0800547
548
549/* This value (in milliseconds) determines the frequency of the driver
550 * issuing the PULSE message code. The firmware monitors this periodic
551 * pulse to determine when to switch to an OS-absent mode. */
552#define DRV_PULSE_PERIOD_MS 250
553
554/* This value (in milliseconds) determines how long the driver should
555 * wait for an acknowledgement from the firmware before timing out. Once
556 * the firmware has timed out, the driver will assume there is no firmware
557 * running and there won't be any firmware-driver synchronization during a
558 * driver reset. */
559#define FW_ACK_TIME_OUT_MS 5000
560
561#define FW_ACK_POLL_TIME_MS 1
562
563#define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)
564
565/* LED Blink rate that will achieve ~15.9Hz */
566#define LED_BLINK_RATE_VAL 480
567
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200568/****************************************************************************
Eliezer Tamirf1410642008-02-28 11:51:50 -0800569 * Driver <-> FW Mailbox *
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200570 ****************************************************************************/
Eliezer Tamirf1410642008-02-28 11:51:50 -0800571struct drv_port_mb {
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200572
Eliezer Tamirf1410642008-02-28 11:51:50 -0800573 u32 link_status;
574 /* Driver should update this field on any link change event */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200575
Eliezer Tamirf1410642008-02-28 11:51:50 -0800576#define LINK_STATUS_LINK_FLAG_MASK 0x00000001
577#define LINK_STATUS_LINK_UP 0x00000001
578#define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E
579#define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1)
580#define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1)
581#define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1)
582#define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1)
583#define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1)
584#define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1)
585#define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1)
586#define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1)
587#define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1)
588#define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1)
589#define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1)
590#define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1)
591#define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1)
592#define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1)
593#define LINK_STATUS_SPEED_AND_DUPLEX_12GTFD (11<<1)
594#define LINK_STATUS_SPEED_AND_DUPLEX_12GXFD (11<<1)
595#define LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD (12<<1)
596#define LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD (12<<1)
597#define LINK_STATUS_SPEED_AND_DUPLEX_13GTFD (13<<1)
598#define LINK_STATUS_SPEED_AND_DUPLEX_13GXFD (13<<1)
599#define LINK_STATUS_SPEED_AND_DUPLEX_15GTFD (14<<1)
600#define LINK_STATUS_SPEED_AND_DUPLEX_15GXFD (14<<1)
601#define LINK_STATUS_SPEED_AND_DUPLEX_16GTFD (15<<1)
602#define LINK_STATUS_SPEED_AND_DUPLEX_16GXFD (15<<1)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200603
Eliezer Tamirf1410642008-02-28 11:51:50 -0800604#define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020
605#define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200606
Eliezer Tamirf1410642008-02-28 11:51:50 -0800607#define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
608#define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080
609#define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200610
Eliezer Tamirf1410642008-02-28 11:51:50 -0800611#define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
612#define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
613#define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800
614#define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000
615#define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000
616#define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000
617#define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000
618
619#define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000
620#define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000
621
622#define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000
623#define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000
624
625#define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000
626#define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18)
627#define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18)
628#define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18)
629#define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18)
630
631#define LINK_STATUS_SERDES_LINK 0x00100000
632
633#define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000
634#define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000
635#define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000
636#define LINK_STATUS_LINK_PARTNER_12GXFD_CAPABLE 0x01000000
637#define LINK_STATUS_LINK_PARTNER_12_5GXFD_CAPABLE 0x02000000
638#define LINK_STATUS_LINK_PARTNER_13GXFD_CAPABLE 0x04000000
639#define LINK_STATUS_LINK_PARTNER_15GXFD_CAPABLE 0x08000000
640#define LINK_STATUS_LINK_PARTNER_16GXFD_CAPABLE 0x10000000
641
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700642 u32 port_stx;
643
644 u32 reserved[2];
Eliezer Tamirf1410642008-02-28 11:51:50 -0800645
646};
647
648
649struct drv_func_mb {
650
651 u32 drv_mb_header;
652#define DRV_MSG_CODE_MASK 0xffff0000
653#define DRV_MSG_CODE_LOAD_REQ 0x10000000
654#define DRV_MSG_CODE_LOAD_DONE 0x11000000
655#define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000
656#define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000
657#define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000
658#define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
659#define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000
660#define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000
661#define DRV_MSG_CODE_VALIDATE_KEY 0x70000000
662#define DRV_MSG_CODE_GET_CURR_KEY 0x80000000
663#define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000
664#define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000
665#define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000
666
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700667#define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000
668#define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000
669#define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000
670#define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
671
Eliezer Tamirf1410642008-02-28 11:51:50 -0800672#define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
673
674 u32 drv_mb_param;
675
676 u32 fw_mb_header;
677#define FW_MSG_CODE_MASK 0xffff0000
678#define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000
679#define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000
680#define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000
681#define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000
682#define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000
683#define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000
684#define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000
685#define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000
686#define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000
687#define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000
688#define FW_MSG_CODE_DIAG_REFUSE 0x50200000
689#define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000
690#define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000
691#define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000
692#define FW_MSG_CODE_GET_KEY_DONE 0x80100000
693#define FW_MSG_CODE_NO_KEY 0x80f00000
694#define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000
695#define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000
696#define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000
697#define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000
698#define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000
699#define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000
700
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700701#define FW_MSG_CODE_LIC_CHALLENGE 0xff010000
702#define FW_MSG_CODE_LIC_RESPONSE 0xff020000
703#define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000
704#define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
705
Eliezer Tamirf1410642008-02-28 11:51:50 -0800706#define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
707
708 u32 fw_mb_param;
709
710 u32 drv_pulse_mb;
711#define DRV_PULSE_SEQ_MASK 0x00007fff
712#define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
713 /* The system time is in the format of
714 * (year-2001)*12*32 + month*32 + day. */
715#define DRV_PULSE_ALWAYS_ALIVE 0x00008000
716 /* Indicate to the firmware not to go into the
717 * OS-absent when it is not getting driver pulse.
718 * This is used for debugging as well for PXE(MBA). */
719
720 u32 mcp_pulse_mb;
721#define MCP_PULSE_SEQ_MASK 0x00007fff
722#define MCP_PULSE_ALWAYS_ALIVE 0x00008000
723 /* Indicates to the driver not to assert due to lack
724 * of MCP response */
725#define MCP_EVENT_MASK 0xffff0000
726#define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
727
728 u32 iscsi_boot_signature;
729 u32 iscsi_boot_block_offset;
730
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700731 u32 drv_status;
732#define DRV_STATUS_PMF 0x00000001
733
734 u32 virt_mac_upper;
735#define VIRT_MAC_SIGN_MASK 0xffff0000
736#define VIRT_MAC_SIGNATURE 0x564d0000
737 u32 virt_mac_lower;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200738
739};
740
741
742/****************************************************************************
743 * Management firmware state *
744 ****************************************************************************/
Eliezer Tamirf1410642008-02-28 11:51:50 -0800745/* Allocate 440 bytes for management firmware */
746#define MGMTFW_STATE_WORD_SIZE 110
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200747
748struct mgmtfw_state {
749 u32 opaque[MGMTFW_STATE_WORD_SIZE];
750};
751
752
753/****************************************************************************
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700754 * Multi-Function configuration *
755 ****************************************************************************/
756struct shared_mf_cfg {
757
758 u32 clp_mb;
759#define SHARED_MF_CLP_SET_DEFAULT 0x00000000
760 /* set by CLP */
761#define SHARED_MF_CLP_EXIT 0x00000001
762 /* set by MCP */
763#define SHARED_MF_CLP_EXIT_DONE 0x00010000
764
765};
766
767struct port_mf_cfg {
768
769 u32 dynamic_cfg; /* device control channel */
770#define PORT_MF_CFG_OUTER_VLAN_TAG_MASK 0x0000ffff
771#define PORT_MF_CFG_OUTER_VLAN_TAG_SHIFT 0
772#define PORT_MF_CFG_DYNAMIC_CFG_ENABLED 0x00010000
773#define PORT_MF_CFG_DYNAMIC_CFG_DEFAULT 0x00000000
774
775 u32 reserved[3];
776
777};
778
779struct func_mf_cfg {
780
781 u32 config;
782 /* E/R/I/D */
783 /* function 0 of each port cannot be hidden */
784#define FUNC_MF_CFG_FUNC_HIDE 0x00000001
785
786#define FUNC_MF_CFG_PROTOCOL_MASK 0x00000007
787#define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002
788#define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004
789#define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006
790#define FUNC_MF_CFG_PROTOCOL_DEFAULT\
791 FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA
792
793#define FUNC_MF_CFG_FUNC_DISABLED 0x00000008
794
795 /* PRI */
796 /* 0 - low priority, 3 - high priority */
797#define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300
798#define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8
799#define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000
800
801 /* MINBW, MAXBW */
802 /* value range - 0..100, increments in 100Mbps */
803#define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000
804#define FUNC_MF_CFG_MIN_BW_SHIFT 16
805#define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000
806#define FUNC_MF_CFG_MAX_BW_MASK 0xff000000
807#define FUNC_MF_CFG_MAX_BW_SHIFT 24
808#define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000
809
810 u32 mac_upper; /* MAC */
811#define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff
812#define FUNC_MF_CFG_UPPERMAC_SHIFT 0
813#define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK
814 u32 mac_lower;
815#define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff
816
817 u32 e1hov_tag; /* VNI */
818#define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
819#define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0
820#define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK
821
822 u32 reserved[2];
823
824};
825
826struct mf_cfg {
827
828 struct shared_mf_cfg shared_mf_config;
829 struct port_mf_cfg port_mf_config[PORT_MAX];
830#if defined(b710)
831 struct func_mf_cfg func_mf_config[E1_FUNC_MAX];
832#else
833 struct func_mf_cfg func_mf_config[E1H_FUNC_MAX];
834#endif
835
836};
837
838
839/****************************************************************************
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200840 * Shared Memory Region *
841 ****************************************************************************/
842struct shmem_region { /* SharedMem Offset (size) */
Eliezer Tamirf1410642008-02-28 11:51:50 -0800843
844 u32 validity_map[PORT_MAX]; /* 0x0 (4*2 = 0x8) */
845#define SHR_MEM_FORMAT_REV_ID ('A'<<24)
846#define SHR_MEM_FORMAT_REV_MASK 0xff000000
847 /* validity bits */
848#define SHR_MEM_VALIDITY_PCI_CFG 0x00100000
849#define SHR_MEM_VALIDITY_MB 0x00200000
850#define SHR_MEM_VALIDITY_DEV_INFO 0x00400000
851#define SHR_MEM_VALIDITY_RESERVED 0x00000007
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200852 /* One licensing bit should be set */
853#define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038
854#define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008
855#define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010
856#define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020
Eliezer Tamirf1410642008-02-28 11:51:50 -0800857 /* Active MFW */
858#define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000
859#define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040
860#define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080
861#define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0
862#define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0
863#define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200864
Eliezer Tamirf1410642008-02-28 11:51:50 -0800865 struct dev_info dev_info; /* 0x8 (0x438) */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200866
Eliezer Tamirf1410642008-02-28 11:51:50 -0800867 u8 reserved[52*PORT_MAX];
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200868
869 /* FW information (for internal FW use) */
Eliezer Tamirf1410642008-02-28 11:51:50 -0800870 u32 fw_info_fio_offset; /* 0x4a8 (0x4) */
871 struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200872
Eliezer Tamirf1410642008-02-28 11:51:50 -0800873 struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */
Eilon Greensteinad8d3942008-06-23 20:29:02 -0700874 struct drv_func_mb func_mb[E1H_FUNC_MAX];
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700875
876 struct mf_cfg mf_cfg;
Eliezer Tamirf1410642008-02-28 11:51:50 -0800877
878}; /* 0x6dc */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200879
880
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -0700881struct emac_stats {
882 u32 rx_stat_ifhcinoctets;
883 u32 rx_stat_ifhcinbadoctets;
884 u32 rx_stat_etherstatsfragments;
885 u32 rx_stat_ifhcinucastpkts;
886 u32 rx_stat_ifhcinmulticastpkts;
887 u32 rx_stat_ifhcinbroadcastpkts;
888 u32 rx_stat_dot3statsfcserrors;
889 u32 rx_stat_dot3statsalignmenterrors;
890 u32 rx_stat_dot3statscarriersenseerrors;
891 u32 rx_stat_xonpauseframesreceived;
892 u32 rx_stat_xoffpauseframesreceived;
893 u32 rx_stat_maccontrolframesreceived;
894 u32 rx_stat_xoffstateentered;
895 u32 rx_stat_dot3statsframestoolong;
896 u32 rx_stat_etherstatsjabbers;
897 u32 rx_stat_etherstatsundersizepkts;
898 u32 rx_stat_etherstatspkts64octets;
899 u32 rx_stat_etherstatspkts65octetsto127octets;
900 u32 rx_stat_etherstatspkts128octetsto255octets;
901 u32 rx_stat_etherstatspkts256octetsto511octets;
902 u32 rx_stat_etherstatspkts512octetsto1023octets;
903 u32 rx_stat_etherstatspkts1024octetsto1522octets;
904 u32 rx_stat_etherstatspktsover1522octets;
905
906 u32 rx_stat_falsecarriererrors;
907
908 u32 tx_stat_ifhcoutoctets;
909 u32 tx_stat_ifhcoutbadoctets;
910 u32 tx_stat_etherstatscollisions;
911 u32 tx_stat_outxonsent;
912 u32 tx_stat_outxoffsent;
913 u32 tx_stat_flowcontroldone;
914 u32 tx_stat_dot3statssinglecollisionframes;
915 u32 tx_stat_dot3statsmultiplecollisionframes;
916 u32 tx_stat_dot3statsdeferredtransmissions;
917 u32 tx_stat_dot3statsexcessivecollisions;
918 u32 tx_stat_dot3statslatecollisions;
919 u32 tx_stat_ifhcoutucastpkts;
920 u32 tx_stat_ifhcoutmulticastpkts;
921 u32 tx_stat_ifhcoutbroadcastpkts;
922 u32 tx_stat_etherstatspkts64octets;
923 u32 tx_stat_etherstatspkts65octetsto127octets;
924 u32 tx_stat_etherstatspkts128octetsto255octets;
925 u32 tx_stat_etherstatspkts256octetsto511octets;
926 u32 tx_stat_etherstatspkts512octetsto1023octets;
927 u32 tx_stat_etherstatspkts1024octetsto1522octets;
928 u32 tx_stat_etherstatspktsover1522octets;
929 u32 tx_stat_dot3statsinternalmactransmiterrors;
930};
931
932
933struct bmac_stats {
934 u32 tx_stat_gtpkt_lo;
935 u32 tx_stat_gtpkt_hi;
936 u32 tx_stat_gtxpf_lo;
937 u32 tx_stat_gtxpf_hi;
938 u32 tx_stat_gtfcs_lo;
939 u32 tx_stat_gtfcs_hi;
940 u32 tx_stat_gtmca_lo;
941 u32 tx_stat_gtmca_hi;
942 u32 tx_stat_gtbca_lo;
943 u32 tx_stat_gtbca_hi;
944 u32 tx_stat_gtfrg_lo;
945 u32 tx_stat_gtfrg_hi;
946 u32 tx_stat_gtovr_lo;
947 u32 tx_stat_gtovr_hi;
948 u32 tx_stat_gt64_lo;
949 u32 tx_stat_gt64_hi;
950 u32 tx_stat_gt127_lo;
951 u32 tx_stat_gt127_hi;
952 u32 tx_stat_gt255_lo;
953 u32 tx_stat_gt255_hi;
954 u32 tx_stat_gt511_lo;
955 u32 tx_stat_gt511_hi;
956 u32 tx_stat_gt1023_lo;
957 u32 tx_stat_gt1023_hi;
958 u32 tx_stat_gt1518_lo;
959 u32 tx_stat_gt1518_hi;
960 u32 tx_stat_gt2047_lo;
961 u32 tx_stat_gt2047_hi;
962 u32 tx_stat_gt4095_lo;
963 u32 tx_stat_gt4095_hi;
964 u32 tx_stat_gt9216_lo;
965 u32 tx_stat_gt9216_hi;
966 u32 tx_stat_gt16383_lo;
967 u32 tx_stat_gt16383_hi;
968 u32 tx_stat_gtmax_lo;
969 u32 tx_stat_gtmax_hi;
970 u32 tx_stat_gtufl_lo;
971 u32 tx_stat_gtufl_hi;
972 u32 tx_stat_gterr_lo;
973 u32 tx_stat_gterr_hi;
974 u32 tx_stat_gtbyt_lo;
975 u32 tx_stat_gtbyt_hi;
976
977 u32 rx_stat_gr64_lo;
978 u32 rx_stat_gr64_hi;
979 u32 rx_stat_gr127_lo;
980 u32 rx_stat_gr127_hi;
981 u32 rx_stat_gr255_lo;
982 u32 rx_stat_gr255_hi;
983 u32 rx_stat_gr511_lo;
984 u32 rx_stat_gr511_hi;
985 u32 rx_stat_gr1023_lo;
986 u32 rx_stat_gr1023_hi;
987 u32 rx_stat_gr1518_lo;
988 u32 rx_stat_gr1518_hi;
989 u32 rx_stat_gr2047_lo;
990 u32 rx_stat_gr2047_hi;
991 u32 rx_stat_gr4095_lo;
992 u32 rx_stat_gr4095_hi;
993 u32 rx_stat_gr9216_lo;
994 u32 rx_stat_gr9216_hi;
995 u32 rx_stat_gr16383_lo;
996 u32 rx_stat_gr16383_hi;
997 u32 rx_stat_grmax_lo;
998 u32 rx_stat_grmax_hi;
999 u32 rx_stat_grpkt_lo;
1000 u32 rx_stat_grpkt_hi;
1001 u32 rx_stat_grfcs_lo;
1002 u32 rx_stat_grfcs_hi;
1003 u32 rx_stat_grmca_lo;
1004 u32 rx_stat_grmca_hi;
1005 u32 rx_stat_grbca_lo;
1006 u32 rx_stat_grbca_hi;
1007 u32 rx_stat_grxcf_lo;
1008 u32 rx_stat_grxcf_hi;
1009 u32 rx_stat_grxpf_lo;
1010 u32 rx_stat_grxpf_hi;
1011 u32 rx_stat_grxuo_lo;
1012 u32 rx_stat_grxuo_hi;
1013 u32 rx_stat_grjbr_lo;
1014 u32 rx_stat_grjbr_hi;
1015 u32 rx_stat_grovr_lo;
1016 u32 rx_stat_grovr_hi;
1017 u32 rx_stat_grflr_lo;
1018 u32 rx_stat_grflr_hi;
1019 u32 rx_stat_grmeg_lo;
1020 u32 rx_stat_grmeg_hi;
1021 u32 rx_stat_grmeb_lo;
1022 u32 rx_stat_grmeb_hi;
1023 u32 rx_stat_grbyt_lo;
1024 u32 rx_stat_grbyt_hi;
1025 u32 rx_stat_grund_lo;
1026 u32 rx_stat_grund_hi;
1027 u32 rx_stat_grfrg_lo;
1028 u32 rx_stat_grfrg_hi;
1029 u32 rx_stat_grerb_lo;
1030 u32 rx_stat_grerb_hi;
1031 u32 rx_stat_grfre_lo;
1032 u32 rx_stat_grfre_hi;
1033 u32 rx_stat_gripj_lo;
1034 u32 rx_stat_gripj_hi;
1035};
1036
1037
1038union mac_stats {
1039 struct emac_stats emac_stats;
1040 struct bmac_stats bmac_stats;
1041};
1042
1043
1044struct mac_stx {
1045 /* in_bad_octets */
1046 u32 rx_stat_ifhcinbadoctets_hi;
1047 u32 rx_stat_ifhcinbadoctets_lo;
1048
1049 /* out_bad_octets */
1050 u32 tx_stat_ifhcoutbadoctets_hi;
1051 u32 tx_stat_ifhcoutbadoctets_lo;
1052
1053 /* crc_receive_errors */
1054 u32 rx_stat_dot3statsfcserrors_hi;
1055 u32 rx_stat_dot3statsfcserrors_lo;
1056 /* alignment_errors */
1057 u32 rx_stat_dot3statsalignmenterrors_hi;
1058 u32 rx_stat_dot3statsalignmenterrors_lo;
1059 /* carrier_sense_errors */
1060 u32 rx_stat_dot3statscarriersenseerrors_hi;
1061 u32 rx_stat_dot3statscarriersenseerrors_lo;
1062 /* false_carrier_detections */
1063 u32 rx_stat_falsecarriererrors_hi;
1064 u32 rx_stat_falsecarriererrors_lo;
1065
1066 /* runt_packets_received */
1067 u32 rx_stat_etherstatsundersizepkts_hi;
1068 u32 rx_stat_etherstatsundersizepkts_lo;
1069 /* jabber_packets_received */
1070 u32 rx_stat_dot3statsframestoolong_hi;
1071 u32 rx_stat_dot3statsframestoolong_lo;
1072
1073 /* error_runt_packets_received */
1074 u32 rx_stat_etherstatsfragments_hi;
1075 u32 rx_stat_etherstatsfragments_lo;
1076 /* error_jabber_packets_received */
1077 u32 rx_stat_etherstatsjabbers_hi;
1078 u32 rx_stat_etherstatsjabbers_lo;
1079
1080 /* control_frames_received */
1081 u32 rx_stat_maccontrolframesreceived_hi;
1082 u32 rx_stat_maccontrolframesreceived_lo;
1083 u32 rx_stat_bmac_xpf_hi;
1084 u32 rx_stat_bmac_xpf_lo;
1085 u32 rx_stat_bmac_xcf_hi;
1086 u32 rx_stat_bmac_xcf_lo;
1087
1088 /* xoff_state_entered */
1089 u32 rx_stat_xoffstateentered_hi;
1090 u32 rx_stat_xoffstateentered_lo;
1091 /* pause_xon_frames_received */
1092 u32 rx_stat_xonpauseframesreceived_hi;
1093 u32 rx_stat_xonpauseframesreceived_lo;
1094 /* pause_xoff_frames_received */
1095 u32 rx_stat_xoffpauseframesreceived_hi;
1096 u32 rx_stat_xoffpauseframesreceived_lo;
1097 /* pause_xon_frames_transmitted */
1098 u32 tx_stat_outxonsent_hi;
1099 u32 tx_stat_outxonsent_lo;
1100 /* pause_xoff_frames_transmitted */
1101 u32 tx_stat_outxoffsent_hi;
1102 u32 tx_stat_outxoffsent_lo;
1103 /* flow_control_done */
1104 u32 tx_stat_flowcontroldone_hi;
1105 u32 tx_stat_flowcontroldone_lo;
1106
1107 /* ether_stats_collisions */
1108 u32 tx_stat_etherstatscollisions_hi;
1109 u32 tx_stat_etherstatscollisions_lo;
1110 /* single_collision_transmit_frames */
1111 u32 tx_stat_dot3statssinglecollisionframes_hi;
1112 u32 tx_stat_dot3statssinglecollisionframes_lo;
1113 /* multiple_collision_transmit_frames */
1114 u32 tx_stat_dot3statsmultiplecollisionframes_hi;
1115 u32 tx_stat_dot3statsmultiplecollisionframes_lo;
1116 /* deferred_transmissions */
1117 u32 tx_stat_dot3statsdeferredtransmissions_hi;
1118 u32 tx_stat_dot3statsdeferredtransmissions_lo;
1119 /* excessive_collision_frames */
1120 u32 tx_stat_dot3statsexcessivecollisions_hi;
1121 u32 tx_stat_dot3statsexcessivecollisions_lo;
1122 /* late_collision_frames */
1123 u32 tx_stat_dot3statslatecollisions_hi;
1124 u32 tx_stat_dot3statslatecollisions_lo;
1125
1126 /* frames_transmitted_64_bytes */
1127 u32 tx_stat_etherstatspkts64octets_hi;
1128 u32 tx_stat_etherstatspkts64octets_lo;
1129 /* frames_transmitted_65_127_bytes */
1130 u32 tx_stat_etherstatspkts65octetsto127octets_hi;
1131 u32 tx_stat_etherstatspkts65octetsto127octets_lo;
1132 /* frames_transmitted_128_255_bytes */
1133 u32 tx_stat_etherstatspkts128octetsto255octets_hi;
1134 u32 tx_stat_etherstatspkts128octetsto255octets_lo;
1135 /* frames_transmitted_256_511_bytes */
1136 u32 tx_stat_etherstatspkts256octetsto511octets_hi;
1137 u32 tx_stat_etherstatspkts256octetsto511octets_lo;
1138 /* frames_transmitted_512_1023_bytes */
1139 u32 tx_stat_etherstatspkts512octetsto1023octets_hi;
1140 u32 tx_stat_etherstatspkts512octetsto1023octets_lo;
1141 /* frames_transmitted_1024_1522_bytes */
1142 u32 tx_stat_etherstatspkts1024octetsto1522octets_hi;
1143 u32 tx_stat_etherstatspkts1024octetsto1522octets_lo;
1144 /* frames_transmitted_1523_9022_bytes */
1145 u32 tx_stat_etherstatspktsover1522octets_hi;
1146 u32 tx_stat_etherstatspktsover1522octets_lo;
1147 u32 tx_stat_bmac_2047_hi;
1148 u32 tx_stat_bmac_2047_lo;
1149 u32 tx_stat_bmac_4095_hi;
1150 u32 tx_stat_bmac_4095_lo;
1151 u32 tx_stat_bmac_9216_hi;
1152 u32 tx_stat_bmac_9216_lo;
1153 u32 tx_stat_bmac_16383_hi;
1154 u32 tx_stat_bmac_16383_lo;
1155
1156 /* internal_mac_transmit_errors */
1157 u32 tx_stat_dot3statsinternalmactransmiterrors_hi;
1158 u32 tx_stat_dot3statsinternalmactransmiterrors_lo;
1159
1160 /* if_out_discards */
1161 u32 tx_stat_bmac_ufl_hi;
1162 u32 tx_stat_bmac_ufl_lo;
1163};
1164
1165
1166#define MAC_STX_IDX_MAX 2
1167
1168struct host_port_stats {
1169 u32 host_port_stats_start;
1170
1171 struct mac_stx mac_stx[MAC_STX_IDX_MAX];
1172
1173 u32 brb_drop_hi;
1174 u32 brb_drop_lo;
1175
1176 u32 host_port_stats_end;
1177};
1178
1179
1180struct host_func_stats {
1181 u32 host_func_stats_start;
1182
1183 u32 total_bytes_received_hi;
1184 u32 total_bytes_received_lo;
1185
1186 u32 total_bytes_transmitted_hi;
1187 u32 total_bytes_transmitted_lo;
1188
1189 u32 total_unicast_packets_received_hi;
1190 u32 total_unicast_packets_received_lo;
1191
1192 u32 total_multicast_packets_received_hi;
1193 u32 total_multicast_packets_received_lo;
1194
1195 u32 total_broadcast_packets_received_hi;
1196 u32 total_broadcast_packets_received_lo;
1197
1198 u32 total_unicast_packets_transmitted_hi;
1199 u32 total_unicast_packets_transmitted_lo;
1200
1201 u32 total_multicast_packets_transmitted_hi;
1202 u32 total_multicast_packets_transmitted_lo;
1203
1204 u32 total_broadcast_packets_transmitted_hi;
1205 u32 total_broadcast_packets_transmitted_lo;
1206
1207 u32 valid_bytes_received_hi;
1208 u32 valid_bytes_received_lo;
1209
1210 u32 host_func_stats_end;
1211};
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001212
1213
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001214#define BCM_5710_FW_MAJOR_VERSION 4
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001215#define BCM_5710_FW_MINOR_VERSION 5
1216#define BCM_5710_FW_REVISION_VERSION 1
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001217#define BCM_5710_FW_COMPILE_FLAGS 1
1218
1219
1220/*
1221 * attention bits
1222 */
1223struct atten_def_status_block {
1224 u32 attn_bits;
1225 u32 attn_bits_ack;
1226#if defined(__BIG_ENDIAN)
1227 u16 attn_bits_index;
1228 u8 reserved0;
1229 u8 status_block_id;
1230#elif defined(__LITTLE_ENDIAN)
1231 u8 status_block_id;
1232 u8 reserved0;
1233 u16 attn_bits_index;
1234#endif
1235 u32 reserved1;
1236};
1237
1238
1239/*
1240 * common data for all protocols
1241 */
1242struct doorbell_hdr {
1243 u8 header;
1244#define DOORBELL_HDR_RX (0x1<<0)
1245#define DOORBELL_HDR_RX_SHIFT 0
1246#define DOORBELL_HDR_DB_TYPE (0x1<<1)
1247#define DOORBELL_HDR_DB_TYPE_SHIFT 1
1248#define DOORBELL_HDR_DPM_SIZE (0x3<<2)
1249#define DOORBELL_HDR_DPM_SIZE_SHIFT 2
1250#define DOORBELL_HDR_CONN_TYPE (0xF<<4)
1251#define DOORBELL_HDR_CONN_TYPE_SHIFT 4
1252};
1253
1254/*
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001255 * doorbell message sent to the chip
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001256 */
1257struct doorbell {
1258#if defined(__BIG_ENDIAN)
1259 u16 zero_fill2;
1260 u8 zero_fill1;
1261 struct doorbell_hdr header;
1262#elif defined(__LITTLE_ENDIAN)
1263 struct doorbell_hdr header;
1264 u8 zero_fill1;
1265 u16 zero_fill2;
1266#endif
1267};
1268
1269
1270/*
1271 * IGU driver acknowlegement register
1272 */
1273struct igu_ack_register {
1274#if defined(__BIG_ENDIAN)
1275 u16 sb_id_and_flags;
1276#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
1277#define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
1278#define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
1279#define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
1280#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
1281#define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
1282#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
1283#define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
1284#define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
1285#define IGU_ACK_REGISTER_RESERVED_SHIFT 11
1286 u16 status_block_index;
1287#elif defined(__LITTLE_ENDIAN)
1288 u16 status_block_index;
1289 u16 sb_id_and_flags;
1290#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
1291#define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
1292#define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
1293#define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
1294#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
1295#define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
1296#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
1297#define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
1298#define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
1299#define IGU_ACK_REGISTER_RESERVED_SHIFT 11
1300#endif
1301};
1302
1303
1304/*
1305 * Parser parsing flags field
1306 */
1307struct parsing_flags {
1308 u16 flags;
1309#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0)
1310#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001311#define PARSING_FLAGS_VLAN (0x1<<1)
1312#define PARSING_FLAGS_VLAN_SHIFT 1
1313#define PARSING_FLAGS_EXTRA_VLAN (0x1<<2)
1314#define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001315#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3)
1316#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3
1317#define PARSING_FLAGS_IP_OPTIONS (0x1<<5)
1318#define PARSING_FLAGS_IP_OPTIONS_SHIFT 5
1319#define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6)
1320#define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6
1321#define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7)
1322#define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7
1323#define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9)
1324#define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9
1325#define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10)
1326#define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10
1327#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11)
1328#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11
1329#define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12)
1330#define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12
1331#define PARSING_FLAGS_LLC_SNAP (0x1<<13)
1332#define PARSING_FLAGS_LLC_SNAP_SHIFT 13
1333#define PARSING_FLAGS_RESERVED0 (0x3<<14)
1334#define PARSING_FLAGS_RESERVED0_SHIFT 14
1335};
1336
1337
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001338struct regpair {
1339 u32 lo;
1340 u32 hi;
1341};
1342
1343
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001344/*
1345 * dmae command structure
1346 */
1347struct dmae_command {
1348 u32 opcode;
1349#define DMAE_COMMAND_SRC (0x1<<0)
1350#define DMAE_COMMAND_SRC_SHIFT 0
1351#define DMAE_COMMAND_DST (0x3<<1)
1352#define DMAE_COMMAND_DST_SHIFT 1
1353#define DMAE_COMMAND_C_DST (0x1<<3)
1354#define DMAE_COMMAND_C_DST_SHIFT 3
1355#define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4)
1356#define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4
1357#define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5)
1358#define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5
1359#define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6)
1360#define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6
1361#define DMAE_COMMAND_ENDIANITY (0x3<<9)
1362#define DMAE_COMMAND_ENDIANITY_SHIFT 9
1363#define DMAE_COMMAND_PORT (0x1<<11)
1364#define DMAE_COMMAND_PORT_SHIFT 11
1365#define DMAE_COMMAND_CRC_RESET (0x1<<12)
1366#define DMAE_COMMAND_CRC_RESET_SHIFT 12
1367#define DMAE_COMMAND_SRC_RESET (0x1<<13)
1368#define DMAE_COMMAND_SRC_RESET_SHIFT 13
1369#define DMAE_COMMAND_DST_RESET (0x1<<14)
1370#define DMAE_COMMAND_DST_RESET_SHIFT 14
Eilon Greensteinad8d3942008-06-23 20:29:02 -07001371#define DMAE_COMMAND_E1HVN (0x3<<15)
1372#define DMAE_COMMAND_E1HVN_SHIFT 15
1373#define DMAE_COMMAND_RESERVED0 (0x7FFF<<17)
1374#define DMAE_COMMAND_RESERVED0_SHIFT 17
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001375 u32 src_addr_lo;
1376 u32 src_addr_hi;
1377 u32 dst_addr_lo;
1378 u32 dst_addr_hi;
1379#if defined(__BIG_ENDIAN)
1380 u16 reserved1;
1381 u16 len;
1382#elif defined(__LITTLE_ENDIAN)
1383 u16 len;
1384 u16 reserved1;
1385#endif
1386 u32 comp_addr_lo;
1387 u32 comp_addr_hi;
1388 u32 comp_val;
1389 u32 crc32;
1390 u32 crc32_c;
1391#if defined(__BIG_ENDIAN)
1392 u16 crc16_c;
1393 u16 crc16;
1394#elif defined(__LITTLE_ENDIAN)
1395 u16 crc16;
1396 u16 crc16_c;
1397#endif
1398#if defined(__BIG_ENDIAN)
1399 u16 reserved2;
1400 u16 crc_t10;
1401#elif defined(__LITTLE_ENDIAN)
1402 u16 crc_t10;
1403 u16 reserved2;
1404#endif
1405#if defined(__BIG_ENDIAN)
1406 u16 xsum8;
1407 u16 xsum16;
1408#elif defined(__LITTLE_ENDIAN)
1409 u16 xsum16;
1410 u16 xsum8;
1411#endif
1412};
1413
1414
1415struct double_regpair {
1416 u32 regpair0_lo;
1417 u32 regpair0_hi;
1418 u32 regpair1_lo;
1419 u32 regpair1_hi;
1420};
1421
1422
1423/*
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001424 * The eth storm context of Ustorm (configuration part)
1425 */
1426struct ustorm_eth_st_context_config {
1427#if defined(__BIG_ENDIAN)
1428 u8 flags;
1429#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT (0x1<<0)
1430#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT_SHIFT 0
1431#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC (0x1<<1)
1432#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC_SHIFT 1
1433#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA (0x1<<2)
1434#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA_SHIFT 2
1435#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING (0x1<<3)
1436#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING_SHIFT 3
1437#define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0 (0xF<<4)
1438#define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0_SHIFT 4
1439 u8 status_block_id;
1440 u8 clientId;
1441 u8 sb_index_numbers;
1442#define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER (0xF<<0)
1443#define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT 0
1444#define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER (0xF<<4)
1445#define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT 4
1446#elif defined(__LITTLE_ENDIAN)
1447 u8 sb_index_numbers;
1448#define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER (0xF<<0)
1449#define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT 0
1450#define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER (0xF<<4)
1451#define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT 4
1452 u8 clientId;
1453 u8 status_block_id;
1454 u8 flags;
1455#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT (0x1<<0)
1456#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT_SHIFT 0
1457#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC (0x1<<1)
1458#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC_SHIFT 1
1459#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA (0x1<<2)
1460#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA_SHIFT 2
1461#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING (0x1<<3)
1462#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING_SHIFT 3
1463#define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0 (0xF<<4)
1464#define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0_SHIFT 4
1465#endif
1466#if defined(__BIG_ENDIAN)
1467 u16 bd_buff_size;
1468 u16 mc_alignment_size;
1469#elif defined(__LITTLE_ENDIAN)
1470 u16 mc_alignment_size;
1471 u16 bd_buff_size;
1472#endif
1473#if defined(__BIG_ENDIAN)
1474 u8 __local_sge_prod;
1475 u8 __local_bd_prod;
1476 u16 sge_buff_size;
1477#elif defined(__LITTLE_ENDIAN)
1478 u16 sge_buff_size;
1479 u8 __local_bd_prod;
1480 u8 __local_sge_prod;
1481#endif
1482#if defined(__BIG_ENDIAN)
1483 u16 __bd_cons;
1484 u16 __sge_cons;
1485#elif defined(__LITTLE_ENDIAN)
1486 u16 __sge_cons;
1487 u16 __bd_cons;
1488#endif
1489 u32 bd_page_base_lo;
1490 u32 bd_page_base_hi;
1491 u32 sge_page_base_lo;
1492 u32 sge_page_base_hi;
1493};
1494
1495/*
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001496 * The eth Rx Buffer Descriptor
1497 */
1498struct eth_rx_bd {
1499 u32 addr_lo;
1500 u32 addr_hi;
1501};
1502
1503/*
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001504 * The eth Rx SGE Descriptor
1505 */
1506struct eth_rx_sge {
1507 u32 addr_lo;
1508 u32 addr_hi;
1509};
1510
1511/*
1512 * Local BDs and SGEs rings (in ETH)
1513 */
1514struct eth_local_rx_rings {
1515 struct eth_rx_bd __local_bd_ring[16];
1516 struct eth_rx_sge __local_sge_ring[12];
1517};
1518
1519/*
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001520 * The eth storm context of Ustorm
1521 */
1522struct ustorm_eth_st_context {
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001523 struct ustorm_eth_st_context_config common;
1524 struct eth_local_rx_rings __rings;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001525};
1526
1527/*
1528 * The eth storm context of Tstorm
1529 */
1530struct tstorm_eth_st_context {
1531 u32 __reserved0[28];
1532};
1533
1534/*
1535 * The eth aggregative context section of Xstorm
1536 */
1537struct xstorm_eth_extra_ag_context_section {
1538#if defined(__BIG_ENDIAN)
1539 u8 __tcp_agg_vars1;
1540 u8 __reserved50;
1541 u16 __mss;
1542#elif defined(__LITTLE_ENDIAN)
1543 u16 __mss;
1544 u8 __reserved50;
1545 u8 __tcp_agg_vars1;
1546#endif
1547 u32 __snd_nxt;
1548 u32 __tx_wnd;
1549 u32 __snd_una;
1550 u32 __reserved53;
1551#if defined(__BIG_ENDIAN)
1552 u8 __agg_val8_th;
1553 u8 __agg_val8;
1554 u16 __tcp_agg_vars2;
1555#elif defined(__LITTLE_ENDIAN)
1556 u16 __tcp_agg_vars2;
1557 u8 __agg_val8;
1558 u8 __agg_val8_th;
1559#endif
1560 u32 __reserved58;
1561 u32 __reserved59;
1562 u32 __reserved60;
1563 u32 __reserved61;
1564#if defined(__BIG_ENDIAN)
1565 u16 __agg_val7_th;
1566 u16 __agg_val7;
1567#elif defined(__LITTLE_ENDIAN)
1568 u16 __agg_val7;
1569 u16 __agg_val7_th;
1570#endif
1571#if defined(__BIG_ENDIAN)
1572 u8 __tcp_agg_vars5;
1573 u8 __tcp_agg_vars4;
1574 u8 __tcp_agg_vars3;
1575 u8 __reserved62;
1576#elif defined(__LITTLE_ENDIAN)
1577 u8 __reserved62;
1578 u8 __tcp_agg_vars3;
1579 u8 __tcp_agg_vars4;
1580 u8 __tcp_agg_vars5;
1581#endif
1582 u32 __tcp_agg_vars6;
1583#if defined(__BIG_ENDIAN)
1584 u16 __agg_misc6;
1585 u16 __tcp_agg_vars7;
1586#elif defined(__LITTLE_ENDIAN)
1587 u16 __tcp_agg_vars7;
1588 u16 __agg_misc6;
1589#endif
1590 u32 __agg_val10;
1591 u32 __agg_val10_th;
1592#if defined(__BIG_ENDIAN)
1593 u16 __reserved3;
1594 u8 __reserved2;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001595 u8 __da_only_cnt;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001596#elif defined(__LITTLE_ENDIAN)
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001597 u8 __da_only_cnt;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001598 u8 __reserved2;
1599 u16 __reserved3;
1600#endif
1601};
1602
1603/*
1604 * The eth aggregative context of Xstorm
1605 */
1606struct xstorm_eth_ag_context {
1607#if defined(__BIG_ENDIAN)
1608 u16 __bd_prod;
1609 u8 __agg_vars1;
1610 u8 __state;
1611#elif defined(__LITTLE_ENDIAN)
1612 u8 __state;
1613 u8 __agg_vars1;
1614 u16 __bd_prod;
1615#endif
1616#if defined(__BIG_ENDIAN)
1617 u8 cdu_reserved;
1618 u8 __agg_vars4;
1619 u8 __agg_vars3;
1620 u8 __agg_vars2;
1621#elif defined(__LITTLE_ENDIAN)
1622 u8 __agg_vars2;
1623 u8 __agg_vars3;
1624 u8 __agg_vars4;
1625 u8 cdu_reserved;
1626#endif
1627 u32 __more_packets_to_send;
1628#if defined(__BIG_ENDIAN)
1629 u16 __agg_vars5;
1630 u16 __agg_val4_th;
1631#elif defined(__LITTLE_ENDIAN)
1632 u16 __agg_val4_th;
1633 u16 __agg_vars5;
1634#endif
1635 struct xstorm_eth_extra_ag_context_section __extra_section;
1636#if defined(__BIG_ENDIAN)
1637 u16 __agg_vars7;
1638 u8 __agg_val3_th;
1639 u8 __agg_vars6;
1640#elif defined(__LITTLE_ENDIAN)
1641 u8 __agg_vars6;
1642 u8 __agg_val3_th;
1643 u16 __agg_vars7;
1644#endif
1645#if defined(__BIG_ENDIAN)
1646 u16 __agg_val11_th;
1647 u16 __agg_val11;
1648#elif defined(__LITTLE_ENDIAN)
1649 u16 __agg_val11;
1650 u16 __agg_val11_th;
1651#endif
1652#if defined(__BIG_ENDIAN)
1653 u8 __reserved1;
1654 u8 __agg_val6_th;
1655 u16 __agg_val9;
1656#elif defined(__LITTLE_ENDIAN)
1657 u16 __agg_val9;
1658 u8 __agg_val6_th;
1659 u8 __reserved1;
1660#endif
1661#if defined(__BIG_ENDIAN)
1662 u16 __agg_val2_th;
1663 u16 __agg_val2;
1664#elif defined(__LITTLE_ENDIAN)
1665 u16 __agg_val2;
1666 u16 __agg_val2_th;
1667#endif
1668 u32 __agg_vars8;
1669#if defined(__BIG_ENDIAN)
1670 u16 __agg_misc0;
1671 u16 __agg_val4;
1672#elif defined(__LITTLE_ENDIAN)
1673 u16 __agg_val4;
1674 u16 __agg_misc0;
1675#endif
1676#if defined(__BIG_ENDIAN)
1677 u8 __agg_val3;
1678 u8 __agg_val6;
1679 u8 __agg_val5_th;
1680 u8 __agg_val5;
1681#elif defined(__LITTLE_ENDIAN)
1682 u8 __agg_val5;
1683 u8 __agg_val5_th;
1684 u8 __agg_val6;
1685 u8 __agg_val3;
1686#endif
1687#if defined(__BIG_ENDIAN)
1688 u16 __agg_misc1;
1689 u16 __bd_ind_max_val;
1690#elif defined(__LITTLE_ENDIAN)
1691 u16 __bd_ind_max_val;
1692 u16 __agg_misc1;
1693#endif
1694 u32 __reserved57;
1695 u32 __agg_misc4;
1696 u32 __agg_misc5;
1697};
1698
1699/*
1700 * The eth aggregative context section of Tstorm
1701 */
1702struct tstorm_eth_extra_ag_context_section {
1703 u32 __agg_val1;
1704#if defined(__BIG_ENDIAN)
1705 u8 __tcp_agg_vars2;
1706 u8 __agg_val3;
1707 u16 __agg_val2;
1708#elif defined(__LITTLE_ENDIAN)
1709 u16 __agg_val2;
1710 u8 __agg_val3;
1711 u8 __tcp_agg_vars2;
1712#endif
1713#if defined(__BIG_ENDIAN)
1714 u16 __agg_val5;
1715 u8 __agg_val6;
1716 u8 __tcp_agg_vars3;
1717#elif defined(__LITTLE_ENDIAN)
1718 u8 __tcp_agg_vars3;
1719 u8 __agg_val6;
1720 u16 __agg_val5;
1721#endif
1722 u32 __reserved63;
1723 u32 __reserved64;
1724 u32 __reserved65;
1725 u32 __reserved66;
1726 u32 __reserved67;
1727 u32 __tcp_agg_vars1;
1728 u32 __reserved61;
1729 u32 __reserved62;
1730 u32 __reserved2;
1731};
1732
1733/*
1734 * The eth aggregative context of Tstorm
1735 */
1736struct tstorm_eth_ag_context {
1737#if defined(__BIG_ENDIAN)
1738 u16 __reserved54;
1739 u8 __agg_vars1;
1740 u8 __state;
1741#elif defined(__LITTLE_ENDIAN)
1742 u8 __state;
1743 u8 __agg_vars1;
1744 u16 __reserved54;
1745#endif
1746#if defined(__BIG_ENDIAN)
1747 u16 __agg_val4;
1748 u16 __agg_vars2;
1749#elif defined(__LITTLE_ENDIAN)
1750 u16 __agg_vars2;
1751 u16 __agg_val4;
1752#endif
1753 struct tstorm_eth_extra_ag_context_section __extra_section;
1754};
1755
1756/*
1757 * The eth aggregative context of Cstorm
1758 */
1759struct cstorm_eth_ag_context {
1760 u32 __agg_vars1;
1761#if defined(__BIG_ENDIAN)
1762 u8 __aux1_th;
1763 u8 __aux1_val;
1764 u16 __agg_vars2;
1765#elif defined(__LITTLE_ENDIAN)
1766 u16 __agg_vars2;
1767 u8 __aux1_val;
1768 u8 __aux1_th;
1769#endif
1770 u32 __num_of_treated_packet;
1771 u32 __last_packet_treated;
1772#if defined(__BIG_ENDIAN)
1773 u16 __reserved58;
1774 u16 __reserved57;
1775#elif defined(__LITTLE_ENDIAN)
1776 u16 __reserved57;
1777 u16 __reserved58;
1778#endif
1779#if defined(__BIG_ENDIAN)
1780 u8 __reserved62;
1781 u8 __reserved61;
1782 u8 __reserved60;
1783 u8 __reserved59;
1784#elif defined(__LITTLE_ENDIAN)
1785 u8 __reserved59;
1786 u8 __reserved60;
1787 u8 __reserved61;
1788 u8 __reserved62;
1789#endif
1790#if defined(__BIG_ENDIAN)
1791 u16 __reserved64;
1792 u16 __reserved63;
1793#elif defined(__LITTLE_ENDIAN)
1794 u16 __reserved63;
1795 u16 __reserved64;
1796#endif
1797 u32 __reserved65;
1798#if defined(__BIG_ENDIAN)
1799 u16 __agg_vars3;
1800 u16 __rq_inv_cnt;
1801#elif defined(__LITTLE_ENDIAN)
1802 u16 __rq_inv_cnt;
1803 u16 __agg_vars3;
1804#endif
1805#if defined(__BIG_ENDIAN)
1806 u16 __packet_index_th;
1807 u16 __packet_index;
1808#elif defined(__LITTLE_ENDIAN)
1809 u16 __packet_index;
1810 u16 __packet_index_th;
1811#endif
1812};
1813
1814/*
1815 * The eth aggregative context of Ustorm
1816 */
1817struct ustorm_eth_ag_context {
1818#if defined(__BIG_ENDIAN)
1819 u8 __aux_counter_flags;
1820 u8 __agg_vars2;
1821 u8 __agg_vars1;
1822 u8 __state;
1823#elif defined(__LITTLE_ENDIAN)
1824 u8 __state;
1825 u8 __agg_vars1;
1826 u8 __agg_vars2;
1827 u8 __aux_counter_flags;
1828#endif
1829#if defined(__BIG_ENDIAN)
1830 u8 cdu_usage;
1831 u8 __agg_misc2;
1832 u16 __agg_misc1;
1833#elif defined(__LITTLE_ENDIAN)
1834 u16 __agg_misc1;
1835 u8 __agg_misc2;
1836 u8 cdu_usage;
1837#endif
1838 u32 __agg_misc4;
1839#if defined(__BIG_ENDIAN)
1840 u8 __agg_val3_th;
1841 u8 __agg_val3;
1842 u16 __agg_misc3;
1843#elif defined(__LITTLE_ENDIAN)
1844 u16 __agg_misc3;
1845 u8 __agg_val3;
1846 u8 __agg_val3_th;
1847#endif
1848 u32 __agg_val1;
1849 u32 __agg_misc4_th;
1850#if defined(__BIG_ENDIAN)
1851 u16 __agg_val2_th;
1852 u16 __agg_val2;
1853#elif defined(__LITTLE_ENDIAN)
1854 u16 __agg_val2;
1855 u16 __agg_val2_th;
1856#endif
1857#if defined(__BIG_ENDIAN)
1858 u16 __reserved2;
1859 u8 __decision_rules;
1860 u8 __decision_rule_enable_bits;
1861#elif defined(__LITTLE_ENDIAN)
1862 u8 __decision_rule_enable_bits;
1863 u8 __decision_rules;
1864 u16 __reserved2;
1865#endif
1866};
1867
1868/*
1869 * Timers connection context
1870 */
1871struct timers_block_context {
1872 u32 __reserved_0;
1873 u32 __reserved_1;
1874 u32 __reserved_2;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001875 u32 flags;
1876#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0)
1877#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0
1878#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2)
1879#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2
1880#define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3)
1881#define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001882};
1883
1884/*
1885 * structure for easy accessability to assembler
1886 */
1887struct eth_tx_bd_flags {
1888 u8 as_bitfield;
1889#define ETH_TX_BD_FLAGS_VLAN_TAG (0x1<<0)
1890#define ETH_TX_BD_FLAGS_VLAN_TAG_SHIFT 0
1891#define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<1)
1892#define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 1
1893#define ETH_TX_BD_FLAGS_TCP_CSUM (0x1<<2)
1894#define ETH_TX_BD_FLAGS_TCP_CSUM_SHIFT 2
1895#define ETH_TX_BD_FLAGS_END_BD (0x1<<3)
1896#define ETH_TX_BD_FLAGS_END_BD_SHIFT 3
1897#define ETH_TX_BD_FLAGS_START_BD (0x1<<4)
1898#define ETH_TX_BD_FLAGS_START_BD_SHIFT 4
1899#define ETH_TX_BD_FLAGS_HDR_POOL (0x1<<5)
1900#define ETH_TX_BD_FLAGS_HDR_POOL_SHIFT 5
1901#define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6)
1902#define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6
1903#define ETH_TX_BD_FLAGS_IPV6 (0x1<<7)
1904#define ETH_TX_BD_FLAGS_IPV6_SHIFT 7
1905};
1906
1907/*
1908 * The eth Tx Buffer Descriptor
1909 */
1910struct eth_tx_bd {
1911 u32 addr_lo;
1912 u32 addr_hi;
1913 u16 nbd;
1914 u16 nbytes;
1915 u16 vlan;
1916 struct eth_tx_bd_flags bd_flags;
1917 u8 general_data;
1918#define ETH_TX_BD_HDR_NBDS (0x3F<<0)
1919#define ETH_TX_BD_HDR_NBDS_SHIFT 0
1920#define ETH_TX_BD_ETH_ADDR_TYPE (0x3<<6)
1921#define ETH_TX_BD_ETH_ADDR_TYPE_SHIFT 6
1922};
1923
1924/*
1925 * Tx parsing BD structure for ETH,Relevant in START
1926 */
1927struct eth_tx_parse_bd {
1928 u8 global_data;
1929#define ETH_TX_PARSE_BD_IP_HDR_START_OFFSET (0xF<<0)
1930#define ETH_TX_PARSE_BD_IP_HDR_START_OFFSET_SHIFT 0
1931#define ETH_TX_PARSE_BD_CS_ANY_FLG (0x1<<4)
1932#define ETH_TX_PARSE_BD_CS_ANY_FLG_SHIFT 4
1933#define ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN (0x1<<5)
1934#define ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN_SHIFT 5
1935#define ETH_TX_PARSE_BD_LLC_SNAP_EN (0x1<<6)
1936#define ETH_TX_PARSE_BD_LLC_SNAP_EN_SHIFT 6
1937#define ETH_TX_PARSE_BD_NS_FLG (0x1<<7)
1938#define ETH_TX_PARSE_BD_NS_FLG_SHIFT 7
1939 u8 tcp_flags;
1940#define ETH_TX_PARSE_BD_FIN_FLG (0x1<<0)
1941#define ETH_TX_PARSE_BD_FIN_FLG_SHIFT 0
1942#define ETH_TX_PARSE_BD_SYN_FLG (0x1<<1)
1943#define ETH_TX_PARSE_BD_SYN_FLG_SHIFT 1
1944#define ETH_TX_PARSE_BD_RST_FLG (0x1<<2)
1945#define ETH_TX_PARSE_BD_RST_FLG_SHIFT 2
1946#define ETH_TX_PARSE_BD_PSH_FLG (0x1<<3)
1947#define ETH_TX_PARSE_BD_PSH_FLG_SHIFT 3
1948#define ETH_TX_PARSE_BD_ACK_FLG (0x1<<4)
1949#define ETH_TX_PARSE_BD_ACK_FLG_SHIFT 4
1950#define ETH_TX_PARSE_BD_URG_FLG (0x1<<5)
1951#define ETH_TX_PARSE_BD_URG_FLG_SHIFT 5
1952#define ETH_TX_PARSE_BD_ECE_FLG (0x1<<6)
1953#define ETH_TX_PARSE_BD_ECE_FLG_SHIFT 6
1954#define ETH_TX_PARSE_BD_CWR_FLG (0x1<<7)
1955#define ETH_TX_PARSE_BD_CWR_FLG_SHIFT 7
1956 u8 ip_hlen;
1957 s8 cs_offset;
1958 u16 total_hlen;
1959 u16 lso_mss;
1960 u16 tcp_pseudo_csum;
1961 u16 ip_id;
1962 u32 tcp_send_seq;
1963};
1964
1965/*
1966 * The last BD in the BD memory will hold a pointer to the next BD memory
1967 */
1968struct eth_tx_next_bd {
1969 u32 addr_lo;
1970 u32 addr_hi;
1971 u8 reserved[8];
1972};
1973
1974/*
1975 * union for 3 Bd types
1976 */
1977union eth_tx_bd_types {
1978 struct eth_tx_bd reg_bd;
1979 struct eth_tx_parse_bd parse_bd;
1980 struct eth_tx_next_bd next_bd;
1981};
1982
1983/*
1984 * The eth storm context of Xstorm
1985 */
1986struct xstorm_eth_st_context {
1987 u32 tx_bd_page_base_lo;
1988 u32 tx_bd_page_base_hi;
1989#if defined(__BIG_ENDIAN)
1990 u16 tx_bd_cons;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001991 u8 statistics_data;
1992#define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID (0x7F<<0)
1993#define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID_SHIFT 0
1994#define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE (0x1<<7)
1995#define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE_SHIFT 7
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001996 u8 __local_tx_bd_prod;
1997#elif defined(__LITTLE_ENDIAN)
1998 u8 __local_tx_bd_prod;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001999 u8 statistics_data;
2000#define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID (0x7F<<0)
2001#define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID_SHIFT 0
2002#define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE (0x1<<7)
2003#define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE_SHIFT 7
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002004 u16 tx_bd_cons;
2005#endif
2006 u32 db_data_addr_lo;
2007 u32 db_data_addr_hi;
2008 u32 __pkt_cons;
2009 u32 __gso_next;
2010 u32 is_eth_conn_1b;
2011 union eth_tx_bd_types __bds[13];
2012};
2013
2014/*
2015 * The eth storm context of Cstorm
2016 */
2017struct cstorm_eth_st_context {
2018#if defined(__BIG_ENDIAN)
2019 u16 __reserved0;
2020 u8 sb_index_number;
2021 u8 status_block_id;
2022#elif defined(__LITTLE_ENDIAN)
2023 u8 status_block_id;
2024 u8 sb_index_number;
2025 u16 __reserved0;
2026#endif
2027 u32 __reserved1[3];
2028};
2029
2030/*
2031 * Ethernet connection context
2032 */
2033struct eth_context {
2034 struct ustorm_eth_st_context ustorm_st_context;
2035 struct tstorm_eth_st_context tstorm_st_context;
2036 struct xstorm_eth_ag_context xstorm_ag_context;
2037 struct tstorm_eth_ag_context tstorm_ag_context;
2038 struct cstorm_eth_ag_context cstorm_ag_context;
2039 struct ustorm_eth_ag_context ustorm_ag_context;
2040 struct timers_block_context timers_context;
2041 struct xstorm_eth_st_context xstorm_st_context;
2042 struct cstorm_eth_st_context cstorm_st_context;
2043};
2044
2045
2046/*
2047 * ethernet doorbell
2048 */
2049struct eth_tx_doorbell {
2050#if defined(__BIG_ENDIAN)
2051 u16 npackets;
2052 u8 params;
2053#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
2054#define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
2055#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
2056#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
2057#define ETH_TX_DOORBELL_SPARE (0x1<<7)
2058#define ETH_TX_DOORBELL_SPARE_SHIFT 7
2059 struct doorbell_hdr hdr;
2060#elif defined(__LITTLE_ENDIAN)
2061 struct doorbell_hdr hdr;
2062 u8 params;
2063#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
2064#define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
2065#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
2066#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
2067#define ETH_TX_DOORBELL_SPARE (0x1<<7)
2068#define ETH_TX_DOORBELL_SPARE_SHIFT 7
2069 u16 npackets;
2070#endif
2071};
2072
2073
2074/*
2075 * ustorm status block
2076 */
2077struct ustorm_def_status_block {
2078 u16 index_values[HC_USTORM_DEF_SB_NUM_INDICES];
2079 u16 status_block_index;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002080 u8 func;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002081 u8 status_block_id;
2082 u32 __flags;
2083};
2084
2085/*
2086 * cstorm status block
2087 */
2088struct cstorm_def_status_block {
2089 u16 index_values[HC_CSTORM_DEF_SB_NUM_INDICES];
2090 u16 status_block_index;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002091 u8 func;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002092 u8 status_block_id;
2093 u32 __flags;
2094};
2095
2096/*
2097 * xstorm status block
2098 */
2099struct xstorm_def_status_block {
2100 u16 index_values[HC_XSTORM_DEF_SB_NUM_INDICES];
2101 u16 status_block_index;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002102 u8 func;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002103 u8 status_block_id;
2104 u32 __flags;
2105};
2106
2107/*
2108 * tstorm status block
2109 */
2110struct tstorm_def_status_block {
2111 u16 index_values[HC_TSTORM_DEF_SB_NUM_INDICES];
2112 u16 status_block_index;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002113 u8 func;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002114 u8 status_block_id;
2115 u32 __flags;
2116};
2117
2118/*
2119 * host status block
2120 */
2121struct host_def_status_block {
2122 struct atten_def_status_block atten_status_block;
2123 struct ustorm_def_status_block u_def_status_block;
2124 struct cstorm_def_status_block c_def_status_block;
2125 struct xstorm_def_status_block x_def_status_block;
2126 struct tstorm_def_status_block t_def_status_block;
2127};
2128
2129
2130/*
2131 * ustorm status block
2132 */
2133struct ustorm_status_block {
2134 u16 index_values[HC_USTORM_SB_NUM_INDICES];
2135 u16 status_block_index;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002136 u8 func;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002137 u8 status_block_id;
2138 u32 __flags;
2139};
2140
2141/*
2142 * cstorm status block
2143 */
2144struct cstorm_status_block {
2145 u16 index_values[HC_CSTORM_SB_NUM_INDICES];
2146 u16 status_block_index;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002147 u8 func;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002148 u8 status_block_id;
2149 u32 __flags;
2150};
2151
2152/*
2153 * host status block
2154 */
2155struct host_status_block {
2156 struct ustorm_status_block u_status_block;
2157 struct cstorm_status_block c_status_block;
2158};
2159
2160
2161/*
2162 * The data for RSS setup ramrod
2163 */
2164struct eth_client_setup_ramrod_data {
2165 u32 client_id_5b;
2166 u8 is_rdma_1b;
2167 u8 reserved0;
2168 u16 reserved1;
2169};
2170
2171
2172/*
2173 * L2 dynamic host coalescing init parameters
2174 */
2175struct eth_dynamic_hc_config {
2176 u32 threshold[3];
2177 u8 hc_timeout[4];
2178};
2179
2180
2181/*
2182 * regular eth FP CQE parameters struct
2183 */
2184struct eth_fast_path_rx_cqe {
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002185 u8 type_error_flags;
2186#define ETH_FAST_PATH_RX_CQE_TYPE (0x1<<0)
2187#define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0
2188#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<1)
2189#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 1
2190#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<2)
2191#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 2
2192#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<3)
2193#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 3
2194#define ETH_FAST_PATH_RX_CQE_START_FLG (0x1<<4)
2195#define ETH_FAST_PATH_RX_CQE_START_FLG_SHIFT 4
2196#define ETH_FAST_PATH_RX_CQE_END_FLG (0x1<<5)
2197#define ETH_FAST_PATH_RX_CQE_END_FLG_SHIFT 5
2198#define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6)
2199#define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002200 u8 status_flags;
2201#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0)
2202#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
2203#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3)
2204#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3
2205#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4)
2206#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4
2207#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5)
2208#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5
2209#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6)
2210#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6
2211#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7)
2212#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7
2213 u8 placement_offset;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002214 u8 queue_index;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002215 u32 rss_hash_result;
2216 u16 vlan_tag;
2217 u16 pkt_len;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002218 u16 len_on_bd;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002219 struct parsing_flags pars_flags;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002220 u16 sgl[8];
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002221};
2222
2223
2224/*
2225 * The data for RSS setup ramrod
2226 */
2227struct eth_halt_ramrod_data {
2228 u32 client_id_5b;
2229 u32 reserved0;
2230};
2231
2232
2233/*
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002234 * The data for statistics query ramrod
2235 */
2236struct eth_query_ramrod_data {
2237#if defined(__BIG_ENDIAN)
2238 u8 reserved0;
2239 u8 collect_port_1b;
2240 u16 drv_counter;
2241#elif defined(__LITTLE_ENDIAN)
2242 u16 drv_counter;
2243 u8 collect_port_1b;
2244 u8 reserved0;
2245#endif
2246 u32 ctr_id_vector;
2247};
2248
2249
2250/*
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002251 * Place holder for ramrods protocol specific data
2252 */
2253struct ramrod_data {
2254 u32 data_lo;
2255 u32 data_hi;
2256};
2257
2258/*
2259 * union for ramrod data for ethernet protocol (CQE) (force size of 16 bits)
2260 */
2261union eth_ramrod_data {
2262 struct ramrod_data general;
2263};
2264
2265
2266/*
2267 * Rx Last BD in page (in ETH)
2268 */
2269struct eth_rx_bd_next_page {
2270 u32 addr_lo;
2271 u32 addr_hi;
2272 u8 reserved[8];
2273};
2274
2275
2276/*
2277 * Eth Rx Cqe structure- general structure for ramrods
2278 */
2279struct common_ramrod_eth_rx_cqe {
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002280 u8 ramrod_type;
2281#define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x1<<0)
2282#define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0
2283#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x7F<<1)
2284#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 1
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002285 u8 conn_type_3b;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002286 u16 reserved1;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002287 u32 conn_and_cmd_data;
2288#define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0)
2289#define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
2290#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24)
2291#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24
2292 struct ramrod_data protocol_data;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002293 u32 reserved2[4];
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002294};
2295
2296/*
2297 * Rx Last CQE in page (in ETH)
2298 */
2299struct eth_rx_cqe_next_page {
2300 u32 addr_lo;
2301 u32 addr_hi;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002302 u32 reserved[6];
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002303};
2304
2305/*
2306 * union for all eth rx cqe types (fix their sizes)
2307 */
2308union eth_rx_cqe {
2309 struct eth_fast_path_rx_cqe fast_path_cqe;
2310 struct common_ramrod_eth_rx_cqe ramrod_cqe;
2311 struct eth_rx_cqe_next_page next_page_cqe;
2312};
2313
2314
2315/*
2316 * common data for all protocols
2317 */
2318struct spe_hdr {
2319 u32 conn_and_cmd_data;
2320#define SPE_HDR_CID (0xFFFFFF<<0)
2321#define SPE_HDR_CID_SHIFT 0
2322#define SPE_HDR_CMD_ID (0xFF<<24)
2323#define SPE_HDR_CMD_ID_SHIFT 24
2324 u16 type;
2325#define SPE_HDR_CONN_TYPE (0xFF<<0)
2326#define SPE_HDR_CONN_TYPE_SHIFT 0
2327#define SPE_HDR_COMMON_RAMROD (0xFF<<8)
2328#define SPE_HDR_COMMON_RAMROD_SHIFT 8
2329 u16 reserved;
2330};
2331
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002332/*
2333 * ethernet slow path element
2334 */
2335union eth_specific_data {
2336 u8 protocol_data[8];
2337 struct regpair mac_config_addr;
2338 struct eth_client_setup_ramrod_data client_setup_ramrod_data;
2339 struct eth_halt_ramrod_data halt_ramrod_data;
2340 struct regpair leading_cqe_addr;
2341 struct regpair update_data_addr;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002342 struct eth_query_ramrod_data query_ramrod_data;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002343};
2344
2345/*
2346 * ethernet slow path element
2347 */
2348struct eth_spe {
2349 struct spe_hdr hdr;
2350 union eth_specific_data data;
2351};
2352
2353
2354/*
2355 * doorbell data in host memory
2356 */
2357struct eth_tx_db_data {
2358 u32 packets_prod;
2359 u16 bds_prod;
2360 u16 reserved;
2361};
2362
2363
2364/*
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002365 * Common configuration parameters per function in Tstorm
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002366 */
2367struct tstorm_eth_function_common_config {
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002368#if defined(__BIG_ENDIAN)
2369 u8 leading_client_id;
2370 u8 rss_result_mask;
2371 u16 config_flags;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002372#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
2373#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
2374#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
2375#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
2376#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
2377#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
2378#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
2379#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
2380#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE (0x1<<4)
2381#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE_SHIFT 4
2382#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<5)
2383#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 5
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002384#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM (0x1<<6)
2385#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 6
2386#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x1FF<<7)
2387#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 7
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002388#elif defined(__LITTLE_ENDIAN)
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002389 u16 config_flags;
2390#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
2391#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
2392#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
2393#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
2394#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
2395#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
2396#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
2397#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
2398#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE (0x1<<4)
2399#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE_SHIFT 4
2400#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<5)
2401#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 5
2402#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM (0x1<<6)
2403#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 6
2404#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x1FF<<7)
2405#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 7
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002406 u8 rss_result_mask;
2407 u8 leading_client_id;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002408#endif
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002409 u16 vlan_id[2];
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002410};
2411
2412/*
2413 * parameters for eth update ramrod
2414 */
2415struct eth_update_ramrod_data {
2416 struct tstorm_eth_function_common_config func_config;
2417 u8 indirectionTable[128];
2418};
2419
2420
2421/*
2422 * MAC filtering configuration command header
2423 */
2424struct mac_configuration_hdr {
2425 u8 length_6b;
2426 u8 offset;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002427 u16 client_id;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002428 u32 reserved1;
2429};
2430
2431/*
2432 * MAC address in list for ramrod
2433 */
2434struct tstorm_cam_entry {
2435 u16 lsb_mac_addr;
2436 u16 middle_mac_addr;
2437 u16 msb_mac_addr;
2438 u16 flags;
2439#define TSTORM_CAM_ENTRY_PORT_ID (0x1<<0)
2440#define TSTORM_CAM_ENTRY_PORT_ID_SHIFT 0
2441#define TSTORM_CAM_ENTRY_RSRVVAL0 (0x7<<1)
2442#define TSTORM_CAM_ENTRY_RSRVVAL0_SHIFT 1
2443#define TSTORM_CAM_ENTRY_RESERVED0 (0xFFF<<4)
2444#define TSTORM_CAM_ENTRY_RESERVED0_SHIFT 4
2445};
2446
2447/*
2448 * MAC filtering: CAM target table entry
2449 */
2450struct tstorm_cam_target_table_entry {
2451 u8 flags;
2452#define TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST (0x1<<0)
2453#define TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST_SHIFT 0
2454#define TSTORM_CAM_TARGET_TABLE_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<1)
2455#define TSTORM_CAM_TARGET_TABLE_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 1
2456#define TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE (0x1<<2)
2457#define TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE_SHIFT 2
2458#define TSTORM_CAM_TARGET_TABLE_ENTRY_RDMA_MAC (0x1<<3)
2459#define TSTORM_CAM_TARGET_TABLE_ENTRY_RDMA_MAC_SHIFT 3
2460#define TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0 (0xF<<4)
2461#define TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0_SHIFT 4
2462 u8 client_id;
2463 u16 vlan_id;
2464};
2465
2466/*
2467 * MAC address in list for ramrod
2468 */
2469struct mac_configuration_entry {
2470 struct tstorm_cam_entry cam_entry;
2471 struct tstorm_cam_target_table_entry target_table_entry;
2472};
2473
2474/*
2475 * MAC filtering configuration command
2476 */
2477struct mac_configuration_cmd {
2478 struct mac_configuration_hdr hdr;
2479 struct mac_configuration_entry config_table[64];
2480};
2481
2482
2483/*
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002484 * MAC address in list for ramrod
2485 */
2486struct mac_configuration_entry_e1h {
2487 u16 lsb_mac_addr;
2488 u16 middle_mac_addr;
2489 u16 msb_mac_addr;
2490 u16 vlan_id;
2491 u16 e1hov_id;
2492 u8 client_id;
2493 u8 flags;
2494#define MAC_CONFIGURATION_ENTRY_E1H_PORT (0x1<<0)
2495#define MAC_CONFIGURATION_ENTRY_E1H_PORT_SHIFT 0
2496#define MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE (0x1<<1)
2497#define MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE_SHIFT 1
2498#define MAC_CONFIGURATION_ENTRY_E1H_RDMA_MAC (0x1<<2)
2499#define MAC_CONFIGURATION_ENTRY_E1H_RDMA_MAC_SHIFT 2
2500#define MAC_CONFIGURATION_ENTRY_E1H_RESERVED0 (0x1F<<3)
2501#define MAC_CONFIGURATION_ENTRY_E1H_RESERVED0_SHIFT 3
2502};
2503
2504/*
2505 * MAC filtering configuration command
2506 */
2507struct mac_configuration_cmd_e1h {
2508 struct mac_configuration_hdr hdr;
2509 struct mac_configuration_entry_e1h config_table[32];
2510};
2511
2512
2513/*
2514 * approximate-match multicast filtering for E1H per function in Tstorm
2515 */
2516struct tstorm_eth_approximate_match_multicast_filtering {
2517 u32 mcast_add_hash_bit_array[8];
2518};
2519
2520
2521/*
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002522 * Configuration parameters per client in Tstorm
2523 */
2524struct tstorm_eth_client_config {
2525#if defined(__BIG_ENDIAN)
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002526 u8 max_sges_for_packet;
2527 u8 statistics_counter_id;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002528 u16 mtu;
2529#elif defined(__LITTLE_ENDIAN)
2530 u16 mtu;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002531 u8 statistics_counter_id;
2532 u8 max_sges_for_packet;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002533#endif
2534#if defined(__BIG_ENDIAN)
2535 u16 drop_flags;
2536#define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR (0x1<<0)
2537#define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0
2538#define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR (0x1<<1)
2539#define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR_SHIFT 1
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002540#define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 (0x1<<2)
2541#define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 2
2542#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<3)
2543#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 3
2544#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0xFFF<<4)
2545#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 4
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002546 u16 config_flags;
2547#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE (0x1<<0)
2548#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE_SHIFT 0
2549#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<1)
2550#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 1
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002551#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING (0x1<<2)
2552#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING_SHIFT 2
2553#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0x1FFF<<3)
2554#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 3
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002555#elif defined(__LITTLE_ENDIAN)
2556 u16 config_flags;
2557#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE (0x1<<0)
2558#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE_SHIFT 0
2559#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<1)
2560#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 1
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002561#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING (0x1<<2)
2562#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING_SHIFT 2
2563#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0x1FFF<<3)
2564#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 3
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002565 u16 drop_flags;
2566#define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR (0x1<<0)
2567#define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0
2568#define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR (0x1<<1)
2569#define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR_SHIFT 1
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002570#define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 (0x1<<2)
2571#define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 2
2572#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<3)
2573#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 3
2574#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0xFFF<<4)
2575#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 4
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002576#endif
2577};
2578
2579
2580/*
2581 * MAC filtering configuration parameters per port in Tstorm
2582 */
2583struct tstorm_eth_mac_filter_config {
2584 u32 ucast_drop_all;
2585 u32 ucast_accept_all;
2586 u32 mcast_drop_all;
2587 u32 mcast_accept_all;
2588 u32 bcast_drop_all;
2589 u32 bcast_accept_all;
2590 u32 strict_vlan;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002591 u32 vlan_filter[2];
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002592 u32 reserved;
2593};
2594
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002595
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002596/*
2597 * Three RX producers for ETH
2598 */
2599struct tstorm_eth_rx_producers {
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002600#if defined(__BIG_ENDIAN)
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002601 u16 bd_prod;
2602 u16 cqe_prod;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002603#elif defined(__LITTLE_ENDIAN)
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002604 u16 cqe_prod;
2605 u16 bd_prod;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002606#endif
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002607#if defined(__BIG_ENDIAN)
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002608 u16 reserved;
2609 u16 sge_prod;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002610#elif defined(__LITTLE_ENDIAN)
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002611 u16 sge_prod;
2612 u16 reserved;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002613#endif
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002614};
2615
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002616
2617/*
2618 * common flag to indicate existance of TPA.
2619 */
2620struct tstorm_eth_tpa_exist {
2621#if defined(__BIG_ENDIAN)
2622 u16 reserved1;
2623 u8 reserved0;
2624 u8 tpa_exist;
2625#elif defined(__LITTLE_ENDIAN)
2626 u8 tpa_exist;
2627 u8 reserved0;
2628 u16 reserved1;
2629#endif
2630 u32 reserved2;
2631};
2632
2633
2634/*
2635 * per-port SAFC demo variables
2636 */
2637struct cmng_flags_per_port {
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002638 u8 con_number[NUM_OF_PROTOCOLS];
2639#if defined(__BIG_ENDIAN)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002640 u8 fairness_enable;
2641 u8 rate_shaping_enable;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002642 u8 cmng_protocol_enable;
2643 u8 cmng_vn_enable;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002644#elif defined(__LITTLE_ENDIAN)
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002645 u8 cmng_vn_enable;
2646 u8 cmng_protocol_enable;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002647 u8 rate_shaping_enable;
2648 u8 fairness_enable;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002649#endif
2650};
2651
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002652
2653/*
2654 * per-port rate shaping variables
2655 */
2656struct rate_shaping_vars_per_port {
2657 u32 rs_periodic_timeout;
2658 u32 rs_threshold;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002659};
2660
2661
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002662/*
2663 * per-port fairness variables
2664 */
2665struct fairness_vars_per_port {
2666 u32 upper_bound;
2667 u32 fair_threshold;
2668 u32 fairness_timeout;
2669};
2670
2671
2672/*
2673 * per-port SAFC variables
2674 */
2675struct safc_struct_per_port {
2676#if defined(__BIG_ENDIAN)
2677 u16 __reserved0;
2678 u8 cur_cos_types;
2679 u8 safc_timeout_usec;
2680#elif defined(__LITTLE_ENDIAN)
2681 u8 safc_timeout_usec;
2682 u8 cur_cos_types;
2683 u16 __reserved0;
2684#endif
2685 u8 cos_to_protocol[MAX_COS_NUMBER];
2686};
2687
2688
2689/*
2690 * Per-port congestion management variables
2691 */
2692struct cmng_struct_per_port {
2693 struct rate_shaping_vars_per_port rs_vars;
2694 struct fairness_vars_per_port fair_vars;
2695 struct safc_struct_per_port safc_vars;
2696 struct cmng_flags_per_port flags;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002697};
2698
2699
2700/*
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07002701 * Protocol-common statistics collected by the Xstorm (per client)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002702 */
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07002703struct xstorm_per_client_stats {
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002704 struct regpair total_sent_bytes;
2705 u32 total_sent_pkts;
2706 u32 unicast_pkts_sent;
2707 struct regpair unicast_bytes_sent;
2708 struct regpair multicast_bytes_sent;
2709 u32 multicast_pkts_sent;
2710 u32 broadcast_pkts_sent;
2711 struct regpair broadcast_bytes_sent;
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07002712 u16 stats_counter;
2713 u16 reserved0;
2714 u32 reserved1;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002715};
2716
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07002717
2718/*
2719 * Common statistics collected by the Xstorm (per port)
2720 */
2721struct xstorm_common_stats {
2722 struct xstorm_per_client_stats client_statistics[MAX_X_STAT_COUNTER_ID];
2723};
2724
2725
2726/*
2727 * Protocol-common statistics collected by the Tstorm (per port)
2728 */
2729struct tstorm_per_port_stats {
2730 u32 mac_filter_discard;
2731 u32 xxoverflow_discard;
2732 u32 brb_truncate_discard;
2733 u32 mac_discard;
2734};
2735
2736
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002737/*
2738 * Protocol-common statistics collected by the Tstorm (per client)
2739 */
2740struct tstorm_per_client_stats {
2741 struct regpair total_rcv_bytes;
2742 struct regpair rcv_unicast_bytes;
2743 struct regpair rcv_broadcast_bytes;
2744 struct regpair rcv_multicast_bytes;
2745 struct regpair rcv_error_bytes;
2746 u32 checksum_discard;
2747 u32 packets_too_big_discard;
2748 u32 total_rcv_pkts;
2749 u32 rcv_unicast_pkts;
2750 u32 rcv_broadcast_pkts;
2751 u32 rcv_multicast_pkts;
2752 u32 no_buff_discard;
2753 u32 ttl0_discard;
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07002754 u16 stats_counter;
2755 u16 reserved0;
2756 u32 reserved1;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002757};
2758
2759/*
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07002760 * Protocol-common statistics collected by the Tstorm
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002761 */
2762struct tstorm_common_stats {
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07002763 struct tstorm_per_port_stats port_statistics;
2764 struct tstorm_per_client_stats client_statistics[MAX_T_STAT_COUNTER_ID];
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002765};
2766
2767/*
2768 * Eth statistics query sturcture for the eth_stats_quesry ramrod
2769 */
2770struct eth_stats_query {
2771 struct xstorm_common_stats xstorm_common;
2772 struct tstorm_common_stats tstorm_common;
2773};
2774
2775
2776/*
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002777 * per-vnic fairness variables
2778 */
2779struct fairness_vars_per_vn {
2780 u32 protocol_credit_delta[NUM_OF_PROTOCOLS];
2781 u32 vn_credit_delta;
2782 u32 __reserved0;
2783};
2784
2785
2786/*
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002787 * FW version stored in the Xstorm RAM
2788 */
2789struct fw_version {
2790#if defined(__BIG_ENDIAN)
2791 u16 patch;
2792 u8 primary;
2793 u8 client;
2794#elif defined(__LITTLE_ENDIAN)
2795 u8 client;
2796 u8 primary;
2797 u16 patch;
2798#endif
2799 u32 flags;
2800#define FW_VERSION_OPTIMIZED (0x1<<0)
2801#define FW_VERSION_OPTIMIZED_SHIFT 0
2802#define FW_VERSION_BIG_ENDIEN (0x1<<1)
2803#define FW_VERSION_BIG_ENDIEN_SHIFT 1
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002804#define FW_VERSION_CHIP_VERSION (0x3<<2)
2805#define FW_VERSION_CHIP_VERSION_SHIFT 2
2806#define __FW_VERSION_RESERVED (0xFFFFFFF<<4)
2807#define __FW_VERSION_RESERVED_SHIFT 4
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002808};
2809
2810
2811/*
2812 * FW version stored in first line of pram
2813 */
2814struct pram_fw_version {
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002815 u8 client;
2816 u8 primary;
2817 u16 patch;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002818 u8 flags;
2819#define PRAM_FW_VERSION_OPTIMIZED (0x1<<0)
2820#define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0
2821#define PRAM_FW_VERSION_STORM_ID (0x3<<1)
2822#define PRAM_FW_VERSION_STORM_ID_SHIFT 1
2823#define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3)
2824#define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002825#define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4)
2826#define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4
2827#define __PRAM_FW_VERSION_RESERVED0 (0x3<<6)
2828#define __PRAM_FW_VERSION_RESERVED0_SHIFT 6
2829};
2830
2831
2832/*
2833 * a single rate shaping counter. can be used as protocol or vnic counter
2834 */
2835struct rate_shaping_counter {
2836 u32 quota;
2837#if defined(__BIG_ENDIAN)
2838 u16 __reserved0;
2839 u16 rate;
2840#elif defined(__LITTLE_ENDIAN)
2841 u16 rate;
2842 u16 __reserved0;
2843#endif
2844};
2845
2846
2847/*
2848 * per-vnic rate shaping variables
2849 */
2850struct rate_shaping_vars_per_vn {
2851 struct rate_shaping_counter protocol_counters[NUM_OF_PROTOCOLS];
2852 struct rate_shaping_counter vn_counter;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002853};
2854
2855
2856/*
2857 * The send queue element
2858 */
2859struct slow_path_element {
2860 struct spe_hdr hdr;
2861 u8 protocol_data[8];
2862};
2863
2864
2865/*
2866 * eth/toe flags that indicate if to query
2867 */
2868struct stats_indication_flags {
2869 u32 collect_eth;
2870 u32 collect_toe;
2871};
2872
2873