Graf Yang | 5be36d2 | 2008-04-25 03:09:15 +0800 | [diff] [blame] | 1 | /* |
| 2 | * file: include/asm-blackfin/mach-bf533/bfin_serial_5xx.h |
| 3 | * based on: |
| 4 | * author: |
| 5 | * |
| 6 | * created: |
| 7 | * description: |
| 8 | * blackfin serial driver head file |
| 9 | * rev: |
| 10 | * |
| 11 | * modified: |
| 12 | * |
| 13 | * |
| 14 | * bugs: enter bugs at http://blackfin.uclinux.org/ |
| 15 | * |
| 16 | * this program is free software; you can redistribute it and/or modify |
| 17 | * it under the terms of the gnu general public license as published by |
| 18 | * the free software foundation; either version 2, or (at your option) |
| 19 | * any later version. |
| 20 | * |
| 21 | * this program is distributed in the hope that it will be useful, |
| 22 | * but without any warranty; without even the implied warranty of |
| 23 | * merchantability or fitness for a particular purpose. see the |
| 24 | * gnu general public license for more details. |
| 25 | * |
| 26 | * you should have received a copy of the gnu general public license |
| 27 | * along with this program; see the file copying. |
| 28 | * if not, write to the free software foundation, |
| 29 | * 59 temple place - suite 330, boston, ma 02111-1307, usa. |
| 30 | */ |
| 31 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 32 | #include <linux/serial.h> |
| 33 | #include <asm/dma.h> |
Michael Hennerich | c58c214 | 2007-10-04 00:35:05 +0800 | [diff] [blame] | 34 | #include <asm/portmux.h> |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 35 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 36 | #define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR)) |
| 37 | #define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL)) |
| 38 | #define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER)) |
| 39 | #define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH)) |
| 40 | #define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR)) |
| 41 | #define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR)) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 42 | #define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL)) |
| 43 | |
| 44 | #define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v) |
| 45 | #define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v) |
| 46 | #define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v) |
Mike Frysinger | 89bf6dc | 2008-05-07 11:41:26 +0800 | [diff] [blame] | 47 | #define UART_SET_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v)) |
| 48 | #define UART_CLEAR_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v)) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 49 | #define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v) |
| 50 | #define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v) |
| 51 | #define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v) |
| 52 | |
Mike Frysinger | 45828b8 | 2008-05-07 11:41:26 +0800 | [diff] [blame] | 53 | #define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0) |
| 54 | #define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0) |
| 55 | |
Sonic Zhang | 1feaa51 | 2008-06-03 12:19:45 +0800 | [diff] [blame] | 56 | #define UART_GET_CTS(x) gpio_get_value(x->cts_pin) |
| 57 | #define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1) |
| 58 | #define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0) |
| 59 | #define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v) |
| 60 | #define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0) |
| 61 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 62 | #ifdef CONFIG_BFIN_UART0_CTSRTS |
| 63 | # define CONFIG_SERIAL_BFIN_CTSRTS |
| 64 | # ifndef CONFIG_UART0_CTS_PIN |
| 65 | # define CONFIG_UART0_CTS_PIN -1 |
| 66 | # endif |
| 67 | # ifndef CONFIG_UART0_RTS_PIN |
| 68 | # define CONFIG_UART0_RTS_PIN -1 |
| 69 | # endif |
| 70 | #endif |
| 71 | |
| 72 | struct bfin_serial_port { |
| 73 | struct uart_port port; |
| 74 | unsigned int old_status; |
Mike Frysinger | 0bcfd70 | 2007-12-24 19:40:05 +0800 | [diff] [blame] | 75 | unsigned int lsr; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 76 | #ifdef CONFIG_SERIAL_BFIN_DMA |
| 77 | int tx_done; |
| 78 | int tx_count; |
| 79 | struct circ_buf rx_dma_buf; |
| 80 | struct timer_list rx_dma_timer; |
| 81 | int rx_dma_nrows; |
| 82 | unsigned int tx_dma_channel; |
| 83 | unsigned int rx_dma_channel; |
| 84 | struct work_struct tx_dma_workqueue; |
| 85 | #else |
Mike Frysinger | 8851c71 | 2007-12-24 19:48:04 +0800 | [diff] [blame] | 86 | # if ANOMALY_05000230 |
| 87 | unsigned int anomaly_threshold; |
| 88 | # endif |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 89 | #endif |
| 90 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS |
Sonic Zhang | 4cb4f22 | 2008-02-02 14:29:25 +0800 | [diff] [blame] | 91 | struct work_struct cts_workqueue; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 92 | int cts_pin; |
| 93 | int rts_pin; |
| 94 | #endif |
| 95 | }; |
| 96 | |
Mike Frysinger | 0bcfd70 | 2007-12-24 19:40:05 +0800 | [diff] [blame] | 97 | /* The hardware clears the LSR bits upon read, so we need to cache |
| 98 | * some of the more fun bits in software so they don't get lost |
| 99 | * when checking the LSR in other code paths (TX). |
| 100 | */ |
| 101 | static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart) |
| 102 | { |
| 103 | unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR); |
| 104 | uart->lsr |= (lsr & (BI|FE|PE|OE)); |
| 105 | return lsr | uart->lsr; |
| 106 | } |
| 107 | |
| 108 | static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart) |
| 109 | { |
| 110 | uart->lsr = 0; |
| 111 | bfin_write16(uart->port.membase + OFFSET_LSR, -1); |
| 112 | } |
| 113 | |
Graf Yang | 5be36d2 | 2008-04-25 03:09:15 +0800 | [diff] [blame] | 114 | struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS]; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 115 | struct bfin_serial_res { |
| 116 | unsigned long uart_base_addr; |
| 117 | int uart_irq; |
| 118 | #ifdef CONFIG_SERIAL_BFIN_DMA |
| 119 | unsigned int uart_tx_dma_channel; |
| 120 | unsigned int uart_rx_dma_channel; |
| 121 | #endif |
| 122 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS |
| 123 | int uart_cts_pin; |
| 124 | int uart_rts_pin; |
| 125 | #endif |
| 126 | }; |
| 127 | |
| 128 | struct bfin_serial_res bfin_serial_resource[] = { |
Mike Frysinger | 9c8f172 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 129 | { |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 130 | 0xFFC00400, |
| 131 | IRQ_UART_RX, |
| 132 | #ifdef CONFIG_SERIAL_BFIN_DMA |
| 133 | CH_UART_TX, |
| 134 | CH_UART_RX, |
| 135 | #endif |
| 136 | #ifdef CONFIG_BFIN_UART0_CTSRTS |
| 137 | CONFIG_UART0_CTS_PIN, |
| 138 | CONFIG_UART0_RTS_PIN, |
| 139 | #endif |
Mike Frysinger | 9c8f172 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 140 | } |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 141 | }; |
| 142 | |
Michael Hennerich | c58c214 | 2007-10-04 00:35:05 +0800 | [diff] [blame] | 143 | #define DRIVER_NAME "bfin-uart" |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 144 | |
Graf Yang | 5be36d2 | 2008-04-25 03:09:15 +0800 | [diff] [blame] | 145 | int nr_ports = BFIN_UART_NR_PORTS; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 146 | static void bfin_serial_hw_init(struct bfin_serial_port *uart) |
| 147 | { |
| 148 | |
Michael Hennerich | c58c214 | 2007-10-04 00:35:05 +0800 | [diff] [blame] | 149 | #ifdef CONFIG_SERIAL_BFIN_UART0 |
| 150 | peripheral_request(P_UART0_TX, DRIVER_NAME); |
| 151 | peripheral_request(P_UART0_RX, DRIVER_NAME); |
| 152 | #endif |
| 153 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 154 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS |
| 155 | if (uart->cts_pin >= 0) { |
Michael Hennerich | c58c214 | 2007-10-04 00:35:05 +0800 | [diff] [blame] | 156 | gpio_request(uart->cts_pin, DRIVER_NAME); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 157 | gpio_direction_input(uart->cts_pin); |
| 158 | } |
| 159 | if (uart->rts_pin >= 0) { |
Michael Hennerich | c58c214 | 2007-10-04 00:35:05 +0800 | [diff] [blame] | 160 | gpio_request(uart->rts_pin, DRIVER_NAME); |
Michael Hennerich | acbcd26 | 2008-01-22 18:36:20 +0800 | [diff] [blame] | 161 | gpio_direction_input(uart->rts_pin, 0); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 162 | } |
| 163 | #endif |
| 164 | } |