blob: e632125cb772db3ebb69baeb153a569bf33f6628 [file] [log] [blame]
Stefano Brivio61bca6e2007-11-06 22:49:05 +01001/*
2
3 Broadcom B43 wireless driver
4
5 PHY workarounds.
6
Stefano Brivio1f21ad22007-11-06 22:49:20 +01007 Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it>
Stefano Brivio61bca6e2007-11-06 22:49:05 +01008 Copyright (c) 2005-2007 Michael Buesch <mbuesch@freenet.de>
Stefano Brivio61bca6e2007-11-06 22:49:05 +01009
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2 of the License, or
13 (at your option) any later version.
14
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with this program; see the file COPYING. If not, write to
22 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
23 Boston, MA 02110-1301, USA.
24
25*/
26
27#include "b43.h"
28#include "main.h"
29#include "tables.h"
30#include "phy.h"
31#include "wa.h"
32
33static void b43_wa_papd(struct b43_wldev *dev)
34{
35 u16 backup;
36
37 backup = b43_ofdmtab_read16(dev, B43_OFDMTAB_PWRDYN2, 0);
38 b43_ofdmtab_write16(dev, B43_OFDMTAB_PWRDYN2, 0, 7);
39 b43_ofdmtab_write16(dev, B43_OFDMTAB_UNKNOWN_APHY, 0, 0);
40 b43_dummy_transmission(dev);
41 b43_ofdmtab_write16(dev, B43_OFDMTAB_PWRDYN2, 0, backup);
42}
43
44static void b43_wa_auxclipthr(struct b43_wldev *dev)
45{
46 b43_phy_write(dev, B43_PHY_OFDM(0x8E), 0x3800);
47}
48
49static void b43_wa_afcdac(struct b43_wldev *dev)
50{
51 b43_phy_write(dev, 0x0035, 0x03FF);
52 b43_phy_write(dev, 0x0036, 0x0400);
53}
54
55static void b43_wa_txdc_offset(struct b43_wldev *dev)
56{
57 b43_ofdmtab_write16(dev, B43_OFDMTAB_DC, 0, 0x0051);
58}
59
60void b43_wa_initgains(struct b43_wldev *dev)
61{
62 struct b43_phy *phy = &dev->phy;
63
64 b43_phy_write(dev, B43_PHY_LNAHPFCTL, 0x1FF9);
65 b43_phy_write(dev, B43_PHY_LPFGAINCTL,
66 b43_phy_read(dev, B43_PHY_LPFGAINCTL) & 0xFF0F);
67 if (phy->rev <= 2)
68 b43_ofdmtab_write16(dev, B43_OFDMTAB_LPFGAIN, 0, 0x1FBF);
69 b43_radio_write16(dev, 0x0002, 0x1FBF);
70
71 b43_phy_write(dev, 0x0024, 0x4680);
72 b43_phy_write(dev, 0x0020, 0x0003);
73 b43_phy_write(dev, 0x001D, 0x0F40);
74 b43_phy_write(dev, 0x001F, 0x1C00);
75 if (phy->rev <= 3)
76 b43_phy_write(dev, 0x002A,
77 (b43_phy_read(dev, 0x002A) & 0x00FF) | 0x0400);
78 else if (phy->rev == 5) {
79 b43_phy_write(dev, 0x002A,
80 (b43_phy_read(dev, 0x002A) & 0x00FF) | 0x1A00);
81 b43_phy_write(dev, 0x00CC, 0x2121);
82 }
83 if (phy->rev >= 3)
84 b43_phy_write(dev, 0x00BA, 0x3ED5);
85}
86
87static void b43_wa_divider(struct b43_wldev *dev)
88{
89 b43_phy_write(dev, 0x002B, b43_phy_read(dev, 0x002B) & ~0x0100);
90 b43_phy_write(dev, 0x008E, 0x58C1);
91}
92
93static void b43_wa_gt(struct b43_wldev *dev) /* Gain table. */
94{
95 if (dev->phy.rev <= 2) {
96 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN2, 0, 15);
97 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN2, 1, 31);
98 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN2, 2, 42);
99 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN2, 3, 48);
100 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN2, 4, 58);
101 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 0, 19);
102 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 1, 19);
103 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 2, 19);
104 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 3, 19);
105 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 4, 21);
106 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 5, 21);
107 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 6, 25);
108 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN1, 0, 3);
109 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN1, 1, 3);
110 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN1, 2, 7);
111 } else {
112 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 0, 19);
113 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 1, 19);
114 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 2, 19);
115 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 3, 19);
116 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 4, 21);
117 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 5, 21);
118 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 6, 25);
119 }
120}
121
122static void b43_wa_rssi_lt(struct b43_wldev *dev) /* RSSI lookup table */
123{
124 int i;
125
Michael Buesch38d1b4c2007-12-12 22:05:18 +0100126 if (0 /* FIXME: For APHY.rev=2 this might be needed */) {
127 for (i = 0; i < 8; i++)
128 b43_ofdmtab_write16(dev, B43_OFDMTAB_RSSI, i, i + 8);
129 for (i = 8; i < 16; i++)
130 b43_ofdmtab_write16(dev, B43_OFDMTAB_RSSI, i, i - 8);
131 } else {
132 for (i = 0; i < 64; i++)
133 b43_ofdmtab_write16(dev, B43_OFDMTAB_RSSI, i, i);
134 }
Stefano Brivio61bca6e2007-11-06 22:49:05 +0100135}
136
137static void b43_wa_analog(struct b43_wldev *dev)
138{
139 struct b43_phy *phy = &dev->phy;
Michael Buesch38d1b4c2007-12-12 22:05:18 +0100140 u16 ofdmrev;
Stefano Brivio61bca6e2007-11-06 22:49:05 +0100141
Michael Buesch38d1b4c2007-12-12 22:05:18 +0100142 ofdmrev = b43_phy_read(dev, B43_PHY_VERSION_OFDM) & B43_PHYVER_VERSION;
143 if (ofdmrev > 2) {
Stefano Brivio61bca6e2007-11-06 22:49:05 +0100144 if (phy->type == B43_PHYTYPE_A)
145 b43_phy_write(dev, B43_PHY_PWRDOWN, 0x1808);
146 else
147 b43_phy_write(dev, B43_PHY_PWRDOWN, 0x1000);
148 } else {
149 b43_ofdmtab_write16(dev, B43_OFDMTAB_DAC, 3, 0x1044);
150 b43_ofdmtab_write16(dev, B43_OFDMTAB_DAC, 4, 0x7201);
151 b43_ofdmtab_write16(dev, B43_OFDMTAB_DAC, 6, 0x0040);
152 }
153}
154
155static void b43_wa_dac(struct b43_wldev *dev)
156{
157 if (dev->phy.analog == 1)
158 b43_ofdmtab_write16(dev, B43_OFDMTAB_DAC, 1,
159 (b43_ofdmtab_read16(dev, B43_OFDMTAB_DAC, 1) & ~0x0034) | 0x0008);
160 else
161 b43_ofdmtab_write16(dev, B43_OFDMTAB_DAC, 1,
162 (b43_ofdmtab_read16(dev, B43_OFDMTAB_DAC, 1) & ~0x0078) | 0x0010);
163}
164
165static void b43_wa_fft(struct b43_wldev *dev) /* Fine frequency table */
166{
167 int i;
168
169 if (dev->phy.type == B43_PHYTYPE_A)
170 for (i = 0; i < B43_TAB_FINEFREQA_SIZE; i++)
171 b43_ofdmtab_write16(dev, B43_OFDMTAB_DACRFPABB, i, b43_tab_finefreqa[i]);
172 else
173 for (i = 0; i < B43_TAB_FINEFREQG_SIZE; i++)
174 b43_ofdmtab_write16(dev, B43_OFDMTAB_DACRFPABB, i, b43_tab_finefreqg[i]);
175}
176
177static void b43_wa_nft(struct b43_wldev *dev) /* Noise figure table */
178{
179 struct b43_phy *phy = &dev->phy;
180 int i;
181
182 if (phy->type == B43_PHYTYPE_A) {
183 if (phy->rev == 2)
184 for (i = 0; i < B43_TAB_NOISEA2_SIZE; i++)
185 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, i, b43_tab_noisea2[i]);
186 else
187 for (i = 0; i < B43_TAB_NOISEA3_SIZE; i++)
188 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, i, b43_tab_noisea3[i]);
189 } else {
190 if (phy->rev == 1)
191 for (i = 0; i < B43_TAB_NOISEG1_SIZE; i++)
192 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, i, b43_tab_noiseg1[i]);
193 else
194 for (i = 0; i < B43_TAB_NOISEG2_SIZE; i++)
195 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, i, b43_tab_noiseg2[i]);
196 }
197}
198
199static void b43_wa_rt(struct b43_wldev *dev) /* Rotor table */
200{
201 int i;
202
203 for (i = 0; i < B43_TAB_ROTOR_SIZE; i++)
204 b43_ofdmtab_write32(dev, B43_OFDMTAB_ROTOR, i, b43_tab_rotor[i]);
205}
206
207static void b43_wa_nst(struct b43_wldev *dev) /* Noise scale table */
208{
209 struct b43_phy *phy = &dev->phy;
210 int i;
211
212 if (phy->type == B43_PHYTYPE_A) {
213 if (phy->rev <= 1)
214 for (i = 0; i < B43_TAB_NOISESCALE_SIZE; i++)
215 b43_ofdmtab_write16(dev, B43_OFDMTAB_NOISESCALE,
216 i, 0);
217 else if (phy->rev == 2)
218 for (i = 0; i < B43_TAB_NOISESCALE_SIZE; i++)
219 b43_ofdmtab_write16(dev, B43_OFDMTAB_NOISESCALE,
220 i, b43_tab_noisescalea2[i]);
221 else if (phy->rev == 3)
222 for (i = 0; i < B43_TAB_NOISESCALE_SIZE; i++)
223 b43_ofdmtab_write16(dev, B43_OFDMTAB_NOISESCALE,
224 i, b43_tab_noisescalea3[i]);
225 else
226 for (i = 0; i < B43_TAB_NOISESCALE_SIZE; i++)
227 b43_ofdmtab_write16(dev, B43_OFDMTAB_NOISESCALE,
228 i, b43_tab_noisescaleg3[i]);
229 } else {
230 if (phy->rev >= 6) {
231 if (b43_phy_read(dev, B43_PHY_ENCORE) & B43_PHY_ENCORE_EN)
232 for (i = 0; i < B43_TAB_NOISESCALE_SIZE; i++)
233 b43_ofdmtab_write16(dev, B43_OFDMTAB_NOISESCALE,
234 i, b43_tab_noisescaleg3[i]);
235 else
236 for (i = 0; i < B43_TAB_NOISESCALE_SIZE; i++)
237 b43_ofdmtab_write16(dev, B43_OFDMTAB_NOISESCALE,
238 i, b43_tab_noisescaleg2[i]);
239 } else {
240 for (i = 0; i < B43_TAB_NOISESCALE_SIZE; i++)
241 b43_ofdmtab_write16(dev, B43_OFDMTAB_NOISESCALE,
242 i, b43_tab_noisescaleg1[i]);
243 }
244 }
245}
246
247static void b43_wa_art(struct b43_wldev *dev) /* ADV retard table */
248{
249 int i;
250
251 for (i = 0; i < B43_TAB_RETARD_SIZE; i++)
252 b43_ofdmtab_write32(dev, B43_OFDMTAB_ADVRETARD,
253 i, b43_tab_retard[i]);
254}
255
256static void b43_wa_txlna_gain(struct b43_wldev *dev)
257{
258 b43_ofdmtab_write16(dev, B43_OFDMTAB_DC, 13, 0x0000);
259}
260
261static void b43_wa_crs_reset(struct b43_wldev *dev)
262{
263 b43_phy_write(dev, 0x002C, 0x0064);
264}
265
266static void b43_wa_2060txlna_gain(struct b43_wldev *dev)
267{
268 b43_hf_write(dev, b43_hf_read(dev) |
269 B43_HF_2060W);
270}
271
272static void b43_wa_lms(struct b43_wldev *dev)
273{
274 b43_phy_write(dev, 0x0055,
275 (b43_phy_read(dev, 0x0055) & 0xFFC0) | 0x0004);
276}
277
278static void b43_wa_mixedsignal(struct b43_wldev *dev)
279{
280 b43_ofdmtab_write16(dev, B43_OFDMTAB_DAC, 1, 3);
281}
282
283static void b43_wa_msst(struct b43_wldev *dev) /* Min sigma square table */
284{
285 struct b43_phy *phy = &dev->phy;
286 int i;
287 const u16 *tab;
288
289 if (phy->type == B43_PHYTYPE_A) {
290 tab = b43_tab_sigmasqr1;
291 } else if (phy->type == B43_PHYTYPE_G) {
292 tab = b43_tab_sigmasqr2;
293 } else {
294 B43_WARN_ON(1);
295 return;
296 }
297
298 for (i = 0; i < B43_TAB_SIGMASQR_SIZE; i++) {
299 b43_ofdmtab_write16(dev, B43_OFDMTAB_MINSIGSQ,
300 i, tab[i]);
301 }
302}
303
304static void b43_wa_iqadc(struct b43_wldev *dev)
305{
306 if (dev->phy.analog == 4)
307 b43_ofdmtab_write16(dev, B43_OFDMTAB_DAC, 0,
308 b43_ofdmtab_read16(dev, B43_OFDMTAB_DAC, 0) & ~0xF000);
309}
310
311static void b43_wa_crs_ed(struct b43_wldev *dev)
312{
313 struct b43_phy *phy = &dev->phy;
314
315 if (phy->rev == 1) {
Michael Buesch38d1b4c2007-12-12 22:05:18 +0100316 b43_phy_write(dev, B43_PHY_CRSTHRES1_R1, 0x4F19);
Stefano Brivio61bca6e2007-11-06 22:49:05 +0100317 } else if (phy->rev == 2) {
Michael Buesch38d1b4c2007-12-12 22:05:18 +0100318 b43_phy_write(dev, B43_PHY_CRSTHRES1, 0x1861);
319 b43_phy_write(dev, B43_PHY_CRSTHRES2, 0x0271);
Stefano Brivio61bca6e2007-11-06 22:49:05 +0100320 b43_phy_write(dev, B43_PHY_ANTDWELL,
321 b43_phy_read(dev, B43_PHY_ANTDWELL)
322 | 0x0800);
323 } else {
Michael Buesch38d1b4c2007-12-12 22:05:18 +0100324 b43_phy_write(dev, B43_PHY_CRSTHRES1, 0x0098);
325 b43_phy_write(dev, B43_PHY_CRSTHRES2, 0x0070);
Stefano Brivio61bca6e2007-11-06 22:49:05 +0100326 b43_phy_write(dev, B43_PHY_OFDM(0xC9), 0x0080);
327 b43_phy_write(dev, B43_PHY_ANTDWELL,
328 b43_phy_read(dev, B43_PHY_ANTDWELL)
329 | 0x0800);
330 }
331}
332
333static void b43_wa_crs_thr(struct b43_wldev *dev)
334{
335 b43_phy_write(dev, B43_PHY_CRS0,
336 (b43_phy_read(dev, B43_PHY_CRS0) & ~0x03C0) | 0xD000);
337}
338
339static void b43_wa_crs_blank(struct b43_wldev *dev)
340{
341 b43_phy_write(dev, B43_PHY_OFDM(0x2C), 0x005A);
342}
343
344static void b43_wa_cck_shiftbits(struct b43_wldev *dev)
345{
346 b43_phy_write(dev, B43_PHY_CCKSHIFTBITS, 0x0026);
347}
348
349static void b43_wa_wrssi_offset(struct b43_wldev *dev)
350{
351 int i;
352
353 if (dev->phy.rev == 1) {
354 for (i = 0; i < 16; i++) {
355 b43_ofdmtab_write16(dev, B43_OFDMTAB_WRSSI_R1,
356 i, 0x0020);
357 }
358 } else {
359 for (i = 0; i < 32; i++) {
360 b43_ofdmtab_write16(dev, B43_OFDMTAB_WRSSI,
361 i, 0x0820);
362 }
363 }
364}
365
366static void b43_wa_txpuoff_rxpuon(struct b43_wldev *dev)
367{
368 b43_ofdmtab_write16(dev, B43_OFDMTAB_UNKNOWN_0F, 2, 15);
369 b43_ofdmtab_write16(dev, B43_OFDMTAB_UNKNOWN_0F, 3, 20);
370}
371
372static void b43_wa_altagc(struct b43_wldev *dev)
373{
374 struct b43_phy *phy = &dev->phy;
375
376 if (phy->rev == 1) {
377 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1_R1, 0, 254);
378 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1_R1, 1, 13);
379 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1_R1, 2, 19);
380 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1_R1, 3, 25);
381 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, 0, 0x2710);
382 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, 1, 0x9B83);
383 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, 2, 0x9B83);
384 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, 3, 0x0F8D);
385 b43_phy_write(dev, B43_PHY_LMS, 4);
386 } else {
387 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0, 254);
388 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 1, 13);
389 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 2, 19);
390 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 3, 25);
391 }
392
393 b43_phy_write(dev, B43_PHY_CCKSHIFTBITS_WA,
394 (b43_phy_read(dev, B43_PHY_CCKSHIFTBITS_WA) & ~0xFF00) | 0x5700);
395 b43_phy_write(dev, B43_PHY_OFDM(0x1A),
396 (b43_phy_read(dev, B43_PHY_OFDM(0x1A)) & ~0x007F) | 0x000F);
397 b43_phy_write(dev, B43_PHY_OFDM(0x1A),
398 (b43_phy_read(dev, B43_PHY_OFDM(0x1A)) & ~0x3F80) | 0x2B80);
399 b43_phy_write(dev, B43_PHY_ANTWRSETT,
400 (b43_phy_read(dev, B43_PHY_ANTWRSETT) & 0xF0FF) | 0x0300);
401 b43_radio_write16(dev, 0x7A,
402 b43_radio_read16(dev, 0x7A) | 0x0008);
403 b43_phy_write(dev, B43_PHY_N1P1GAIN,
404 (b43_phy_read(dev, B43_PHY_N1P1GAIN) & ~0x000F) | 0x0008);
405 b43_phy_write(dev, B43_PHY_P1P2GAIN,
406 (b43_phy_read(dev, B43_PHY_P1P2GAIN) & ~0x0F00) | 0x0600);
407 b43_phy_write(dev, B43_PHY_N1N2GAIN,
408 (b43_phy_read(dev, B43_PHY_N1N2GAIN) & ~0x0F00) | 0x0700);
409 b43_phy_write(dev, B43_PHY_N1P1GAIN,
410 (b43_phy_read(dev, B43_PHY_N1P1GAIN) & ~0x0F00) | 0x0100);
411 if (phy->rev == 1) {
412 b43_phy_write(dev, B43_PHY_N1N2GAIN,
413 (b43_phy_read(dev, B43_PHY_N1N2GAIN)
414 & ~0x000F) | 0x0007);
415 }
416 b43_phy_write(dev, B43_PHY_OFDM(0x88),
417 (b43_phy_read(dev, B43_PHY_OFDM(0x88)) & ~0x00FF) | 0x001C);
418 b43_phy_write(dev, B43_PHY_OFDM(0x88),
419 (b43_phy_read(dev, B43_PHY_OFDM(0x88)) & ~0x3F00) | 0x0200);
420 b43_phy_write(dev, B43_PHY_OFDM(0x96),
421 (b43_phy_read(dev, B43_PHY_OFDM(0x96)) & ~0x00FF) | 0x001C);
422 b43_phy_write(dev, B43_PHY_OFDM(0x89),
423 (b43_phy_read(dev, B43_PHY_OFDM(0x89)) & ~0x00FF) | 0x0020);
424 b43_phy_write(dev, B43_PHY_OFDM(0x89),
425 (b43_phy_read(dev, B43_PHY_OFDM(0x89)) & ~0x3F00) | 0x0200);
426 b43_phy_write(dev, B43_PHY_OFDM(0x82),
427 (b43_phy_read(dev, B43_PHY_OFDM(0x82)) & ~0x00FF) | 0x002E);
428 b43_phy_write(dev, B43_PHY_OFDM(0x96),
429 (b43_phy_read(dev, B43_PHY_OFDM(0x96)) & ~0xFF00) | 0x1A00);
430 b43_phy_write(dev, B43_PHY_OFDM(0x81),
431 (b43_phy_read(dev, B43_PHY_OFDM(0x81)) & ~0x00FF) | 0x0028);
432 b43_phy_write(dev, B43_PHY_OFDM(0x81),
433 (b43_phy_read(dev, B43_PHY_OFDM(0x81)) & ~0xFF00) | 0x2C00);
434 if (phy->rev == 1) {
435 b43_phy_write(dev, B43_PHY_PEAK_COUNT, 0x092B);
436 b43_phy_write(dev, B43_PHY_OFDM(0x1B),
437 (b43_phy_read(dev, B43_PHY_OFDM(0x1B)) & ~0x001E) | 0x0002);
438 } else {
439 b43_phy_write(dev, B43_PHY_OFDM(0x1B),
440 b43_phy_read(dev, B43_PHY_OFDM(0x1B)) & ~0x001E);
441 b43_phy_write(dev, B43_PHY_OFDM(0x1F), 0x287A);
442 b43_phy_write(dev, B43_PHY_LPFGAINCTL,
443 (b43_phy_read(dev, B43_PHY_LPFGAINCTL) & ~0x000F) | 0x0004);
444 if (phy->rev >= 6) {
445 b43_phy_write(dev, B43_PHY_OFDM(0x22), 0x287A);
446 b43_phy_write(dev, B43_PHY_LPFGAINCTL,
447 (b43_phy_read(dev, B43_PHY_LPFGAINCTL) & ~0xF000) | 0x3000);
448 }
449 }
450 b43_phy_write(dev, B43_PHY_DIVSRCHIDX,
Michael Buesch38d1b4c2007-12-12 22:05:18 +0100451 (b43_phy_read(dev, B43_PHY_DIVSRCHIDX) & 0x8080) | 0x7874);
Stefano Brivio61bca6e2007-11-06 22:49:05 +0100452 b43_phy_write(dev, B43_PHY_OFDM(0x8E), 0x1C00);
453 if (phy->rev == 1) {
454 b43_phy_write(dev, B43_PHY_DIVP1P2GAIN,
455 (b43_phy_read(dev, B43_PHY_DIVP1P2GAIN) & ~0x0F00) | 0x0600);
456 b43_phy_write(dev, B43_PHY_OFDM(0x8B), 0x005E);
457 b43_phy_write(dev, B43_PHY_ANTWRSETT,
458 (b43_phy_read(dev, B43_PHY_ANTWRSETT) & ~0x00FF) | 0x001E);
459 b43_phy_write(dev, B43_PHY_OFDM(0x8D), 0x0002);
460 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3_R1, 0, 0);
461 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3_R1, 1, 7);
462 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3_R1, 2, 16);
463 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3_R1, 3, 28);
464 } else {
465 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3, 0, 0);
466 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3, 1, 7);
467 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3, 2, 16);
468 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3, 3, 28);
469 }
470 if (phy->rev >= 6) {
471 b43_phy_write(dev, B43_PHY_OFDM(0x26),
472 b43_phy_read(dev, B43_PHY_OFDM(0x26)) & ~0x0003);
473 b43_phy_write(dev, B43_PHY_OFDM(0x26),
474 b43_phy_read(dev, B43_PHY_OFDM(0x26)) & ~0x1000);
475 }
Michael Buesch38d1b4c2007-12-12 22:05:18 +0100476 b43_phy_read(dev, B43_PHY_VERSION_OFDM); /* Dummy read */
Stefano Brivio61bca6e2007-11-06 22:49:05 +0100477}
478
479static void b43_wa_tr_ltov(struct b43_wldev *dev) /* TR Lookup Table Original Values */
480{
481 b43_gtab_write(dev, B43_GTAB_ORIGTR, 0, 0xC480);
482}
483
484static void b43_wa_cpll_nonpilot(struct b43_wldev *dev)
485{
486 b43_ofdmtab_write16(dev, B43_OFDMTAB_UNKNOWN_11, 0, 0);
487 b43_ofdmtab_write16(dev, B43_OFDMTAB_UNKNOWN_11, 1, 0);
488}
489
490static void b43_wa_rssi_adc(struct b43_wldev *dev)
491{
492 if (dev->phy.analog == 4)
493 b43_phy_write(dev, 0x00DC, 0x7454);
494}
495
496static void b43_wa_boards_a(struct b43_wldev *dev)
497{
498 struct ssb_bus *bus = dev->dev->bus;
499
500 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM &&
501 bus->boardinfo.type == SSB_BOARD_BU4306 &&
502 bus->boardinfo.rev < 0x30) {
503 b43_phy_write(dev, 0x0010, 0xE000);
504 b43_phy_write(dev, 0x0013, 0x0140);
505 b43_phy_write(dev, 0x0014, 0x0280);
506 } else {
507 if (bus->boardinfo.type == SSB_BOARD_MP4318 &&
508 bus->boardinfo.rev < 0x20) {
509 b43_phy_write(dev, 0x0013, 0x0210);
510 b43_phy_write(dev, 0x0014, 0x0840);
511 } else {
512 b43_phy_write(dev, 0x0013, 0x0140);
513 b43_phy_write(dev, 0x0014, 0x0280);
514 }
515 if (dev->phy.rev <= 4)
516 b43_phy_write(dev, 0x0010, 0xE000);
517 else
518 b43_phy_write(dev, 0x0010, 0x2000);
519 b43_ofdmtab_write16(dev, B43_OFDMTAB_DC, 1, 0x0039);
520 b43_ofdmtab_write16(dev, B43_OFDMTAB_UNKNOWN_APHY, 7, 0x0040);
521 }
522}
523
524static void b43_wa_boards_g(struct b43_wldev *dev)
525{
526 struct ssb_bus *bus = dev->dev->bus;
527 struct b43_phy *phy = &dev->phy;
528
529 if (bus->boardinfo.vendor != SSB_BOARDVENDOR_BCM ||
530 bus->boardinfo.type != SSB_BOARD_BU4306 ||
531 bus->boardinfo.rev != 0x17) {
532 if (phy->rev < 2) {
533 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX_R1, 1, 0x0002);
534 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX_R1, 2, 0x0001);
535 } else {
536 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 1, 0x0002);
537 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 2, 0x0001);
Larry Finger95de2842007-11-09 16:57:18 -0600538 if ((bus->sprom.boardflags_lo & B43_BFL_EXTLNA) &&
Stefano Brivio61bca6e2007-11-06 22:49:05 +0100539 (phy->rev >= 7)) {
540 b43_phy_write(dev, B43_PHY_EXTG(0x11),
541 b43_phy_read(dev, B43_PHY_EXTG(0x11)) & 0xF7FF);
542 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0020, 0x0001);
543 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0021, 0x0001);
544 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0022, 0x0001);
545 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0023, 0x0000);
546 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0000, 0x0000);
547 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0003, 0x0002);
548 }
549 }
550 }
Larry Finger95de2842007-11-09 16:57:18 -0600551 if (bus->sprom.boardflags_lo & B43_BFL_FEM) {
Stefano Brivio61bca6e2007-11-06 22:49:05 +0100552 b43_phy_write(dev, B43_PHY_GTABCTL, 0x3120);
553 b43_phy_write(dev, B43_PHY_GTABDATA, 0xC480);
554 }
555}
556
557void b43_wa_all(struct b43_wldev *dev)
558{
559 struct b43_phy *phy = &dev->phy;
560
561 if (phy->type == B43_PHYTYPE_A) {
562 switch (phy->rev) {
563 case 2:
564 b43_wa_papd(dev);
565 b43_wa_auxclipthr(dev);
566 b43_wa_afcdac(dev);
567 b43_wa_txdc_offset(dev);
568 b43_wa_initgains(dev);
569 b43_wa_divider(dev);
570 b43_wa_gt(dev);
571 b43_wa_rssi_lt(dev);
572 b43_wa_analog(dev);
573 b43_wa_dac(dev);
574 b43_wa_fft(dev);
575 b43_wa_nft(dev);
576 b43_wa_rt(dev);
577 b43_wa_nst(dev);
578 b43_wa_art(dev);
579 b43_wa_txlna_gain(dev);
580 b43_wa_crs_reset(dev);
581 b43_wa_2060txlna_gain(dev);
582 b43_wa_lms(dev);
583 break;
584 case 3:
585 b43_wa_papd(dev);
586 b43_wa_mixedsignal(dev);
587 b43_wa_rssi_lt(dev);
588 b43_wa_txdc_offset(dev);
589 b43_wa_initgains(dev);
590 b43_wa_dac(dev);
591 b43_wa_nft(dev);
592 b43_wa_nst(dev);
593 b43_wa_msst(dev);
594 b43_wa_analog(dev);
595 b43_wa_gt(dev);
596 b43_wa_txpuoff_rxpuon(dev);
597 b43_wa_txlna_gain(dev);
598 break;
599 case 5:
600 b43_wa_iqadc(dev);
601 case 6:
602 b43_wa_papd(dev);
603 b43_wa_rssi_lt(dev);
604 b43_wa_txdc_offset(dev);
605 b43_wa_initgains(dev);
606 b43_wa_dac(dev);
607 b43_wa_nft(dev);
608 b43_wa_nst(dev);
609 b43_wa_msst(dev);
610 b43_wa_analog(dev);
611 b43_wa_gt(dev);
612 b43_wa_txpuoff_rxpuon(dev);
613 b43_wa_txlna_gain(dev);
614 break;
615 case 7:
616 b43_wa_iqadc(dev);
617 b43_wa_papd(dev);
618 b43_wa_rssi_lt(dev);
619 b43_wa_txdc_offset(dev);
620 b43_wa_initgains(dev);
621 b43_wa_dac(dev);
622 b43_wa_nft(dev);
623 b43_wa_nst(dev);
624 b43_wa_msst(dev);
625 b43_wa_analog(dev);
626 b43_wa_gt(dev);
627 b43_wa_txpuoff_rxpuon(dev);
628 b43_wa_txlna_gain(dev);
629 b43_wa_rssi_adc(dev);
630 default:
631 B43_WARN_ON(1);
632 }
633 b43_wa_boards_a(dev);
634 } else if (phy->type == B43_PHYTYPE_G) {
635 switch (phy->rev) {
636 case 1://XXX review rev1
637 b43_wa_crs_ed(dev);
638 b43_wa_crs_thr(dev);
639 b43_wa_crs_blank(dev);
640 b43_wa_cck_shiftbits(dev);
641 b43_wa_fft(dev);
642 b43_wa_nft(dev);
643 b43_wa_rt(dev);
644 b43_wa_nst(dev);
645 b43_wa_art(dev);
646 b43_wa_wrssi_offset(dev);
647 b43_wa_altagc(dev);
648 break;
649 case 2:
650 case 6:
651 case 7:
652 case 8:
Larry Finger013978b2007-11-26 10:29:47 -0600653 case 9:
Stefano Brivio61bca6e2007-11-06 22:49:05 +0100654 b43_wa_tr_ltov(dev);
655 b43_wa_crs_ed(dev);
656 b43_wa_rssi_lt(dev);
657 b43_wa_nft(dev);
658 b43_wa_nst(dev);
659 b43_wa_msst(dev);
660 b43_wa_wrssi_offset(dev);
661 b43_wa_altagc(dev);
662 b43_wa_analog(dev);
663 b43_wa_txpuoff_rxpuon(dev);
664 break;
665 default:
666 B43_WARN_ON(1);
667 }
668 b43_wa_boards_g(dev);
669 } else { /* No N PHY support so far */
670 B43_WARN_ON(1);
671 }
672
673 b43_wa_cpll_nonpilot(dev);
674}