Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * forcedeth: Ethernet driver for NVIDIA nForce media access controllers. |
| 3 | * |
| 4 | * Note: This driver is a cleanroom reimplementation based on reverse |
| 5 | * engineered documentation written by Carl-Daniel Hailfinger |
| 6 | * and Andrew de Quincey. It's neither supported nor endorsed |
| 7 | * by NVIDIA Corp. Use at your own risk. |
| 8 | * |
| 9 | * NVIDIA, nForce and other NVIDIA marks are trademarks or registered |
| 10 | * trademarks of NVIDIA Corporation in the United States and other |
| 11 | * countries. |
| 12 | * |
| 13 | * Copyright (C) 2003,4 Manfred Spraul |
| 14 | * Copyright (C) 2004 Andrew de Quincey (wol support) |
| 15 | * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane |
| 16 | * IRQ rate fixes, bigendian fixes, cleanups, verification) |
| 17 | * Copyright (c) 2004 NVIDIA Corporation |
| 18 | * |
| 19 | * This program is free software; you can redistribute it and/or modify |
| 20 | * it under the terms of the GNU General Public License as published by |
| 21 | * the Free Software Foundation; either version 2 of the License, or |
| 22 | * (at your option) any later version. |
| 23 | * |
| 24 | * This program is distributed in the hope that it will be useful, |
| 25 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 26 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 27 | * GNU General Public License for more details. |
| 28 | * |
| 29 | * You should have received a copy of the GNU General Public License |
| 30 | * along with this program; if not, write to the Free Software |
| 31 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 32 | * |
| 33 | * Changelog: |
| 34 | * 0.01: 05 Oct 2003: First release that compiles without warnings. |
| 35 | * 0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs. |
| 36 | * Check all PCI BARs for the register window. |
| 37 | * udelay added to mii_rw. |
| 38 | * 0.03: 06 Oct 2003: Initialize dev->irq. |
| 39 | * 0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks. |
| 40 | * 0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout. |
| 41 | * 0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated, |
| 42 | * irq mask updated |
| 43 | * 0.07: 14 Oct 2003: Further irq mask updates. |
| 44 | * 0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill |
| 45 | * added into irq handler, NULL check for drain_ring. |
| 46 | * 0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the |
| 47 | * requested interrupt sources. |
| 48 | * 0.10: 20 Oct 2003: First cleanup for release. |
| 49 | * 0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased. |
| 50 | * MAC Address init fix, set_multicast cleanup. |
| 51 | * 0.12: 23 Oct 2003: Cleanups for release. |
| 52 | * 0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10. |
| 53 | * Set link speed correctly. start rx before starting |
| 54 | * tx (nv_start_rx sets the link speed). |
| 55 | * 0.14: 25 Oct 2003: Nic dependant irq mask. |
| 56 | * 0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during |
| 57 | * open. |
| 58 | * 0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size |
| 59 | * increased to 1628 bytes. |
| 60 | * 0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from |
| 61 | * the tx length. |
| 62 | * 0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats |
| 63 | * 0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac |
| 64 | * addresses, really stop rx if already running |
| 65 | * in nv_start_rx, clean up a bit. |
| 66 | * 0.20: 07 Dec 2003: alloc fixes |
| 67 | * 0.21: 12 Jan 2004: additional alloc fix, nic polling fix. |
| 68 | * 0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup |
| 69 | * on close. |
| 70 | * 0.23: 26 Jan 2004: various small cleanups |
| 71 | * 0.24: 27 Feb 2004: make driver even less anonymous in backtraces |
| 72 | * 0.25: 09 Mar 2004: wol support |
| 73 | * 0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes |
| 74 | * 0.27: 19 Jun 2004: Gigabit support, new descriptor rings, |
| 75 | * added CK804/MCP04 device IDs, code fixes |
| 76 | * for registers, link status and other minor fixes. |
| 77 | * 0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe |
| 78 | * 0.29: 31 Aug 2004: Add backup timer for link change notification. |
| 79 | * 0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset |
| 80 | * into nv_close, otherwise reenabling for wol can |
| 81 | * cause DMA to kfree'd memory. |
| 82 | * 0.31: 14 Nov 2004: ethtool support for getting/setting link |
| 83 | * capabilities. |
| 84 | * |
| 85 | * Known bugs: |
| 86 | * We suspect that on some hardware no TX done interrupts are generated. |
| 87 | * This means recovery from netif_stop_queue only happens if the hw timer |
| 88 | * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT) |
| 89 | * and the timer is active in the IRQMask, or if a rx packet arrives by chance. |
| 90 | * If your hardware reliably generates tx done interrupts, then you can remove |
| 91 | * DEV_NEED_TIMERIRQ from the driver_data flags. |
| 92 | * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few |
| 93 | * superfluous timer interrupts from the nic. |
| 94 | */ |
| 95 | #define FORCEDETH_VERSION "0.31" |
| 96 | #define DRV_NAME "forcedeth" |
| 97 | |
| 98 | #include <linux/module.h> |
| 99 | #include <linux/types.h> |
| 100 | #include <linux/pci.h> |
| 101 | #include <linux/interrupt.h> |
| 102 | #include <linux/netdevice.h> |
| 103 | #include <linux/etherdevice.h> |
| 104 | #include <linux/delay.h> |
| 105 | #include <linux/spinlock.h> |
| 106 | #include <linux/ethtool.h> |
| 107 | #include <linux/timer.h> |
| 108 | #include <linux/skbuff.h> |
| 109 | #include <linux/mii.h> |
| 110 | #include <linux/random.h> |
| 111 | #include <linux/init.h> |
| 112 | |
| 113 | #include <asm/irq.h> |
| 114 | #include <asm/io.h> |
| 115 | #include <asm/uaccess.h> |
| 116 | #include <asm/system.h> |
| 117 | |
| 118 | #if 0 |
| 119 | #define dprintk printk |
| 120 | #else |
| 121 | #define dprintk(x...) do { } while (0) |
| 122 | #endif |
| 123 | |
| 124 | |
| 125 | /* |
| 126 | * Hardware access: |
| 127 | */ |
| 128 | |
| 129 | #define DEV_NEED_LASTPACKET1 0x0001 /* set LASTPACKET1 in tx flags */ |
| 130 | #define DEV_IRQMASK_1 0x0002 /* use NVREG_IRQMASK_WANTED_1 for irq mask */ |
| 131 | #define DEV_IRQMASK_2 0x0004 /* use NVREG_IRQMASK_WANTED_2 for irq mask */ |
| 132 | #define DEV_NEED_TIMERIRQ 0x0008 /* set the timer irq flag in the irq mask */ |
| 133 | #define DEV_NEED_LINKTIMER 0x0010 /* poll link settings. Relies on the timer irq */ |
| 134 | |
| 135 | enum { |
| 136 | NvRegIrqStatus = 0x000, |
| 137 | #define NVREG_IRQSTAT_MIIEVENT 0x040 |
| 138 | #define NVREG_IRQSTAT_MASK 0x1ff |
| 139 | NvRegIrqMask = 0x004, |
| 140 | #define NVREG_IRQ_RX_ERROR 0x0001 |
| 141 | #define NVREG_IRQ_RX 0x0002 |
| 142 | #define NVREG_IRQ_RX_NOBUF 0x0004 |
| 143 | #define NVREG_IRQ_TX_ERR 0x0008 |
| 144 | #define NVREG_IRQ_TX2 0x0010 |
| 145 | #define NVREG_IRQ_TIMER 0x0020 |
| 146 | #define NVREG_IRQ_LINK 0x0040 |
| 147 | #define NVREG_IRQ_TX1 0x0100 |
| 148 | #define NVREG_IRQMASK_WANTED_1 0x005f |
| 149 | #define NVREG_IRQMASK_WANTED_2 0x0147 |
| 150 | #define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR|NVREG_IRQ_TX2|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_TX1)) |
| 151 | |
| 152 | NvRegUnknownSetupReg6 = 0x008, |
| 153 | #define NVREG_UNKSETUP6_VAL 3 |
| 154 | |
| 155 | /* |
| 156 | * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic |
| 157 | * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms |
| 158 | */ |
| 159 | NvRegPollingInterval = 0x00c, |
| 160 | #define NVREG_POLL_DEFAULT 970 |
| 161 | NvRegMisc1 = 0x080, |
| 162 | #define NVREG_MISC1_HD 0x02 |
| 163 | #define NVREG_MISC1_FORCE 0x3b0f3c |
| 164 | |
| 165 | NvRegTransmitterControl = 0x084, |
| 166 | #define NVREG_XMITCTL_START 0x01 |
| 167 | NvRegTransmitterStatus = 0x088, |
| 168 | #define NVREG_XMITSTAT_BUSY 0x01 |
| 169 | |
| 170 | NvRegPacketFilterFlags = 0x8c, |
| 171 | #define NVREG_PFF_ALWAYS 0x7F0008 |
| 172 | #define NVREG_PFF_PROMISC 0x80 |
| 173 | #define NVREG_PFF_MYADDR 0x20 |
| 174 | |
| 175 | NvRegOffloadConfig = 0x90, |
| 176 | #define NVREG_OFFLOAD_HOMEPHY 0x601 |
| 177 | #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE |
| 178 | NvRegReceiverControl = 0x094, |
| 179 | #define NVREG_RCVCTL_START 0x01 |
| 180 | NvRegReceiverStatus = 0x98, |
| 181 | #define NVREG_RCVSTAT_BUSY 0x01 |
| 182 | |
| 183 | NvRegRandomSeed = 0x9c, |
| 184 | #define NVREG_RNDSEED_MASK 0x00ff |
| 185 | #define NVREG_RNDSEED_FORCE 0x7f00 |
| 186 | #define NVREG_RNDSEED_FORCE2 0x2d00 |
| 187 | #define NVREG_RNDSEED_FORCE3 0x7400 |
| 188 | |
| 189 | NvRegUnknownSetupReg1 = 0xA0, |
| 190 | #define NVREG_UNKSETUP1_VAL 0x16070f |
| 191 | NvRegUnknownSetupReg2 = 0xA4, |
| 192 | #define NVREG_UNKSETUP2_VAL 0x16 |
| 193 | NvRegMacAddrA = 0xA8, |
| 194 | NvRegMacAddrB = 0xAC, |
| 195 | NvRegMulticastAddrA = 0xB0, |
| 196 | #define NVREG_MCASTADDRA_FORCE 0x01 |
| 197 | NvRegMulticastAddrB = 0xB4, |
| 198 | NvRegMulticastMaskA = 0xB8, |
| 199 | NvRegMulticastMaskB = 0xBC, |
| 200 | |
| 201 | NvRegPhyInterface = 0xC0, |
| 202 | #define PHY_RGMII 0x10000000 |
| 203 | |
| 204 | NvRegTxRingPhysAddr = 0x100, |
| 205 | NvRegRxRingPhysAddr = 0x104, |
| 206 | NvRegRingSizes = 0x108, |
| 207 | #define NVREG_RINGSZ_TXSHIFT 0 |
| 208 | #define NVREG_RINGSZ_RXSHIFT 16 |
| 209 | NvRegUnknownTransmitterReg = 0x10c, |
| 210 | NvRegLinkSpeed = 0x110, |
| 211 | #define NVREG_LINKSPEED_FORCE 0x10000 |
| 212 | #define NVREG_LINKSPEED_10 1000 |
| 213 | #define NVREG_LINKSPEED_100 100 |
| 214 | #define NVREG_LINKSPEED_1000 50 |
| 215 | #define NVREG_LINKSPEED_MASK (0xFFF) |
| 216 | NvRegUnknownSetupReg5 = 0x130, |
| 217 | #define NVREG_UNKSETUP5_BIT31 (1<<31) |
| 218 | NvRegUnknownSetupReg3 = 0x13c, |
| 219 | #define NVREG_UNKSETUP3_VAL1 0x200010 |
| 220 | NvRegTxRxControl = 0x144, |
| 221 | #define NVREG_TXRXCTL_KICK 0x0001 |
| 222 | #define NVREG_TXRXCTL_BIT1 0x0002 |
| 223 | #define NVREG_TXRXCTL_BIT2 0x0004 |
| 224 | #define NVREG_TXRXCTL_IDLE 0x0008 |
| 225 | #define NVREG_TXRXCTL_RESET 0x0010 |
| 226 | #define NVREG_TXRXCTL_RXCHECK 0x0400 |
| 227 | NvRegMIIStatus = 0x180, |
| 228 | #define NVREG_MIISTAT_ERROR 0x0001 |
| 229 | #define NVREG_MIISTAT_LINKCHANGE 0x0008 |
| 230 | #define NVREG_MIISTAT_MASK 0x000f |
| 231 | #define NVREG_MIISTAT_MASK2 0x000f |
| 232 | NvRegUnknownSetupReg4 = 0x184, |
| 233 | #define NVREG_UNKSETUP4_VAL 8 |
| 234 | |
| 235 | NvRegAdapterControl = 0x188, |
| 236 | #define NVREG_ADAPTCTL_START 0x02 |
| 237 | #define NVREG_ADAPTCTL_LINKUP 0x04 |
| 238 | #define NVREG_ADAPTCTL_PHYVALID 0x40000 |
| 239 | #define NVREG_ADAPTCTL_RUNNING 0x100000 |
| 240 | #define NVREG_ADAPTCTL_PHYSHIFT 24 |
| 241 | NvRegMIISpeed = 0x18c, |
| 242 | #define NVREG_MIISPEED_BIT8 (1<<8) |
| 243 | #define NVREG_MIIDELAY 5 |
| 244 | NvRegMIIControl = 0x190, |
| 245 | #define NVREG_MIICTL_INUSE 0x08000 |
| 246 | #define NVREG_MIICTL_WRITE 0x00400 |
| 247 | #define NVREG_MIICTL_ADDRSHIFT 5 |
| 248 | NvRegMIIData = 0x194, |
| 249 | NvRegWakeUpFlags = 0x200, |
| 250 | #define NVREG_WAKEUPFLAGS_VAL 0x7770 |
| 251 | #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24 |
| 252 | #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16 |
| 253 | #define NVREG_WAKEUPFLAGS_D3SHIFT 12 |
| 254 | #define NVREG_WAKEUPFLAGS_D2SHIFT 8 |
| 255 | #define NVREG_WAKEUPFLAGS_D1SHIFT 4 |
| 256 | #define NVREG_WAKEUPFLAGS_D0SHIFT 0 |
| 257 | #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01 |
| 258 | #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02 |
| 259 | #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04 |
| 260 | #define NVREG_WAKEUPFLAGS_ENABLE 0x1111 |
| 261 | |
| 262 | NvRegPatternCRC = 0x204, |
| 263 | NvRegPatternMask = 0x208, |
| 264 | NvRegPowerCap = 0x268, |
| 265 | #define NVREG_POWERCAP_D3SUPP (1<<30) |
| 266 | #define NVREG_POWERCAP_D2SUPP (1<<26) |
| 267 | #define NVREG_POWERCAP_D1SUPP (1<<25) |
| 268 | NvRegPowerState = 0x26c, |
| 269 | #define NVREG_POWERSTATE_POWEREDUP 0x8000 |
| 270 | #define NVREG_POWERSTATE_VALID 0x0100 |
| 271 | #define NVREG_POWERSTATE_MASK 0x0003 |
| 272 | #define NVREG_POWERSTATE_D0 0x0000 |
| 273 | #define NVREG_POWERSTATE_D1 0x0001 |
| 274 | #define NVREG_POWERSTATE_D2 0x0002 |
| 275 | #define NVREG_POWERSTATE_D3 0x0003 |
| 276 | }; |
| 277 | |
| 278 | /* Big endian: should work, but is untested */ |
| 279 | struct ring_desc { |
| 280 | u32 PacketBuffer; |
| 281 | u32 FlagLen; |
| 282 | }; |
| 283 | |
| 284 | #define FLAG_MASK_V1 0xffff0000 |
| 285 | #define FLAG_MASK_V2 0xffffc000 |
| 286 | #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1) |
| 287 | #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2) |
| 288 | |
| 289 | #define NV_TX_LASTPACKET (1<<16) |
| 290 | #define NV_TX_RETRYERROR (1<<19) |
| 291 | #define NV_TX_LASTPACKET1 (1<<24) |
| 292 | #define NV_TX_DEFERRED (1<<26) |
| 293 | #define NV_TX_CARRIERLOST (1<<27) |
| 294 | #define NV_TX_LATECOLLISION (1<<28) |
| 295 | #define NV_TX_UNDERFLOW (1<<29) |
| 296 | #define NV_TX_ERROR (1<<30) |
| 297 | #define NV_TX_VALID (1<<31) |
| 298 | |
| 299 | #define NV_TX2_LASTPACKET (1<<29) |
| 300 | #define NV_TX2_RETRYERROR (1<<18) |
| 301 | #define NV_TX2_LASTPACKET1 (1<<23) |
| 302 | #define NV_TX2_DEFERRED (1<<25) |
| 303 | #define NV_TX2_CARRIERLOST (1<<26) |
| 304 | #define NV_TX2_LATECOLLISION (1<<27) |
| 305 | #define NV_TX2_UNDERFLOW (1<<28) |
| 306 | /* error and valid are the same for both */ |
| 307 | #define NV_TX2_ERROR (1<<30) |
| 308 | #define NV_TX2_VALID (1<<31) |
| 309 | |
| 310 | #define NV_RX_DESCRIPTORVALID (1<<16) |
| 311 | #define NV_RX_MISSEDFRAME (1<<17) |
| 312 | #define NV_RX_SUBSTRACT1 (1<<18) |
| 313 | #define NV_RX_ERROR1 (1<<23) |
| 314 | #define NV_RX_ERROR2 (1<<24) |
| 315 | #define NV_RX_ERROR3 (1<<25) |
| 316 | #define NV_RX_ERROR4 (1<<26) |
| 317 | #define NV_RX_CRCERR (1<<27) |
| 318 | #define NV_RX_OVERFLOW (1<<28) |
| 319 | #define NV_RX_FRAMINGERR (1<<29) |
| 320 | #define NV_RX_ERROR (1<<30) |
| 321 | #define NV_RX_AVAIL (1<<31) |
| 322 | |
| 323 | #define NV_RX2_CHECKSUMMASK (0x1C000000) |
| 324 | #define NV_RX2_CHECKSUMOK1 (0x10000000) |
| 325 | #define NV_RX2_CHECKSUMOK2 (0x14000000) |
| 326 | #define NV_RX2_CHECKSUMOK3 (0x18000000) |
| 327 | #define NV_RX2_DESCRIPTORVALID (1<<29) |
| 328 | #define NV_RX2_SUBSTRACT1 (1<<25) |
| 329 | #define NV_RX2_ERROR1 (1<<18) |
| 330 | #define NV_RX2_ERROR2 (1<<19) |
| 331 | #define NV_RX2_ERROR3 (1<<20) |
| 332 | #define NV_RX2_ERROR4 (1<<21) |
| 333 | #define NV_RX2_CRCERR (1<<22) |
| 334 | #define NV_RX2_OVERFLOW (1<<23) |
| 335 | #define NV_RX2_FRAMINGERR (1<<24) |
| 336 | /* error and avail are the same for both */ |
| 337 | #define NV_RX2_ERROR (1<<30) |
| 338 | #define NV_RX2_AVAIL (1<<31) |
| 339 | |
| 340 | /* Miscelaneous hardware related defines: */ |
| 341 | #define NV_PCI_REGSZ 0x270 |
| 342 | |
| 343 | /* various timeout delays: all in usec */ |
| 344 | #define NV_TXRX_RESET_DELAY 4 |
| 345 | #define NV_TXSTOP_DELAY1 10 |
| 346 | #define NV_TXSTOP_DELAY1MAX 500000 |
| 347 | #define NV_TXSTOP_DELAY2 100 |
| 348 | #define NV_RXSTOP_DELAY1 10 |
| 349 | #define NV_RXSTOP_DELAY1MAX 500000 |
| 350 | #define NV_RXSTOP_DELAY2 100 |
| 351 | #define NV_SETUP5_DELAY 5 |
| 352 | #define NV_SETUP5_DELAYMAX 50000 |
| 353 | #define NV_POWERUP_DELAY 5 |
| 354 | #define NV_POWERUP_DELAYMAX 5000 |
| 355 | #define NV_MIIBUSY_DELAY 50 |
| 356 | #define NV_MIIPHY_DELAY 10 |
| 357 | #define NV_MIIPHY_DELAYMAX 10000 |
| 358 | |
| 359 | #define NV_WAKEUPPATTERNS 5 |
| 360 | #define NV_WAKEUPMASKENTRIES 4 |
| 361 | |
| 362 | /* General driver defaults */ |
| 363 | #define NV_WATCHDOG_TIMEO (5*HZ) |
| 364 | |
| 365 | #define RX_RING 128 |
| 366 | #define TX_RING 64 |
| 367 | /* |
| 368 | * If your nic mysteriously hangs then try to reduce the limits |
| 369 | * to 1/0: It might be required to set NV_TX_LASTPACKET in the |
| 370 | * last valid ring entry. But this would be impossible to |
| 371 | * implement - probably a disassembly error. |
| 372 | */ |
| 373 | #define TX_LIMIT_STOP 63 |
| 374 | #define TX_LIMIT_START 62 |
| 375 | |
| 376 | /* rx/tx mac addr + type + vlan + align + slack*/ |
| 377 | #define RX_NIC_BUFSIZE (ETH_DATA_LEN + 64) |
| 378 | /* even more slack */ |
| 379 | #define RX_ALLOC_BUFSIZE (ETH_DATA_LEN + 128) |
| 380 | |
| 381 | #define OOM_REFILL (1+HZ/20) |
| 382 | #define POLL_WAIT (1+HZ/100) |
| 383 | #define LINK_TIMEOUT (3*HZ) |
| 384 | |
| 385 | /* |
| 386 | * desc_ver values: |
| 387 | * This field has two purposes: |
| 388 | * - Newer nics uses a different ring layout. The layout is selected by |
| 389 | * comparing np->desc_ver with DESC_VER_xy. |
| 390 | * - It contains bits that are forced on when writing to NvRegTxRxControl. |
| 391 | */ |
| 392 | #define DESC_VER_1 0x0 |
| 393 | #define DESC_VER_2 (0x02100|NVREG_TXRXCTL_RXCHECK) |
| 394 | |
| 395 | /* PHY defines */ |
| 396 | #define PHY_OUI_MARVELL 0x5043 |
| 397 | #define PHY_OUI_CICADA 0x03f1 |
| 398 | #define PHYID1_OUI_MASK 0x03ff |
| 399 | #define PHYID1_OUI_SHFT 6 |
| 400 | #define PHYID2_OUI_MASK 0xfc00 |
| 401 | #define PHYID2_OUI_SHFT 10 |
| 402 | #define PHY_INIT1 0x0f000 |
| 403 | #define PHY_INIT2 0x0e00 |
| 404 | #define PHY_INIT3 0x01000 |
| 405 | #define PHY_INIT4 0x0200 |
| 406 | #define PHY_INIT5 0x0004 |
| 407 | #define PHY_INIT6 0x02000 |
| 408 | #define PHY_GIGABIT 0x0100 |
| 409 | |
| 410 | #define PHY_TIMEOUT 0x1 |
| 411 | #define PHY_ERROR 0x2 |
| 412 | |
| 413 | #define PHY_100 0x1 |
| 414 | #define PHY_1000 0x2 |
| 415 | #define PHY_HALF 0x100 |
| 416 | |
| 417 | /* FIXME: MII defines that should be added to <linux/mii.h> */ |
| 418 | #define MII_1000BT_CR 0x09 |
| 419 | #define MII_1000BT_SR 0x0a |
| 420 | #define ADVERTISE_1000FULL 0x0200 |
| 421 | #define ADVERTISE_1000HALF 0x0100 |
| 422 | #define LPA_1000FULL 0x0800 |
| 423 | #define LPA_1000HALF 0x0400 |
| 424 | |
| 425 | |
| 426 | /* |
| 427 | * SMP locking: |
| 428 | * All hardware access under dev->priv->lock, except the performance |
| 429 | * critical parts: |
| 430 | * - rx is (pseudo-) lockless: it relies on the single-threading provided |
| 431 | * by the arch code for interrupts. |
| 432 | * - tx setup is lockless: it relies on dev->xmit_lock. Actual submission |
| 433 | * needs dev->priv->lock :-( |
| 434 | * - set_multicast_list: preparation lockless, relies on dev->xmit_lock. |
| 435 | */ |
| 436 | |
| 437 | /* in dev: base, irq */ |
| 438 | struct fe_priv { |
| 439 | spinlock_t lock; |
| 440 | |
| 441 | /* General data: |
| 442 | * Locking: spin_lock(&np->lock); */ |
| 443 | struct net_device_stats stats; |
| 444 | int in_shutdown; |
| 445 | u32 linkspeed; |
| 446 | int duplex; |
| 447 | int autoneg; |
| 448 | int fixed_mode; |
| 449 | int phyaddr; |
| 450 | int wolenabled; |
| 451 | unsigned int phy_oui; |
| 452 | u16 gigabit; |
| 453 | |
| 454 | /* General data: RO fields */ |
| 455 | dma_addr_t ring_addr; |
| 456 | struct pci_dev *pci_dev; |
| 457 | u32 orig_mac[2]; |
| 458 | u32 irqmask; |
| 459 | u32 desc_ver; |
| 460 | |
| 461 | void __iomem *base; |
| 462 | |
| 463 | /* rx specific fields. |
| 464 | * Locking: Within irq hander or disable_irq+spin_lock(&np->lock); |
| 465 | */ |
| 466 | struct ring_desc *rx_ring; |
| 467 | unsigned int cur_rx, refill_rx; |
| 468 | struct sk_buff *rx_skbuff[RX_RING]; |
| 469 | dma_addr_t rx_dma[RX_RING]; |
| 470 | unsigned int rx_buf_sz; |
| 471 | struct timer_list oom_kick; |
| 472 | struct timer_list nic_poll; |
| 473 | |
| 474 | /* media detection workaround. |
| 475 | * Locking: Within irq hander or disable_irq+spin_lock(&np->lock); |
| 476 | */ |
| 477 | int need_linktimer; |
| 478 | unsigned long link_timeout; |
| 479 | /* |
| 480 | * tx specific fields. |
| 481 | */ |
| 482 | struct ring_desc *tx_ring; |
| 483 | unsigned int next_tx, nic_tx; |
| 484 | struct sk_buff *tx_skbuff[TX_RING]; |
| 485 | dma_addr_t tx_dma[TX_RING]; |
| 486 | u32 tx_flags; |
| 487 | }; |
| 488 | |
| 489 | /* |
| 490 | * Maximum number of loops until we assume that a bit in the irq mask |
| 491 | * is stuck. Overridable with module param. |
| 492 | */ |
| 493 | static int max_interrupt_work = 5; |
| 494 | |
| 495 | static inline struct fe_priv *get_nvpriv(struct net_device *dev) |
| 496 | { |
| 497 | return netdev_priv(dev); |
| 498 | } |
| 499 | |
| 500 | static inline u8 __iomem *get_hwbase(struct net_device *dev) |
| 501 | { |
| 502 | return get_nvpriv(dev)->base; |
| 503 | } |
| 504 | |
| 505 | static inline void pci_push(u8 __iomem *base) |
| 506 | { |
| 507 | /* force out pending posted writes */ |
| 508 | readl(base); |
| 509 | } |
| 510 | |
| 511 | static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v) |
| 512 | { |
| 513 | return le32_to_cpu(prd->FlagLen) |
| 514 | & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2); |
| 515 | } |
| 516 | |
| 517 | static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target, |
| 518 | int delay, int delaymax, const char *msg) |
| 519 | { |
| 520 | u8 __iomem *base = get_hwbase(dev); |
| 521 | |
| 522 | pci_push(base); |
| 523 | do { |
| 524 | udelay(delay); |
| 525 | delaymax -= delay; |
| 526 | if (delaymax < 0) { |
| 527 | if (msg) |
| 528 | printk(msg); |
| 529 | return 1; |
| 530 | } |
| 531 | } while ((readl(base + offset) & mask) != target); |
| 532 | return 0; |
| 533 | } |
| 534 | |
| 535 | #define MII_READ (-1) |
| 536 | /* mii_rw: read/write a register on the PHY. |
| 537 | * |
| 538 | * Caller must guarantee serialization |
| 539 | */ |
| 540 | static int mii_rw(struct net_device *dev, int addr, int miireg, int value) |
| 541 | { |
| 542 | u8 __iomem *base = get_hwbase(dev); |
| 543 | u32 reg; |
| 544 | int retval; |
| 545 | |
| 546 | writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus); |
| 547 | |
| 548 | reg = readl(base + NvRegMIIControl); |
| 549 | if (reg & NVREG_MIICTL_INUSE) { |
| 550 | writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl); |
| 551 | udelay(NV_MIIBUSY_DELAY); |
| 552 | } |
| 553 | |
| 554 | reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg; |
| 555 | if (value != MII_READ) { |
| 556 | writel(value, base + NvRegMIIData); |
| 557 | reg |= NVREG_MIICTL_WRITE; |
| 558 | } |
| 559 | writel(reg, base + NvRegMIIControl); |
| 560 | |
| 561 | if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0, |
| 562 | NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) { |
| 563 | dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n", |
| 564 | dev->name, miireg, addr); |
| 565 | retval = -1; |
| 566 | } else if (value != MII_READ) { |
| 567 | /* it was a write operation - fewer failures are detectable */ |
| 568 | dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n", |
| 569 | dev->name, value, miireg, addr); |
| 570 | retval = 0; |
| 571 | } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) { |
| 572 | dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n", |
| 573 | dev->name, miireg, addr); |
| 574 | retval = -1; |
| 575 | } else { |
| 576 | retval = readl(base + NvRegMIIData); |
| 577 | dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n", |
| 578 | dev->name, miireg, addr, retval); |
| 579 | } |
| 580 | |
| 581 | return retval; |
| 582 | } |
| 583 | |
| 584 | static int phy_reset(struct net_device *dev) |
| 585 | { |
| 586 | struct fe_priv *np = get_nvpriv(dev); |
| 587 | u32 miicontrol; |
| 588 | unsigned int tries = 0; |
| 589 | |
| 590 | miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
| 591 | miicontrol |= BMCR_RESET; |
| 592 | if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) { |
| 593 | return -1; |
| 594 | } |
| 595 | |
| 596 | /* wait for 500ms */ |
| 597 | msleep(500); |
| 598 | |
| 599 | /* must wait till reset is deasserted */ |
| 600 | while (miicontrol & BMCR_RESET) { |
| 601 | msleep(10); |
| 602 | miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
| 603 | /* FIXME: 100 tries seem excessive */ |
| 604 | if (tries++ > 100) |
| 605 | return -1; |
| 606 | } |
| 607 | return 0; |
| 608 | } |
| 609 | |
| 610 | static int phy_init(struct net_device *dev) |
| 611 | { |
| 612 | struct fe_priv *np = get_nvpriv(dev); |
| 613 | u8 __iomem *base = get_hwbase(dev); |
| 614 | u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg; |
| 615 | |
| 616 | /* set advertise register */ |
| 617 | reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); |
| 618 | reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|0x800|0x400); |
| 619 | if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) { |
| 620 | printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev)); |
| 621 | return PHY_ERROR; |
| 622 | } |
| 623 | |
| 624 | /* get phy interface type */ |
| 625 | phyinterface = readl(base + NvRegPhyInterface); |
| 626 | |
| 627 | /* see if gigabit phy */ |
| 628 | mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); |
| 629 | if (mii_status & PHY_GIGABIT) { |
| 630 | np->gigabit = PHY_GIGABIT; |
| 631 | mii_control_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ); |
| 632 | mii_control_1000 &= ~ADVERTISE_1000HALF; |
| 633 | if (phyinterface & PHY_RGMII) |
| 634 | mii_control_1000 |= ADVERTISE_1000FULL; |
| 635 | else |
| 636 | mii_control_1000 &= ~ADVERTISE_1000FULL; |
| 637 | |
| 638 | if (mii_rw(dev, np->phyaddr, MII_1000BT_CR, mii_control_1000)) { |
| 639 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); |
| 640 | return PHY_ERROR; |
| 641 | } |
| 642 | } |
| 643 | else |
| 644 | np->gigabit = 0; |
| 645 | |
| 646 | /* reset the phy */ |
| 647 | if (phy_reset(dev)) { |
| 648 | printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev)); |
| 649 | return PHY_ERROR; |
| 650 | } |
| 651 | |
| 652 | /* phy vendor specific configuration */ |
| 653 | if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) { |
| 654 | phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ); |
| 655 | phy_reserved &= ~(PHY_INIT1 | PHY_INIT2); |
| 656 | phy_reserved |= (PHY_INIT3 | PHY_INIT4); |
| 657 | if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) { |
| 658 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); |
| 659 | return PHY_ERROR; |
| 660 | } |
| 661 | phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ); |
| 662 | phy_reserved |= PHY_INIT5; |
| 663 | if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) { |
| 664 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); |
| 665 | return PHY_ERROR; |
| 666 | } |
| 667 | } |
| 668 | if (np->phy_oui == PHY_OUI_CICADA) { |
| 669 | phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ); |
| 670 | phy_reserved |= PHY_INIT6; |
| 671 | if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) { |
| 672 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); |
| 673 | return PHY_ERROR; |
| 674 | } |
| 675 | } |
| 676 | |
| 677 | /* restart auto negotiation */ |
| 678 | mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
| 679 | mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE); |
| 680 | if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) { |
| 681 | return PHY_ERROR; |
| 682 | } |
| 683 | |
| 684 | return 0; |
| 685 | } |
| 686 | |
| 687 | static void nv_start_rx(struct net_device *dev) |
| 688 | { |
| 689 | struct fe_priv *np = get_nvpriv(dev); |
| 690 | u8 __iomem *base = get_hwbase(dev); |
| 691 | |
| 692 | dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name); |
| 693 | /* Already running? Stop it. */ |
| 694 | if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) { |
| 695 | writel(0, base + NvRegReceiverControl); |
| 696 | pci_push(base); |
| 697 | } |
| 698 | writel(np->linkspeed, base + NvRegLinkSpeed); |
| 699 | pci_push(base); |
| 700 | writel(NVREG_RCVCTL_START, base + NvRegReceiverControl); |
| 701 | dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n", |
| 702 | dev->name, np->duplex, np->linkspeed); |
| 703 | pci_push(base); |
| 704 | } |
| 705 | |
| 706 | static void nv_stop_rx(struct net_device *dev) |
| 707 | { |
| 708 | u8 __iomem *base = get_hwbase(dev); |
| 709 | |
| 710 | dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name); |
| 711 | writel(0, base + NvRegReceiverControl); |
| 712 | reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0, |
| 713 | NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX, |
| 714 | KERN_INFO "nv_stop_rx: ReceiverStatus remained busy"); |
| 715 | |
| 716 | udelay(NV_RXSTOP_DELAY2); |
| 717 | writel(0, base + NvRegLinkSpeed); |
| 718 | } |
| 719 | |
| 720 | static void nv_start_tx(struct net_device *dev) |
| 721 | { |
| 722 | u8 __iomem *base = get_hwbase(dev); |
| 723 | |
| 724 | dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name); |
| 725 | writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl); |
| 726 | pci_push(base); |
| 727 | } |
| 728 | |
| 729 | static void nv_stop_tx(struct net_device *dev) |
| 730 | { |
| 731 | u8 __iomem *base = get_hwbase(dev); |
| 732 | |
| 733 | dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name); |
| 734 | writel(0, base + NvRegTransmitterControl); |
| 735 | reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0, |
| 736 | NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX, |
| 737 | KERN_INFO "nv_stop_tx: TransmitterStatus remained busy"); |
| 738 | |
| 739 | udelay(NV_TXSTOP_DELAY2); |
| 740 | writel(0, base + NvRegUnknownTransmitterReg); |
| 741 | } |
| 742 | |
| 743 | static void nv_txrx_reset(struct net_device *dev) |
| 744 | { |
| 745 | struct fe_priv *np = get_nvpriv(dev); |
| 746 | u8 __iomem *base = get_hwbase(dev); |
| 747 | |
| 748 | dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name); |
| 749 | writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->desc_ver, base + NvRegTxRxControl); |
| 750 | pci_push(base); |
| 751 | udelay(NV_TXRX_RESET_DELAY); |
| 752 | writel(NVREG_TXRXCTL_BIT2 | np->desc_ver, base + NvRegTxRxControl); |
| 753 | pci_push(base); |
| 754 | } |
| 755 | |
| 756 | /* |
| 757 | * nv_get_stats: dev->get_stats function |
| 758 | * Get latest stats value from the nic. |
| 759 | * Called with read_lock(&dev_base_lock) held for read - |
| 760 | * only synchronized against unregister_netdevice. |
| 761 | */ |
| 762 | static struct net_device_stats *nv_get_stats(struct net_device *dev) |
| 763 | { |
| 764 | struct fe_priv *np = get_nvpriv(dev); |
| 765 | |
| 766 | /* It seems that the nic always generates interrupts and doesn't |
| 767 | * accumulate errors internally. Thus the current values in np->stats |
| 768 | * are already up to date. |
| 769 | */ |
| 770 | return &np->stats; |
| 771 | } |
| 772 | |
| 773 | /* |
| 774 | * nv_alloc_rx: fill rx ring entries. |
| 775 | * Return 1 if the allocations for the skbs failed and the |
| 776 | * rx engine is without Available descriptors |
| 777 | */ |
| 778 | static int nv_alloc_rx(struct net_device *dev) |
| 779 | { |
| 780 | struct fe_priv *np = get_nvpriv(dev); |
| 781 | unsigned int refill_rx = np->refill_rx; |
| 782 | int nr; |
| 783 | |
| 784 | while (np->cur_rx != refill_rx) { |
| 785 | struct sk_buff *skb; |
| 786 | |
| 787 | nr = refill_rx % RX_RING; |
| 788 | if (np->rx_skbuff[nr] == NULL) { |
| 789 | |
| 790 | skb = dev_alloc_skb(RX_ALLOC_BUFSIZE); |
| 791 | if (!skb) |
| 792 | break; |
| 793 | |
| 794 | skb->dev = dev; |
| 795 | np->rx_skbuff[nr] = skb; |
| 796 | } else { |
| 797 | skb = np->rx_skbuff[nr]; |
| 798 | } |
| 799 | np->rx_dma[nr] = pci_map_single(np->pci_dev, skb->data, skb->len, |
| 800 | PCI_DMA_FROMDEVICE); |
| 801 | np->rx_ring[nr].PacketBuffer = cpu_to_le32(np->rx_dma[nr]); |
| 802 | wmb(); |
| 803 | np->rx_ring[nr].FlagLen = cpu_to_le32(RX_NIC_BUFSIZE | NV_RX_AVAIL); |
| 804 | dprintk(KERN_DEBUG "%s: nv_alloc_rx: Packet %d marked as Available\n", |
| 805 | dev->name, refill_rx); |
| 806 | refill_rx++; |
| 807 | } |
| 808 | np->refill_rx = refill_rx; |
| 809 | if (np->cur_rx - refill_rx == RX_RING) |
| 810 | return 1; |
| 811 | return 0; |
| 812 | } |
| 813 | |
| 814 | static void nv_do_rx_refill(unsigned long data) |
| 815 | { |
| 816 | struct net_device *dev = (struct net_device *) data; |
| 817 | struct fe_priv *np = get_nvpriv(dev); |
| 818 | |
| 819 | disable_irq(dev->irq); |
| 820 | if (nv_alloc_rx(dev)) { |
| 821 | spin_lock(&np->lock); |
| 822 | if (!np->in_shutdown) |
| 823 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); |
| 824 | spin_unlock(&np->lock); |
| 825 | } |
| 826 | enable_irq(dev->irq); |
| 827 | } |
| 828 | |
| 829 | static int nv_init_ring(struct net_device *dev) |
| 830 | { |
| 831 | struct fe_priv *np = get_nvpriv(dev); |
| 832 | int i; |
| 833 | |
| 834 | np->next_tx = np->nic_tx = 0; |
| 835 | for (i = 0; i < TX_RING; i++) |
| 836 | np->tx_ring[i].FlagLen = 0; |
| 837 | |
| 838 | np->cur_rx = RX_RING; |
| 839 | np->refill_rx = 0; |
| 840 | for (i = 0; i < RX_RING; i++) |
| 841 | np->rx_ring[i].FlagLen = 0; |
| 842 | return nv_alloc_rx(dev); |
| 843 | } |
| 844 | |
| 845 | static void nv_drain_tx(struct net_device *dev) |
| 846 | { |
| 847 | struct fe_priv *np = get_nvpriv(dev); |
| 848 | int i; |
| 849 | for (i = 0; i < TX_RING; i++) { |
| 850 | np->tx_ring[i].FlagLen = 0; |
| 851 | if (np->tx_skbuff[i]) { |
| 852 | pci_unmap_single(np->pci_dev, np->tx_dma[i], |
| 853 | np->tx_skbuff[i]->len, |
| 854 | PCI_DMA_TODEVICE); |
| 855 | dev_kfree_skb(np->tx_skbuff[i]); |
| 856 | np->tx_skbuff[i] = NULL; |
| 857 | np->stats.tx_dropped++; |
| 858 | } |
| 859 | } |
| 860 | } |
| 861 | |
| 862 | static void nv_drain_rx(struct net_device *dev) |
| 863 | { |
| 864 | struct fe_priv *np = get_nvpriv(dev); |
| 865 | int i; |
| 866 | for (i = 0; i < RX_RING; i++) { |
| 867 | np->rx_ring[i].FlagLen = 0; |
| 868 | wmb(); |
| 869 | if (np->rx_skbuff[i]) { |
| 870 | pci_unmap_single(np->pci_dev, np->rx_dma[i], |
| 871 | np->rx_skbuff[i]->len, |
| 872 | PCI_DMA_FROMDEVICE); |
| 873 | dev_kfree_skb(np->rx_skbuff[i]); |
| 874 | np->rx_skbuff[i] = NULL; |
| 875 | } |
| 876 | } |
| 877 | } |
| 878 | |
| 879 | static void drain_ring(struct net_device *dev) |
| 880 | { |
| 881 | nv_drain_tx(dev); |
| 882 | nv_drain_rx(dev); |
| 883 | } |
| 884 | |
| 885 | /* |
| 886 | * nv_start_xmit: dev->hard_start_xmit function |
| 887 | * Called with dev->xmit_lock held. |
| 888 | */ |
| 889 | static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev) |
| 890 | { |
| 891 | struct fe_priv *np = get_nvpriv(dev); |
| 892 | int nr = np->next_tx % TX_RING; |
| 893 | |
| 894 | np->tx_skbuff[nr] = skb; |
| 895 | np->tx_dma[nr] = pci_map_single(np->pci_dev, skb->data,skb->len, |
| 896 | PCI_DMA_TODEVICE); |
| 897 | |
| 898 | np->tx_ring[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]); |
| 899 | |
| 900 | spin_lock_irq(&np->lock); |
| 901 | wmb(); |
| 902 | np->tx_ring[nr].FlagLen = cpu_to_le32( (skb->len-1) | np->tx_flags ); |
| 903 | dprintk(KERN_DEBUG "%s: nv_start_xmit: packet packet %d queued for transmission.\n", |
| 904 | dev->name, np->next_tx); |
| 905 | { |
| 906 | int j; |
| 907 | for (j=0; j<64; j++) { |
| 908 | if ((j%16) == 0) |
| 909 | dprintk("\n%03x:", j); |
| 910 | dprintk(" %02x", ((unsigned char*)skb->data)[j]); |
| 911 | } |
| 912 | dprintk("\n"); |
| 913 | } |
| 914 | |
| 915 | np->next_tx++; |
| 916 | |
| 917 | dev->trans_start = jiffies; |
| 918 | if (np->next_tx - np->nic_tx >= TX_LIMIT_STOP) |
| 919 | netif_stop_queue(dev); |
| 920 | spin_unlock_irq(&np->lock); |
| 921 | writel(NVREG_TXRXCTL_KICK|np->desc_ver, get_hwbase(dev) + NvRegTxRxControl); |
| 922 | pci_push(get_hwbase(dev)); |
| 923 | return 0; |
| 924 | } |
| 925 | |
| 926 | /* |
| 927 | * nv_tx_done: check for completed packets, release the skbs. |
| 928 | * |
| 929 | * Caller must own np->lock. |
| 930 | */ |
| 931 | static void nv_tx_done(struct net_device *dev) |
| 932 | { |
| 933 | struct fe_priv *np = get_nvpriv(dev); |
| 934 | u32 Flags; |
| 935 | int i; |
| 936 | |
| 937 | while (np->nic_tx != np->next_tx) { |
| 938 | i = np->nic_tx % TX_RING; |
| 939 | |
| 940 | Flags = le32_to_cpu(np->tx_ring[i].FlagLen); |
| 941 | |
| 942 | dprintk(KERN_DEBUG "%s: nv_tx_done: looking at packet %d, Flags 0x%x.\n", |
| 943 | dev->name, np->nic_tx, Flags); |
| 944 | if (Flags & NV_TX_VALID) |
| 945 | break; |
| 946 | if (np->desc_ver == DESC_VER_1) { |
| 947 | if (Flags & (NV_TX_RETRYERROR|NV_TX_CARRIERLOST|NV_TX_LATECOLLISION| |
| 948 | NV_TX_UNDERFLOW|NV_TX_ERROR)) { |
| 949 | if (Flags & NV_TX_UNDERFLOW) |
| 950 | np->stats.tx_fifo_errors++; |
| 951 | if (Flags & NV_TX_CARRIERLOST) |
| 952 | np->stats.tx_carrier_errors++; |
| 953 | np->stats.tx_errors++; |
| 954 | } else { |
| 955 | np->stats.tx_packets++; |
| 956 | np->stats.tx_bytes += np->tx_skbuff[i]->len; |
| 957 | } |
| 958 | } else { |
| 959 | if (Flags & (NV_TX2_RETRYERROR|NV_TX2_CARRIERLOST|NV_TX2_LATECOLLISION| |
| 960 | NV_TX2_UNDERFLOW|NV_TX2_ERROR)) { |
| 961 | if (Flags & NV_TX2_UNDERFLOW) |
| 962 | np->stats.tx_fifo_errors++; |
| 963 | if (Flags & NV_TX2_CARRIERLOST) |
| 964 | np->stats.tx_carrier_errors++; |
| 965 | np->stats.tx_errors++; |
| 966 | } else { |
| 967 | np->stats.tx_packets++; |
| 968 | np->stats.tx_bytes += np->tx_skbuff[i]->len; |
| 969 | } |
| 970 | } |
| 971 | pci_unmap_single(np->pci_dev, np->tx_dma[i], |
| 972 | np->tx_skbuff[i]->len, |
| 973 | PCI_DMA_TODEVICE); |
| 974 | dev_kfree_skb_irq(np->tx_skbuff[i]); |
| 975 | np->tx_skbuff[i] = NULL; |
| 976 | np->nic_tx++; |
| 977 | } |
| 978 | if (np->next_tx - np->nic_tx < TX_LIMIT_START) |
| 979 | netif_wake_queue(dev); |
| 980 | } |
| 981 | |
| 982 | /* |
| 983 | * nv_tx_timeout: dev->tx_timeout function |
| 984 | * Called with dev->xmit_lock held. |
| 985 | */ |
| 986 | static void nv_tx_timeout(struct net_device *dev) |
| 987 | { |
| 988 | struct fe_priv *np = get_nvpriv(dev); |
| 989 | u8 __iomem *base = get_hwbase(dev); |
| 990 | |
| 991 | dprintk(KERN_DEBUG "%s: Got tx_timeout. irq: %08x\n", dev->name, |
| 992 | readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK); |
| 993 | |
| 994 | spin_lock_irq(&np->lock); |
| 995 | |
| 996 | /* 1) stop tx engine */ |
| 997 | nv_stop_tx(dev); |
| 998 | |
| 999 | /* 2) check that the packets were not sent already: */ |
| 1000 | nv_tx_done(dev); |
| 1001 | |
| 1002 | /* 3) if there are dead entries: clear everything */ |
| 1003 | if (np->next_tx != np->nic_tx) { |
| 1004 | printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name); |
| 1005 | nv_drain_tx(dev); |
| 1006 | np->next_tx = np->nic_tx = 0; |
| 1007 | writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr); |
| 1008 | netif_wake_queue(dev); |
| 1009 | } |
| 1010 | |
| 1011 | /* 4) restart tx engine */ |
| 1012 | nv_start_tx(dev); |
| 1013 | spin_unlock_irq(&np->lock); |
| 1014 | } |
| 1015 | |
| 1016 | static void nv_rx_process(struct net_device *dev) |
| 1017 | { |
| 1018 | struct fe_priv *np = get_nvpriv(dev); |
| 1019 | u32 Flags; |
| 1020 | |
| 1021 | for (;;) { |
| 1022 | struct sk_buff *skb; |
| 1023 | int len; |
| 1024 | int i; |
| 1025 | if (np->cur_rx - np->refill_rx >= RX_RING) |
| 1026 | break; /* we scanned the whole ring - do not continue */ |
| 1027 | |
| 1028 | i = np->cur_rx % RX_RING; |
| 1029 | Flags = le32_to_cpu(np->rx_ring[i].FlagLen); |
| 1030 | len = nv_descr_getlength(&np->rx_ring[i], np->desc_ver); |
| 1031 | |
| 1032 | dprintk(KERN_DEBUG "%s: nv_rx_process: looking at packet %d, Flags 0x%x.\n", |
| 1033 | dev->name, np->cur_rx, Flags); |
| 1034 | |
| 1035 | if (Flags & NV_RX_AVAIL) |
| 1036 | break; /* still owned by hardware, */ |
| 1037 | |
| 1038 | /* |
| 1039 | * the packet is for us - immediately tear down the pci mapping. |
| 1040 | * TODO: check if a prefetch of the first cacheline improves |
| 1041 | * the performance. |
| 1042 | */ |
| 1043 | pci_unmap_single(np->pci_dev, np->rx_dma[i], |
| 1044 | np->rx_skbuff[i]->len, |
| 1045 | PCI_DMA_FROMDEVICE); |
| 1046 | |
| 1047 | { |
| 1048 | int j; |
| 1049 | dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",Flags); |
| 1050 | for (j=0; j<64; j++) { |
| 1051 | if ((j%16) == 0) |
| 1052 | dprintk("\n%03x:", j); |
| 1053 | dprintk(" %02x", ((unsigned char*)np->rx_skbuff[i]->data)[j]); |
| 1054 | } |
| 1055 | dprintk("\n"); |
| 1056 | } |
| 1057 | /* look at what we actually got: */ |
| 1058 | if (np->desc_ver == DESC_VER_1) { |
| 1059 | if (!(Flags & NV_RX_DESCRIPTORVALID)) |
| 1060 | goto next_pkt; |
| 1061 | |
| 1062 | if (Flags & NV_RX_MISSEDFRAME) { |
| 1063 | np->stats.rx_missed_errors++; |
| 1064 | np->stats.rx_errors++; |
| 1065 | goto next_pkt; |
| 1066 | } |
| 1067 | if (Flags & (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4)) { |
| 1068 | np->stats.rx_errors++; |
| 1069 | goto next_pkt; |
| 1070 | } |
| 1071 | if (Flags & NV_RX_CRCERR) { |
| 1072 | np->stats.rx_crc_errors++; |
| 1073 | np->stats.rx_errors++; |
| 1074 | goto next_pkt; |
| 1075 | } |
| 1076 | if (Flags & NV_RX_OVERFLOW) { |
| 1077 | np->stats.rx_over_errors++; |
| 1078 | np->stats.rx_errors++; |
| 1079 | goto next_pkt; |
| 1080 | } |
| 1081 | if (Flags & NV_RX_ERROR) { |
| 1082 | /* framing errors are soft errors, the rest is fatal. */ |
| 1083 | if (Flags & NV_RX_FRAMINGERR) { |
| 1084 | if (Flags & NV_RX_SUBSTRACT1) { |
| 1085 | len--; |
| 1086 | } |
| 1087 | } else { |
| 1088 | np->stats.rx_errors++; |
| 1089 | goto next_pkt; |
| 1090 | } |
| 1091 | } |
| 1092 | } else { |
| 1093 | if (!(Flags & NV_RX2_DESCRIPTORVALID)) |
| 1094 | goto next_pkt; |
| 1095 | |
| 1096 | if (Flags & (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4)) { |
| 1097 | np->stats.rx_errors++; |
| 1098 | goto next_pkt; |
| 1099 | } |
| 1100 | if (Flags & NV_RX2_CRCERR) { |
| 1101 | np->stats.rx_crc_errors++; |
| 1102 | np->stats.rx_errors++; |
| 1103 | goto next_pkt; |
| 1104 | } |
| 1105 | if (Flags & NV_RX2_OVERFLOW) { |
| 1106 | np->stats.rx_over_errors++; |
| 1107 | np->stats.rx_errors++; |
| 1108 | goto next_pkt; |
| 1109 | } |
| 1110 | if (Flags & NV_RX2_ERROR) { |
| 1111 | /* framing errors are soft errors, the rest is fatal. */ |
| 1112 | if (Flags & NV_RX2_FRAMINGERR) { |
| 1113 | if (Flags & NV_RX2_SUBSTRACT1) { |
| 1114 | len--; |
| 1115 | } |
| 1116 | } else { |
| 1117 | np->stats.rx_errors++; |
| 1118 | goto next_pkt; |
| 1119 | } |
| 1120 | } |
| 1121 | Flags &= NV_RX2_CHECKSUMMASK; |
| 1122 | if (Flags == NV_RX2_CHECKSUMOK1 || |
| 1123 | Flags == NV_RX2_CHECKSUMOK2 || |
| 1124 | Flags == NV_RX2_CHECKSUMOK3) { |
| 1125 | dprintk(KERN_DEBUG "%s: hw checksum hit!.\n", dev->name); |
| 1126 | np->rx_skbuff[i]->ip_summed = CHECKSUM_UNNECESSARY; |
| 1127 | } else { |
| 1128 | dprintk(KERN_DEBUG "%s: hwchecksum miss!.\n", dev->name); |
| 1129 | } |
| 1130 | } |
| 1131 | /* got a valid packet - forward it to the network core */ |
| 1132 | skb = np->rx_skbuff[i]; |
| 1133 | np->rx_skbuff[i] = NULL; |
| 1134 | |
| 1135 | skb_put(skb, len); |
| 1136 | skb->protocol = eth_type_trans(skb, dev); |
| 1137 | dprintk(KERN_DEBUG "%s: nv_rx_process: packet %d with %d bytes, proto %d accepted.\n", |
| 1138 | dev->name, np->cur_rx, len, skb->protocol); |
| 1139 | netif_rx(skb); |
| 1140 | dev->last_rx = jiffies; |
| 1141 | np->stats.rx_packets++; |
| 1142 | np->stats.rx_bytes += len; |
| 1143 | next_pkt: |
| 1144 | np->cur_rx++; |
| 1145 | } |
| 1146 | } |
| 1147 | |
| 1148 | /* |
| 1149 | * nv_change_mtu: dev->change_mtu function |
| 1150 | * Called with dev_base_lock held for read. |
| 1151 | */ |
| 1152 | static int nv_change_mtu(struct net_device *dev, int new_mtu) |
| 1153 | { |
| 1154 | if (new_mtu > ETH_DATA_LEN) |
| 1155 | return -EINVAL; |
| 1156 | dev->mtu = new_mtu; |
| 1157 | return 0; |
| 1158 | } |
| 1159 | |
| 1160 | /* |
| 1161 | * nv_set_multicast: dev->set_multicast function |
| 1162 | * Called with dev->xmit_lock held. |
| 1163 | */ |
| 1164 | static void nv_set_multicast(struct net_device *dev) |
| 1165 | { |
| 1166 | struct fe_priv *np = get_nvpriv(dev); |
| 1167 | u8 __iomem *base = get_hwbase(dev); |
| 1168 | u32 addr[2]; |
| 1169 | u32 mask[2]; |
| 1170 | u32 pff; |
| 1171 | |
| 1172 | memset(addr, 0, sizeof(addr)); |
| 1173 | memset(mask, 0, sizeof(mask)); |
| 1174 | |
| 1175 | if (dev->flags & IFF_PROMISC) { |
| 1176 | printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name); |
| 1177 | pff = NVREG_PFF_PROMISC; |
| 1178 | } else { |
| 1179 | pff = NVREG_PFF_MYADDR; |
| 1180 | |
| 1181 | if (dev->flags & IFF_ALLMULTI || dev->mc_list) { |
| 1182 | u32 alwaysOff[2]; |
| 1183 | u32 alwaysOn[2]; |
| 1184 | |
| 1185 | alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff; |
| 1186 | if (dev->flags & IFF_ALLMULTI) { |
| 1187 | alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0; |
| 1188 | } else { |
| 1189 | struct dev_mc_list *walk; |
| 1190 | |
| 1191 | walk = dev->mc_list; |
| 1192 | while (walk != NULL) { |
| 1193 | u32 a, b; |
| 1194 | a = le32_to_cpu(*(u32 *) walk->dmi_addr); |
| 1195 | b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4])); |
| 1196 | alwaysOn[0] &= a; |
| 1197 | alwaysOff[0] &= ~a; |
| 1198 | alwaysOn[1] &= b; |
| 1199 | alwaysOff[1] &= ~b; |
| 1200 | walk = walk->next; |
| 1201 | } |
| 1202 | } |
| 1203 | addr[0] = alwaysOn[0]; |
| 1204 | addr[1] = alwaysOn[1]; |
| 1205 | mask[0] = alwaysOn[0] | alwaysOff[0]; |
| 1206 | mask[1] = alwaysOn[1] | alwaysOff[1]; |
| 1207 | } |
| 1208 | } |
| 1209 | addr[0] |= NVREG_MCASTADDRA_FORCE; |
| 1210 | pff |= NVREG_PFF_ALWAYS; |
| 1211 | spin_lock_irq(&np->lock); |
| 1212 | nv_stop_rx(dev); |
| 1213 | writel(addr[0], base + NvRegMulticastAddrA); |
| 1214 | writel(addr[1], base + NvRegMulticastAddrB); |
| 1215 | writel(mask[0], base + NvRegMulticastMaskA); |
| 1216 | writel(mask[1], base + NvRegMulticastMaskB); |
| 1217 | writel(pff, base + NvRegPacketFilterFlags); |
| 1218 | dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n", |
| 1219 | dev->name); |
| 1220 | nv_start_rx(dev); |
| 1221 | spin_unlock_irq(&np->lock); |
| 1222 | } |
| 1223 | |
| 1224 | static int nv_update_linkspeed(struct net_device *dev) |
| 1225 | { |
| 1226 | struct fe_priv *np = get_nvpriv(dev); |
| 1227 | u8 __iomem *base = get_hwbase(dev); |
| 1228 | int adv, lpa; |
| 1229 | int newls = np->linkspeed; |
| 1230 | int newdup = np->duplex; |
| 1231 | int mii_status; |
| 1232 | int retval = 0; |
| 1233 | u32 control_1000, status_1000, phyreg; |
| 1234 | |
| 1235 | /* BMSR_LSTATUS is latched, read it twice: |
| 1236 | * we want the current value. |
| 1237 | */ |
| 1238 | mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); |
| 1239 | mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); |
| 1240 | |
| 1241 | if (!(mii_status & BMSR_LSTATUS)) { |
| 1242 | dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n", |
| 1243 | dev->name); |
| 1244 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
| 1245 | newdup = 0; |
| 1246 | retval = 0; |
| 1247 | goto set_speed; |
| 1248 | } |
| 1249 | |
| 1250 | if (np->autoneg == 0) { |
| 1251 | dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n", |
| 1252 | dev->name, np->fixed_mode); |
| 1253 | if (np->fixed_mode & LPA_100FULL) { |
| 1254 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; |
| 1255 | newdup = 1; |
| 1256 | } else if (np->fixed_mode & LPA_100HALF) { |
| 1257 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; |
| 1258 | newdup = 0; |
| 1259 | } else if (np->fixed_mode & LPA_10FULL) { |
| 1260 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
| 1261 | newdup = 1; |
| 1262 | } else { |
| 1263 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
| 1264 | newdup = 0; |
| 1265 | } |
| 1266 | retval = 1; |
| 1267 | goto set_speed; |
| 1268 | } |
| 1269 | /* check auto negotiation is complete */ |
| 1270 | if (!(mii_status & BMSR_ANEGCOMPLETE)) { |
| 1271 | /* still in autonegotiation - configure nic for 10 MBit HD and wait. */ |
| 1272 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
| 1273 | newdup = 0; |
| 1274 | retval = 0; |
| 1275 | dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name); |
| 1276 | goto set_speed; |
| 1277 | } |
| 1278 | |
| 1279 | retval = 1; |
| 1280 | if (np->gigabit == PHY_GIGABIT) { |
| 1281 | control_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ); |
| 1282 | status_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_SR, MII_READ); |
| 1283 | |
| 1284 | if ((control_1000 & ADVERTISE_1000FULL) && |
| 1285 | (status_1000 & LPA_1000FULL)) { |
| 1286 | dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n", |
| 1287 | dev->name); |
| 1288 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000; |
| 1289 | newdup = 1; |
| 1290 | goto set_speed; |
| 1291 | } |
| 1292 | } |
| 1293 | |
| 1294 | adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); |
| 1295 | lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ); |
| 1296 | dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n", |
| 1297 | dev->name, adv, lpa); |
| 1298 | |
| 1299 | /* FIXME: handle parallel detection properly */ |
| 1300 | lpa = lpa & adv; |
| 1301 | if (lpa & LPA_100FULL) { |
| 1302 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; |
| 1303 | newdup = 1; |
| 1304 | } else if (lpa & LPA_100HALF) { |
| 1305 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; |
| 1306 | newdup = 0; |
| 1307 | } else if (lpa & LPA_10FULL) { |
| 1308 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
| 1309 | newdup = 1; |
| 1310 | } else if (lpa & LPA_10HALF) { |
| 1311 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
| 1312 | newdup = 0; |
| 1313 | } else { |
| 1314 | dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, lpa); |
| 1315 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
| 1316 | newdup = 0; |
| 1317 | } |
| 1318 | |
| 1319 | set_speed: |
| 1320 | if (np->duplex == newdup && np->linkspeed == newls) |
| 1321 | return retval; |
| 1322 | |
| 1323 | dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n", |
| 1324 | dev->name, np->linkspeed, np->duplex, newls, newdup); |
| 1325 | |
| 1326 | np->duplex = newdup; |
| 1327 | np->linkspeed = newls; |
| 1328 | |
| 1329 | if (np->gigabit == PHY_GIGABIT) { |
| 1330 | phyreg = readl(base + NvRegRandomSeed); |
| 1331 | phyreg &= ~(0x3FF00); |
| 1332 | if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) |
| 1333 | phyreg |= NVREG_RNDSEED_FORCE3; |
| 1334 | else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100) |
| 1335 | phyreg |= NVREG_RNDSEED_FORCE2; |
| 1336 | else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000) |
| 1337 | phyreg |= NVREG_RNDSEED_FORCE; |
| 1338 | writel(phyreg, base + NvRegRandomSeed); |
| 1339 | } |
| 1340 | |
| 1341 | phyreg = readl(base + NvRegPhyInterface); |
| 1342 | phyreg &= ~(PHY_HALF|PHY_100|PHY_1000); |
| 1343 | if (np->duplex == 0) |
| 1344 | phyreg |= PHY_HALF; |
| 1345 | if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100) |
| 1346 | phyreg |= PHY_100; |
| 1347 | else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) |
| 1348 | phyreg |= PHY_1000; |
| 1349 | writel(phyreg, base + NvRegPhyInterface); |
| 1350 | |
| 1351 | writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD), |
| 1352 | base + NvRegMisc1); |
| 1353 | pci_push(base); |
| 1354 | writel(np->linkspeed, base + NvRegLinkSpeed); |
| 1355 | pci_push(base); |
| 1356 | |
| 1357 | return retval; |
| 1358 | } |
| 1359 | |
| 1360 | static void nv_linkchange(struct net_device *dev) |
| 1361 | { |
| 1362 | if (nv_update_linkspeed(dev)) { |
| 1363 | if (netif_carrier_ok(dev)) { |
| 1364 | nv_stop_rx(dev); |
| 1365 | } else { |
| 1366 | netif_carrier_on(dev); |
| 1367 | printk(KERN_INFO "%s: link up.\n", dev->name); |
| 1368 | } |
| 1369 | nv_start_rx(dev); |
| 1370 | } else { |
| 1371 | if (netif_carrier_ok(dev)) { |
| 1372 | netif_carrier_off(dev); |
| 1373 | printk(KERN_INFO "%s: link down.\n", dev->name); |
| 1374 | nv_stop_rx(dev); |
| 1375 | } |
| 1376 | } |
| 1377 | } |
| 1378 | |
| 1379 | static void nv_link_irq(struct net_device *dev) |
| 1380 | { |
| 1381 | u8 __iomem *base = get_hwbase(dev); |
| 1382 | u32 miistat; |
| 1383 | |
| 1384 | miistat = readl(base + NvRegMIIStatus); |
| 1385 | writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus); |
| 1386 | dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat); |
| 1387 | |
| 1388 | if (miistat & (NVREG_MIISTAT_LINKCHANGE)) |
| 1389 | nv_linkchange(dev); |
| 1390 | dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name); |
| 1391 | } |
| 1392 | |
| 1393 | static irqreturn_t nv_nic_irq(int foo, void *data, struct pt_regs *regs) |
| 1394 | { |
| 1395 | struct net_device *dev = (struct net_device *) data; |
| 1396 | struct fe_priv *np = get_nvpriv(dev); |
| 1397 | u8 __iomem *base = get_hwbase(dev); |
| 1398 | u32 events; |
| 1399 | int i; |
| 1400 | |
| 1401 | dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name); |
| 1402 | |
| 1403 | for (i=0; ; i++) { |
| 1404 | events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK; |
| 1405 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); |
| 1406 | pci_push(base); |
| 1407 | dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events); |
| 1408 | if (!(events & np->irqmask)) |
| 1409 | break; |
| 1410 | |
| 1411 | if (events & (NVREG_IRQ_TX1|NVREG_IRQ_TX2|NVREG_IRQ_TX_ERR)) { |
| 1412 | spin_lock(&np->lock); |
| 1413 | nv_tx_done(dev); |
| 1414 | spin_unlock(&np->lock); |
| 1415 | } |
| 1416 | |
| 1417 | if (events & (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF)) { |
| 1418 | nv_rx_process(dev); |
| 1419 | if (nv_alloc_rx(dev)) { |
| 1420 | spin_lock(&np->lock); |
| 1421 | if (!np->in_shutdown) |
| 1422 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); |
| 1423 | spin_unlock(&np->lock); |
| 1424 | } |
| 1425 | } |
| 1426 | |
| 1427 | if (events & NVREG_IRQ_LINK) { |
| 1428 | spin_lock(&np->lock); |
| 1429 | nv_link_irq(dev); |
| 1430 | spin_unlock(&np->lock); |
| 1431 | } |
| 1432 | if (np->need_linktimer && time_after(jiffies, np->link_timeout)) { |
| 1433 | spin_lock(&np->lock); |
| 1434 | nv_linkchange(dev); |
| 1435 | spin_unlock(&np->lock); |
| 1436 | np->link_timeout = jiffies + LINK_TIMEOUT; |
| 1437 | } |
| 1438 | if (events & (NVREG_IRQ_TX_ERR)) { |
| 1439 | dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n", |
| 1440 | dev->name, events); |
| 1441 | } |
| 1442 | if (events & (NVREG_IRQ_UNKNOWN)) { |
| 1443 | printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n", |
| 1444 | dev->name, events); |
| 1445 | } |
| 1446 | if (i > max_interrupt_work) { |
| 1447 | spin_lock(&np->lock); |
| 1448 | /* disable interrupts on the nic */ |
| 1449 | writel(0, base + NvRegIrqMask); |
| 1450 | pci_push(base); |
| 1451 | |
| 1452 | if (!np->in_shutdown) |
| 1453 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); |
| 1454 | printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i); |
| 1455 | spin_unlock(&np->lock); |
| 1456 | break; |
| 1457 | } |
| 1458 | |
| 1459 | } |
| 1460 | dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name); |
| 1461 | |
| 1462 | return IRQ_RETVAL(i); |
| 1463 | } |
| 1464 | |
| 1465 | static void nv_do_nic_poll(unsigned long data) |
| 1466 | { |
| 1467 | struct net_device *dev = (struct net_device *) data; |
| 1468 | struct fe_priv *np = get_nvpriv(dev); |
| 1469 | u8 __iomem *base = get_hwbase(dev); |
| 1470 | |
| 1471 | disable_irq(dev->irq); |
| 1472 | /* FIXME: Do we need synchronize_irq(dev->irq) here? */ |
| 1473 | /* |
| 1474 | * reenable interrupts on the nic, we have to do this before calling |
| 1475 | * nv_nic_irq because that may decide to do otherwise |
| 1476 | */ |
| 1477 | writel(np->irqmask, base + NvRegIrqMask); |
| 1478 | pci_push(base); |
| 1479 | nv_nic_irq((int) 0, (void *) data, (struct pt_regs *) NULL); |
| 1480 | enable_irq(dev->irq); |
| 1481 | } |
| 1482 | |
| 1483 | static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) |
| 1484 | { |
| 1485 | struct fe_priv *np = get_nvpriv(dev); |
| 1486 | strcpy(info->driver, "forcedeth"); |
| 1487 | strcpy(info->version, FORCEDETH_VERSION); |
| 1488 | strcpy(info->bus_info, pci_name(np->pci_dev)); |
| 1489 | } |
| 1490 | |
| 1491 | static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo) |
| 1492 | { |
| 1493 | struct fe_priv *np = get_nvpriv(dev); |
| 1494 | wolinfo->supported = WAKE_MAGIC; |
| 1495 | |
| 1496 | spin_lock_irq(&np->lock); |
| 1497 | if (np->wolenabled) |
| 1498 | wolinfo->wolopts = WAKE_MAGIC; |
| 1499 | spin_unlock_irq(&np->lock); |
| 1500 | } |
| 1501 | |
| 1502 | static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo) |
| 1503 | { |
| 1504 | struct fe_priv *np = get_nvpriv(dev); |
| 1505 | u8 __iomem *base = get_hwbase(dev); |
| 1506 | |
| 1507 | spin_lock_irq(&np->lock); |
| 1508 | if (wolinfo->wolopts == 0) { |
| 1509 | writel(0, base + NvRegWakeUpFlags); |
| 1510 | np->wolenabled = 0; |
| 1511 | } |
| 1512 | if (wolinfo->wolopts & WAKE_MAGIC) { |
| 1513 | writel(NVREG_WAKEUPFLAGS_ENABLE, base + NvRegWakeUpFlags); |
| 1514 | np->wolenabled = 1; |
| 1515 | } |
| 1516 | spin_unlock_irq(&np->lock); |
| 1517 | return 0; |
| 1518 | } |
| 1519 | |
| 1520 | static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) |
| 1521 | { |
| 1522 | struct fe_priv *np = netdev_priv(dev); |
| 1523 | int adv; |
| 1524 | |
| 1525 | spin_lock_irq(&np->lock); |
| 1526 | ecmd->port = PORT_MII; |
| 1527 | if (!netif_running(dev)) { |
| 1528 | /* We do not track link speed / duplex setting if the |
| 1529 | * interface is disabled. Force a link check */ |
| 1530 | nv_update_linkspeed(dev); |
| 1531 | } |
| 1532 | switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) { |
| 1533 | case NVREG_LINKSPEED_10: |
| 1534 | ecmd->speed = SPEED_10; |
| 1535 | break; |
| 1536 | case NVREG_LINKSPEED_100: |
| 1537 | ecmd->speed = SPEED_100; |
| 1538 | break; |
| 1539 | case NVREG_LINKSPEED_1000: |
| 1540 | ecmd->speed = SPEED_1000; |
| 1541 | break; |
| 1542 | } |
| 1543 | ecmd->duplex = DUPLEX_HALF; |
| 1544 | if (np->duplex) |
| 1545 | ecmd->duplex = DUPLEX_FULL; |
| 1546 | |
| 1547 | ecmd->autoneg = np->autoneg; |
| 1548 | |
| 1549 | ecmd->advertising = ADVERTISED_MII; |
| 1550 | if (np->autoneg) { |
| 1551 | ecmd->advertising |= ADVERTISED_Autoneg; |
| 1552 | adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); |
| 1553 | } else { |
| 1554 | adv = np->fixed_mode; |
| 1555 | } |
| 1556 | if (adv & ADVERTISE_10HALF) |
| 1557 | ecmd->advertising |= ADVERTISED_10baseT_Half; |
| 1558 | if (adv & ADVERTISE_10FULL) |
| 1559 | ecmd->advertising |= ADVERTISED_10baseT_Full; |
| 1560 | if (adv & ADVERTISE_100HALF) |
| 1561 | ecmd->advertising |= ADVERTISED_100baseT_Half; |
| 1562 | if (adv & ADVERTISE_100FULL) |
| 1563 | ecmd->advertising |= ADVERTISED_100baseT_Full; |
| 1564 | if (np->autoneg && np->gigabit == PHY_GIGABIT) { |
| 1565 | adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ); |
| 1566 | if (adv & ADVERTISE_1000FULL) |
| 1567 | ecmd->advertising |= ADVERTISED_1000baseT_Full; |
| 1568 | } |
| 1569 | |
| 1570 | ecmd->supported = (SUPPORTED_Autoneg | |
| 1571 | SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | |
| 1572 | SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | |
| 1573 | SUPPORTED_MII); |
| 1574 | if (np->gigabit == PHY_GIGABIT) |
| 1575 | ecmd->supported |= SUPPORTED_1000baseT_Full; |
| 1576 | |
| 1577 | ecmd->phy_address = np->phyaddr; |
| 1578 | ecmd->transceiver = XCVR_EXTERNAL; |
| 1579 | |
| 1580 | /* ignore maxtxpkt, maxrxpkt for now */ |
| 1581 | spin_unlock_irq(&np->lock); |
| 1582 | return 0; |
| 1583 | } |
| 1584 | |
| 1585 | static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) |
| 1586 | { |
| 1587 | struct fe_priv *np = netdev_priv(dev); |
| 1588 | |
| 1589 | if (ecmd->port != PORT_MII) |
| 1590 | return -EINVAL; |
| 1591 | if (ecmd->transceiver != XCVR_EXTERNAL) |
| 1592 | return -EINVAL; |
| 1593 | if (ecmd->phy_address != np->phyaddr) { |
| 1594 | /* TODO: support switching between multiple phys. Should be |
| 1595 | * trivial, but not enabled due to lack of test hardware. */ |
| 1596 | return -EINVAL; |
| 1597 | } |
| 1598 | if (ecmd->autoneg == AUTONEG_ENABLE) { |
| 1599 | u32 mask; |
| 1600 | |
| 1601 | mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | |
| 1602 | ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full; |
| 1603 | if (np->gigabit == PHY_GIGABIT) |
| 1604 | mask |= ADVERTISED_1000baseT_Full; |
| 1605 | |
| 1606 | if ((ecmd->advertising & mask) == 0) |
| 1607 | return -EINVAL; |
| 1608 | |
| 1609 | } else if (ecmd->autoneg == AUTONEG_DISABLE) { |
| 1610 | /* Note: autonegotiation disable, speed 1000 intentionally |
| 1611 | * forbidden - noone should need that. */ |
| 1612 | |
| 1613 | if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100) |
| 1614 | return -EINVAL; |
| 1615 | if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL) |
| 1616 | return -EINVAL; |
| 1617 | } else { |
| 1618 | return -EINVAL; |
| 1619 | } |
| 1620 | |
| 1621 | spin_lock_irq(&np->lock); |
| 1622 | if (ecmd->autoneg == AUTONEG_ENABLE) { |
| 1623 | int adv, bmcr; |
| 1624 | |
| 1625 | np->autoneg = 1; |
| 1626 | |
| 1627 | /* advertise only what has been requested */ |
| 1628 | adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); |
| 1629 | adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4); |
| 1630 | if (ecmd->advertising & ADVERTISED_10baseT_Half) |
| 1631 | adv |= ADVERTISE_10HALF; |
| 1632 | if (ecmd->advertising & ADVERTISED_10baseT_Full) |
| 1633 | adv |= ADVERTISE_10FULL; |
| 1634 | if (ecmd->advertising & ADVERTISED_100baseT_Half) |
| 1635 | adv |= ADVERTISE_100HALF; |
| 1636 | if (ecmd->advertising & ADVERTISED_100baseT_Full) |
| 1637 | adv |= ADVERTISE_100FULL; |
| 1638 | mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); |
| 1639 | |
| 1640 | if (np->gigabit == PHY_GIGABIT) { |
| 1641 | adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ); |
| 1642 | adv &= ~ADVERTISE_1000FULL; |
| 1643 | if (ecmd->advertising & ADVERTISED_1000baseT_Full) |
| 1644 | adv |= ADVERTISE_1000FULL; |
| 1645 | mii_rw(dev, np->phyaddr, MII_1000BT_CR, adv); |
| 1646 | } |
| 1647 | |
| 1648 | bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
| 1649 | bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); |
| 1650 | mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); |
| 1651 | |
| 1652 | } else { |
| 1653 | int adv, bmcr; |
| 1654 | |
| 1655 | np->autoneg = 0; |
| 1656 | |
| 1657 | adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); |
| 1658 | adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4); |
| 1659 | if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF) |
| 1660 | adv |= ADVERTISE_10HALF; |
| 1661 | if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL) |
| 1662 | adv |= ADVERTISE_10FULL; |
| 1663 | if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF) |
| 1664 | adv |= ADVERTISE_100HALF; |
| 1665 | if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL) |
| 1666 | adv |= ADVERTISE_100FULL; |
| 1667 | mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); |
| 1668 | np->fixed_mode = adv; |
| 1669 | |
| 1670 | if (np->gigabit == PHY_GIGABIT) { |
| 1671 | adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ); |
| 1672 | adv &= ~ADVERTISE_1000FULL; |
| 1673 | mii_rw(dev, np->phyaddr, MII_1000BT_CR, adv); |
| 1674 | } |
| 1675 | |
| 1676 | bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
| 1677 | bmcr |= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_FULLDPLX); |
| 1678 | if (adv & (ADVERTISE_10FULL|ADVERTISE_100FULL)) |
| 1679 | bmcr |= BMCR_FULLDPLX; |
| 1680 | if (adv & (ADVERTISE_100HALF|ADVERTISE_100FULL)) |
| 1681 | bmcr |= BMCR_SPEED100; |
| 1682 | mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); |
| 1683 | |
| 1684 | if (netif_running(dev)) { |
| 1685 | /* Wait a bit and then reconfigure the nic. */ |
| 1686 | udelay(10); |
| 1687 | nv_linkchange(dev); |
| 1688 | } |
| 1689 | } |
| 1690 | spin_unlock_irq(&np->lock); |
| 1691 | |
| 1692 | return 0; |
| 1693 | } |
| 1694 | |
| 1695 | static struct ethtool_ops ops = { |
| 1696 | .get_drvinfo = nv_get_drvinfo, |
| 1697 | .get_link = ethtool_op_get_link, |
| 1698 | .get_wol = nv_get_wol, |
| 1699 | .set_wol = nv_set_wol, |
| 1700 | .get_settings = nv_get_settings, |
| 1701 | .set_settings = nv_set_settings, |
| 1702 | }; |
| 1703 | |
| 1704 | static int nv_open(struct net_device *dev) |
| 1705 | { |
| 1706 | struct fe_priv *np = get_nvpriv(dev); |
| 1707 | u8 __iomem *base = get_hwbase(dev); |
| 1708 | int ret, oom, i; |
| 1709 | |
| 1710 | dprintk(KERN_DEBUG "nv_open: begin\n"); |
| 1711 | |
| 1712 | /* 1) erase previous misconfiguration */ |
| 1713 | /* 4.1-1: stop adapter: ignored, 4.3 seems to be overkill */ |
| 1714 | writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA); |
| 1715 | writel(0, base + NvRegMulticastAddrB); |
| 1716 | writel(0, base + NvRegMulticastMaskA); |
| 1717 | writel(0, base + NvRegMulticastMaskB); |
| 1718 | writel(0, base + NvRegPacketFilterFlags); |
| 1719 | |
| 1720 | writel(0, base + NvRegTransmitterControl); |
| 1721 | writel(0, base + NvRegReceiverControl); |
| 1722 | |
| 1723 | writel(0, base + NvRegAdapterControl); |
| 1724 | |
| 1725 | /* 2) initialize descriptor rings */ |
| 1726 | oom = nv_init_ring(dev); |
| 1727 | |
| 1728 | writel(0, base + NvRegLinkSpeed); |
| 1729 | writel(0, base + NvRegUnknownTransmitterReg); |
| 1730 | nv_txrx_reset(dev); |
| 1731 | writel(0, base + NvRegUnknownSetupReg6); |
| 1732 | |
| 1733 | np->in_shutdown = 0; |
| 1734 | |
| 1735 | /* 3) set mac address */ |
| 1736 | { |
| 1737 | u32 mac[2]; |
| 1738 | |
| 1739 | mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) + |
| 1740 | (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24); |
| 1741 | mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8); |
| 1742 | |
| 1743 | writel(mac[0], base + NvRegMacAddrA); |
| 1744 | writel(mac[1], base + NvRegMacAddrB); |
| 1745 | } |
| 1746 | |
| 1747 | /* 4) give hw rings */ |
| 1748 | writel((u32) np->ring_addr, base + NvRegRxRingPhysAddr); |
| 1749 | writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr); |
| 1750 | writel( ((RX_RING-1) << NVREG_RINGSZ_RXSHIFT) + ((TX_RING-1) << NVREG_RINGSZ_TXSHIFT), |
| 1751 | base + NvRegRingSizes); |
| 1752 | |
| 1753 | /* 5) continue setup */ |
| 1754 | writel(np->linkspeed, base + NvRegLinkSpeed); |
| 1755 | writel(NVREG_UNKSETUP3_VAL1, base + NvRegUnknownSetupReg3); |
| 1756 | writel(np->desc_ver, base + NvRegTxRxControl); |
| 1757 | pci_push(base); |
| 1758 | writel(NVREG_TXRXCTL_BIT1|np->desc_ver, base + NvRegTxRxControl); |
| 1759 | reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31, |
| 1760 | NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX, |
| 1761 | KERN_INFO "open: SetupReg5, Bit 31 remained off\n"); |
| 1762 | |
| 1763 | writel(0, base + NvRegUnknownSetupReg4); |
| 1764 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); |
| 1765 | writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus); |
| 1766 | |
| 1767 | /* 6) continue setup */ |
| 1768 | writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1); |
| 1769 | writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus); |
| 1770 | writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags); |
| 1771 | writel(NVREG_OFFLOAD_NORMAL, base + NvRegOffloadConfig); |
| 1772 | |
| 1773 | writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus); |
| 1774 | get_random_bytes(&i, sizeof(i)); |
| 1775 | writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed); |
| 1776 | writel(NVREG_UNKSETUP1_VAL, base + NvRegUnknownSetupReg1); |
| 1777 | writel(NVREG_UNKSETUP2_VAL, base + NvRegUnknownSetupReg2); |
| 1778 | writel(NVREG_POLL_DEFAULT, base + NvRegPollingInterval); |
| 1779 | writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6); |
| 1780 | writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING, |
| 1781 | base + NvRegAdapterControl); |
| 1782 | writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed); |
| 1783 | writel(NVREG_UNKSETUP4_VAL, base + NvRegUnknownSetupReg4); |
| 1784 | writel(NVREG_WAKEUPFLAGS_VAL, base + NvRegWakeUpFlags); |
| 1785 | |
| 1786 | i = readl(base + NvRegPowerState); |
| 1787 | if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0) |
| 1788 | writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState); |
| 1789 | |
| 1790 | pci_push(base); |
| 1791 | udelay(10); |
| 1792 | writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState); |
| 1793 | |
| 1794 | writel(0, base + NvRegIrqMask); |
| 1795 | pci_push(base); |
| 1796 | writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus); |
| 1797 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); |
| 1798 | pci_push(base); |
| 1799 | |
| 1800 | ret = request_irq(dev->irq, &nv_nic_irq, SA_SHIRQ, dev->name, dev); |
| 1801 | if (ret) |
| 1802 | goto out_drain; |
| 1803 | |
| 1804 | /* ask for interrupts */ |
| 1805 | writel(np->irqmask, base + NvRegIrqMask); |
| 1806 | |
| 1807 | spin_lock_irq(&np->lock); |
| 1808 | writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA); |
| 1809 | writel(0, base + NvRegMulticastAddrB); |
| 1810 | writel(0, base + NvRegMulticastMaskA); |
| 1811 | writel(0, base + NvRegMulticastMaskB); |
| 1812 | writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags); |
| 1813 | /* One manual link speed update: Interrupts are enabled, future link |
| 1814 | * speed changes cause interrupts and are handled by nv_link_irq(). |
| 1815 | */ |
| 1816 | { |
| 1817 | u32 miistat; |
| 1818 | miistat = readl(base + NvRegMIIStatus); |
| 1819 | writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus); |
| 1820 | dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat); |
| 1821 | } |
| 1822 | ret = nv_update_linkspeed(dev); |
| 1823 | nv_start_rx(dev); |
| 1824 | nv_start_tx(dev); |
| 1825 | netif_start_queue(dev); |
| 1826 | if (ret) { |
| 1827 | netif_carrier_on(dev); |
| 1828 | } else { |
| 1829 | printk("%s: no link during initialization.\n", dev->name); |
| 1830 | netif_carrier_off(dev); |
| 1831 | } |
| 1832 | if (oom) |
| 1833 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); |
| 1834 | spin_unlock_irq(&np->lock); |
| 1835 | |
| 1836 | return 0; |
| 1837 | out_drain: |
| 1838 | drain_ring(dev); |
| 1839 | return ret; |
| 1840 | } |
| 1841 | |
| 1842 | static int nv_close(struct net_device *dev) |
| 1843 | { |
| 1844 | struct fe_priv *np = get_nvpriv(dev); |
| 1845 | u8 __iomem *base; |
| 1846 | |
| 1847 | spin_lock_irq(&np->lock); |
| 1848 | np->in_shutdown = 1; |
| 1849 | spin_unlock_irq(&np->lock); |
| 1850 | synchronize_irq(dev->irq); |
| 1851 | |
| 1852 | del_timer_sync(&np->oom_kick); |
| 1853 | del_timer_sync(&np->nic_poll); |
| 1854 | |
| 1855 | netif_stop_queue(dev); |
| 1856 | spin_lock_irq(&np->lock); |
| 1857 | nv_stop_tx(dev); |
| 1858 | nv_stop_rx(dev); |
| 1859 | nv_txrx_reset(dev); |
| 1860 | |
| 1861 | /* disable interrupts on the nic or we will lock up */ |
| 1862 | base = get_hwbase(dev); |
| 1863 | writel(0, base + NvRegIrqMask); |
| 1864 | pci_push(base); |
| 1865 | dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name); |
| 1866 | |
| 1867 | spin_unlock_irq(&np->lock); |
| 1868 | |
| 1869 | free_irq(dev->irq, dev); |
| 1870 | |
| 1871 | drain_ring(dev); |
| 1872 | |
| 1873 | if (np->wolenabled) |
| 1874 | nv_start_rx(dev); |
| 1875 | |
| 1876 | /* FIXME: power down nic */ |
| 1877 | |
| 1878 | return 0; |
| 1879 | } |
| 1880 | |
| 1881 | static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id) |
| 1882 | { |
| 1883 | struct net_device *dev; |
| 1884 | struct fe_priv *np; |
| 1885 | unsigned long addr; |
| 1886 | u8 __iomem *base; |
| 1887 | int err, i; |
| 1888 | |
| 1889 | dev = alloc_etherdev(sizeof(struct fe_priv)); |
| 1890 | err = -ENOMEM; |
| 1891 | if (!dev) |
| 1892 | goto out; |
| 1893 | |
| 1894 | np = get_nvpriv(dev); |
| 1895 | np->pci_dev = pci_dev; |
| 1896 | spin_lock_init(&np->lock); |
| 1897 | SET_MODULE_OWNER(dev); |
| 1898 | SET_NETDEV_DEV(dev, &pci_dev->dev); |
| 1899 | |
| 1900 | init_timer(&np->oom_kick); |
| 1901 | np->oom_kick.data = (unsigned long) dev; |
| 1902 | np->oom_kick.function = &nv_do_rx_refill; /* timer handler */ |
| 1903 | init_timer(&np->nic_poll); |
| 1904 | np->nic_poll.data = (unsigned long) dev; |
| 1905 | np->nic_poll.function = &nv_do_nic_poll; /* timer handler */ |
| 1906 | |
| 1907 | err = pci_enable_device(pci_dev); |
| 1908 | if (err) { |
| 1909 | printk(KERN_INFO "forcedeth: pci_enable_dev failed (%d) for device %s\n", |
| 1910 | err, pci_name(pci_dev)); |
| 1911 | goto out_free; |
| 1912 | } |
| 1913 | |
| 1914 | pci_set_master(pci_dev); |
| 1915 | |
| 1916 | err = pci_request_regions(pci_dev, DRV_NAME); |
| 1917 | if (err < 0) |
| 1918 | goto out_disable; |
| 1919 | |
| 1920 | err = -EINVAL; |
| 1921 | addr = 0; |
| 1922 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { |
| 1923 | dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n", |
| 1924 | pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i), |
| 1925 | pci_resource_len(pci_dev, i), |
| 1926 | pci_resource_flags(pci_dev, i)); |
| 1927 | if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM && |
| 1928 | pci_resource_len(pci_dev, i) >= NV_PCI_REGSZ) { |
| 1929 | addr = pci_resource_start(pci_dev, i); |
| 1930 | break; |
| 1931 | } |
| 1932 | } |
| 1933 | if (i == DEVICE_COUNT_RESOURCE) { |
| 1934 | printk(KERN_INFO "forcedeth: Couldn't find register window for device %s.\n", |
| 1935 | pci_name(pci_dev)); |
| 1936 | goto out_relreg; |
| 1937 | } |
| 1938 | |
| 1939 | /* handle different descriptor versions */ |
| 1940 | if (pci_dev->device == PCI_DEVICE_ID_NVIDIA_NVENET_1 || |
| 1941 | pci_dev->device == PCI_DEVICE_ID_NVIDIA_NVENET_2 || |
| 1942 | pci_dev->device == PCI_DEVICE_ID_NVIDIA_NVENET_3) |
| 1943 | np->desc_ver = DESC_VER_1; |
| 1944 | else |
| 1945 | np->desc_ver = DESC_VER_2; |
| 1946 | |
| 1947 | err = -ENOMEM; |
| 1948 | np->base = ioremap(addr, NV_PCI_REGSZ); |
| 1949 | if (!np->base) |
| 1950 | goto out_relreg; |
| 1951 | dev->base_addr = (unsigned long)np->base; |
| 1952 | dev->irq = pci_dev->irq; |
| 1953 | np->rx_ring = pci_alloc_consistent(pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING), |
| 1954 | &np->ring_addr); |
| 1955 | if (!np->rx_ring) |
| 1956 | goto out_unmap; |
| 1957 | np->tx_ring = &np->rx_ring[RX_RING]; |
| 1958 | |
| 1959 | dev->open = nv_open; |
| 1960 | dev->stop = nv_close; |
| 1961 | dev->hard_start_xmit = nv_start_xmit; |
| 1962 | dev->get_stats = nv_get_stats; |
| 1963 | dev->change_mtu = nv_change_mtu; |
| 1964 | dev->set_multicast_list = nv_set_multicast; |
| 1965 | SET_ETHTOOL_OPS(dev, &ops); |
| 1966 | dev->tx_timeout = nv_tx_timeout; |
| 1967 | dev->watchdog_timeo = NV_WATCHDOG_TIMEO; |
| 1968 | |
| 1969 | pci_set_drvdata(pci_dev, dev); |
| 1970 | |
| 1971 | /* read the mac address */ |
| 1972 | base = get_hwbase(dev); |
| 1973 | np->orig_mac[0] = readl(base + NvRegMacAddrA); |
| 1974 | np->orig_mac[1] = readl(base + NvRegMacAddrB); |
| 1975 | |
| 1976 | dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff; |
| 1977 | dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff; |
| 1978 | dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff; |
| 1979 | dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff; |
| 1980 | dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff; |
| 1981 | dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff; |
| 1982 | |
| 1983 | if (!is_valid_ether_addr(dev->dev_addr)) { |
| 1984 | /* |
| 1985 | * Bad mac address. At least one bios sets the mac address |
| 1986 | * to 01:23:45:67:89:ab |
| 1987 | */ |
| 1988 | printk(KERN_ERR "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n", |
| 1989 | pci_name(pci_dev), |
| 1990 | dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2], |
| 1991 | dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]); |
| 1992 | printk(KERN_ERR "Please complain to your hardware vendor. Switching to a random MAC.\n"); |
| 1993 | dev->dev_addr[0] = 0x00; |
| 1994 | dev->dev_addr[1] = 0x00; |
| 1995 | dev->dev_addr[2] = 0x6c; |
| 1996 | get_random_bytes(&dev->dev_addr[3], 3); |
| 1997 | } |
| 1998 | |
| 1999 | dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev), |
| 2000 | dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2], |
| 2001 | dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]); |
| 2002 | |
| 2003 | /* disable WOL */ |
| 2004 | writel(0, base + NvRegWakeUpFlags); |
| 2005 | np->wolenabled = 0; |
| 2006 | |
| 2007 | if (np->desc_ver == DESC_VER_1) { |
| 2008 | np->tx_flags = NV_TX_LASTPACKET|NV_TX_VALID; |
| 2009 | if (id->driver_data & DEV_NEED_LASTPACKET1) |
| 2010 | np->tx_flags |= NV_TX_LASTPACKET1; |
| 2011 | } else { |
| 2012 | np->tx_flags = NV_TX2_LASTPACKET|NV_TX2_VALID; |
| 2013 | if (id->driver_data & DEV_NEED_LASTPACKET1) |
| 2014 | np->tx_flags |= NV_TX2_LASTPACKET1; |
| 2015 | } |
| 2016 | if (id->driver_data & DEV_IRQMASK_1) |
| 2017 | np->irqmask = NVREG_IRQMASK_WANTED_1; |
| 2018 | if (id->driver_data & DEV_IRQMASK_2) |
| 2019 | np->irqmask = NVREG_IRQMASK_WANTED_2; |
| 2020 | if (id->driver_data & DEV_NEED_TIMERIRQ) |
| 2021 | np->irqmask |= NVREG_IRQ_TIMER; |
| 2022 | if (id->driver_data & DEV_NEED_LINKTIMER) { |
| 2023 | dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev)); |
| 2024 | np->need_linktimer = 1; |
| 2025 | np->link_timeout = jiffies + LINK_TIMEOUT; |
| 2026 | } else { |
| 2027 | dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev)); |
| 2028 | np->need_linktimer = 0; |
| 2029 | } |
| 2030 | |
| 2031 | /* find a suitable phy */ |
| 2032 | for (i = 1; i < 32; i++) { |
| 2033 | int id1, id2; |
| 2034 | |
| 2035 | spin_lock_irq(&np->lock); |
| 2036 | id1 = mii_rw(dev, i, MII_PHYSID1, MII_READ); |
| 2037 | spin_unlock_irq(&np->lock); |
| 2038 | if (id1 < 0 || id1 == 0xffff) |
| 2039 | continue; |
| 2040 | spin_lock_irq(&np->lock); |
| 2041 | id2 = mii_rw(dev, i, MII_PHYSID2, MII_READ); |
| 2042 | spin_unlock_irq(&np->lock); |
| 2043 | if (id2 < 0 || id2 == 0xffff) |
| 2044 | continue; |
| 2045 | |
| 2046 | id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT; |
| 2047 | id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT; |
| 2048 | dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n", |
| 2049 | pci_name(pci_dev), id1, id2, i); |
| 2050 | np->phyaddr = i; |
| 2051 | np->phy_oui = id1 | id2; |
| 2052 | break; |
| 2053 | } |
| 2054 | if (i == 32) { |
| 2055 | /* PHY in isolate mode? No phy attached and user wants to |
| 2056 | * test loopback? Very odd, but can be correct. |
| 2057 | */ |
| 2058 | printk(KERN_INFO "%s: open: Could not find a valid PHY.\n", |
| 2059 | pci_name(pci_dev)); |
| 2060 | } |
| 2061 | |
| 2062 | if (i != 32) { |
| 2063 | /* reset it */ |
| 2064 | phy_init(dev); |
| 2065 | } |
| 2066 | |
| 2067 | /* set default link speed settings */ |
| 2068 | np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
| 2069 | np->duplex = 0; |
| 2070 | np->autoneg = 1; |
| 2071 | |
| 2072 | err = register_netdev(dev); |
| 2073 | if (err) { |
| 2074 | printk(KERN_INFO "forcedeth: unable to register netdev: %d\n", err); |
| 2075 | goto out_freering; |
| 2076 | } |
| 2077 | printk(KERN_INFO "%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n", |
| 2078 | dev->name, pci_dev->subsystem_vendor, pci_dev->subsystem_device, |
| 2079 | pci_name(pci_dev)); |
| 2080 | |
| 2081 | return 0; |
| 2082 | |
| 2083 | out_freering: |
| 2084 | pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING), |
| 2085 | np->rx_ring, np->ring_addr); |
| 2086 | pci_set_drvdata(pci_dev, NULL); |
| 2087 | out_unmap: |
| 2088 | iounmap(get_hwbase(dev)); |
| 2089 | out_relreg: |
| 2090 | pci_release_regions(pci_dev); |
| 2091 | out_disable: |
| 2092 | pci_disable_device(pci_dev); |
| 2093 | out_free: |
| 2094 | free_netdev(dev); |
| 2095 | out: |
| 2096 | return err; |
| 2097 | } |
| 2098 | |
| 2099 | static void __devexit nv_remove(struct pci_dev *pci_dev) |
| 2100 | { |
| 2101 | struct net_device *dev = pci_get_drvdata(pci_dev); |
| 2102 | struct fe_priv *np = get_nvpriv(dev); |
| 2103 | u8 __iomem *base = get_hwbase(dev); |
| 2104 | |
| 2105 | unregister_netdev(dev); |
| 2106 | |
| 2107 | /* special op: write back the misordered MAC address - otherwise |
| 2108 | * the next nv_probe would see a wrong address. |
| 2109 | */ |
| 2110 | writel(np->orig_mac[0], base + NvRegMacAddrA); |
| 2111 | writel(np->orig_mac[1], base + NvRegMacAddrB); |
| 2112 | |
| 2113 | /* free all structures */ |
| 2114 | pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING), np->rx_ring, np->ring_addr); |
| 2115 | iounmap(get_hwbase(dev)); |
| 2116 | pci_release_regions(pci_dev); |
| 2117 | pci_disable_device(pci_dev); |
| 2118 | free_netdev(dev); |
| 2119 | pci_set_drvdata(pci_dev, NULL); |
| 2120 | } |
| 2121 | |
| 2122 | static struct pci_device_id pci_tbl[] = { |
| 2123 | { /* nForce Ethernet Controller */ |
| 2124 | .vendor = PCI_VENDOR_ID_NVIDIA, |
| 2125 | .device = PCI_DEVICE_ID_NVIDIA_NVENET_1, |
| 2126 | .subvendor = PCI_ANY_ID, |
| 2127 | .subdevice = PCI_ANY_ID, |
| 2128 | .driver_data = DEV_IRQMASK_1|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER, |
| 2129 | }, |
| 2130 | { /* nForce2 Ethernet Controller */ |
| 2131 | .vendor = PCI_VENDOR_ID_NVIDIA, |
| 2132 | .device = PCI_DEVICE_ID_NVIDIA_NVENET_2, |
| 2133 | .subvendor = PCI_ANY_ID, |
| 2134 | .subdevice = PCI_ANY_ID, |
| 2135 | .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER, |
| 2136 | }, |
| 2137 | { /* nForce3 Ethernet Controller */ |
| 2138 | .vendor = PCI_VENDOR_ID_NVIDIA, |
| 2139 | .device = PCI_DEVICE_ID_NVIDIA_NVENET_3, |
| 2140 | .subvendor = PCI_ANY_ID, |
| 2141 | .subdevice = PCI_ANY_ID, |
| 2142 | .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER, |
| 2143 | }, |
| 2144 | { /* nForce3 Ethernet Controller */ |
| 2145 | .vendor = PCI_VENDOR_ID_NVIDIA, |
| 2146 | .device = PCI_DEVICE_ID_NVIDIA_NVENET_4, |
| 2147 | .subvendor = PCI_ANY_ID, |
| 2148 | .subdevice = PCI_ANY_ID, |
| 2149 | .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ, |
| 2150 | }, |
| 2151 | { /* nForce3 Ethernet Controller */ |
| 2152 | .vendor = PCI_VENDOR_ID_NVIDIA, |
| 2153 | .device = PCI_DEVICE_ID_NVIDIA_NVENET_5, |
| 2154 | .subvendor = PCI_ANY_ID, |
| 2155 | .subdevice = PCI_ANY_ID, |
| 2156 | .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ, |
| 2157 | }, |
| 2158 | { /* nForce3 Ethernet Controller */ |
| 2159 | .vendor = PCI_VENDOR_ID_NVIDIA, |
| 2160 | .device = PCI_DEVICE_ID_NVIDIA_NVENET_6, |
| 2161 | .subvendor = PCI_ANY_ID, |
| 2162 | .subdevice = PCI_ANY_ID, |
| 2163 | .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ, |
| 2164 | }, |
| 2165 | { /* nForce3 Ethernet Controller */ |
| 2166 | .vendor = PCI_VENDOR_ID_NVIDIA, |
| 2167 | .device = PCI_DEVICE_ID_NVIDIA_NVENET_7, |
| 2168 | .subvendor = PCI_ANY_ID, |
| 2169 | .subdevice = PCI_ANY_ID, |
| 2170 | .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ, |
| 2171 | }, |
| 2172 | { /* CK804 Ethernet Controller */ |
| 2173 | .vendor = PCI_VENDOR_ID_NVIDIA, |
| 2174 | .device = PCI_DEVICE_ID_NVIDIA_NVENET_8, |
| 2175 | .subvendor = PCI_ANY_ID, |
| 2176 | .subdevice = PCI_ANY_ID, |
| 2177 | .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ, |
| 2178 | }, |
| 2179 | { /* CK804 Ethernet Controller */ |
| 2180 | .vendor = PCI_VENDOR_ID_NVIDIA, |
| 2181 | .device = PCI_DEVICE_ID_NVIDIA_NVENET_9, |
| 2182 | .subvendor = PCI_ANY_ID, |
| 2183 | .subdevice = PCI_ANY_ID, |
| 2184 | .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ, |
| 2185 | }, |
| 2186 | { /* MCP04 Ethernet Controller */ |
| 2187 | .vendor = PCI_VENDOR_ID_NVIDIA, |
| 2188 | .device = PCI_DEVICE_ID_NVIDIA_NVENET_10, |
| 2189 | .subvendor = PCI_ANY_ID, |
| 2190 | .subdevice = PCI_ANY_ID, |
| 2191 | .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ, |
| 2192 | }, |
| 2193 | { /* MCP04 Ethernet Controller */ |
| 2194 | .vendor = PCI_VENDOR_ID_NVIDIA, |
| 2195 | .device = PCI_DEVICE_ID_NVIDIA_NVENET_11, |
| 2196 | .subvendor = PCI_ANY_ID, |
| 2197 | .subdevice = PCI_ANY_ID, |
| 2198 | .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ, |
| 2199 | }, |
| 2200 | {0,}, |
| 2201 | }; |
| 2202 | |
| 2203 | static struct pci_driver driver = { |
| 2204 | .name = "forcedeth", |
| 2205 | .id_table = pci_tbl, |
| 2206 | .probe = nv_probe, |
| 2207 | .remove = __devexit_p(nv_remove), |
| 2208 | }; |
| 2209 | |
| 2210 | |
| 2211 | static int __init init_nic(void) |
| 2212 | { |
| 2213 | printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION); |
| 2214 | return pci_module_init(&driver); |
| 2215 | } |
| 2216 | |
| 2217 | static void __exit exit_nic(void) |
| 2218 | { |
| 2219 | pci_unregister_driver(&driver); |
| 2220 | } |
| 2221 | |
| 2222 | module_param(max_interrupt_work, int, 0); |
| 2223 | MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt"); |
| 2224 | |
| 2225 | MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>"); |
| 2226 | MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver"); |
| 2227 | MODULE_LICENSE("GPL"); |
| 2228 | |
| 2229 | MODULE_DEVICE_TABLE(pci, pci_tbl); |
| 2230 | |
| 2231 | module_init(init_nic); |
| 2232 | module_exit(exit_nic); |