Quick compiler: Single .so for all targets

With this CL, all targets can be built into a single .so (but
we're not yet doing so - the compiler driver needs to be reworked).

A new Codgen class is introduced (see compiler/codegen/codegen.h),
along with target-specific sub-classes ArmCodegen, MipsCodegens and
X86Codegen (see compiler/codegen/*/codegen_[Arm|Mips|X86].h).

Additional minor code, comment and format refactoring.  Some source
files combined, temporary header files deleted and a few file
renames to better identify their function.

Next up is combining the Quick and Portable .so files.

Note: building all targets into libdvm-compiler.so increases its
size by 140K bytes.  I'm inclined to not bother introducing conditional
compilation to limit code to the specific target - the added build and
testing complexity doesn't doesn't seem worth such a modest size savings.

Change-Id: Id9c5b4502ad6b77cdb31f71d3126f51a4f2e9dfe
diff --git a/src/compiler/ralloc.cc b/src/compiler/ralloc.cc
index c2e663e..8813193 100644
--- a/src/compiler/ralloc.cc
+++ b/src/compiler/ralloc.cc
@@ -364,18 +364,19 @@
 
 static const char* storage_name[] = {" Frame ", "PhysReg", " Spill "};
 
-static void DumpRegLocTable(RegLocation* table, int count)
+static void DumpRegLocTable(CompilationUnit* cu, RegLocation* table, int count)
 {
+  Codegen* cg = cu->cg.get();
   for (int i = 0; i < count; i++) {
     LOG(INFO) << StringPrintf("Loc[%02d] : %s, %c %c %c %c %c %c%d %c%d S%d",
         table[i].orig_sreg, storage_name[table[i].location],
         table[i].wide ? 'W' : 'N', table[i].defined ? 'D' : 'U',
         table[i].fp ? 'F' : table[i].ref ? 'R' :'C',
         table[i].high_word ? 'H' : 'L', table[i].home ? 'h' : 't',
-        IsFpReg(table[i].low_reg) ? 's' : 'r',
-        table[i].low_reg & FpRegMask(),
-        IsFpReg(table[i].high_reg) ? 's' : 'r',
-        table[i].high_reg & FpRegMask(), table[i].s_reg_low);
+        cg->IsFpReg(table[i].low_reg) ? 's' : 'r',
+        table[i].low_reg & cg->FpRegMask(),
+        cg->IsFpReg(table[i].high_reg) ? 's' : 'r',
+        table[i].high_reg & cg->FpRegMask(), table[i].s_reg_low);
   }
 }
 
@@ -515,7 +516,7 @@
 
   if (cu->verbose && !(cu->disable_opt & (1 << kPromoteRegs))) {
     LOG(INFO) << "After Promotion";
-    DumpRegLocTable(cu->reg_location, cu->num_ssa_regs);
+    DumpRegLocTable(cu, cu->reg_location, cu->num_ssa_regs);
   }
 
   /* Set the frame size */