commit a3fe7422d7ce8bfb01f95decef45f91a44d39264
author Zheng Xu <zheng.xu@arm.com> Wed Jul 09 14:03:15 2014 +0800
committer Zheng Xu <zheng.xu@arm.com> Thu Jul 10 08:47:16 2014 +0800
tree c95d83be9696bc14c13d3b4ff9332bcde10a5961
parent bcb3b29095817ce8987d8310d4db87271f5114ad

AArch64: Fix and enable reverseBytes intrinsic.

There is no revsh on arm64, use rev16 and sxth instead.

Change-Id: I5f9879352f0ad76b386c82cbf476894af888a64c

compiler/dex/quick/arm64/utility_arm64.cc

diff --git a/compiler/dex/quick/arm64/utility_arm64.cc b/compiler/dex/quick/arm64/utility_arm64.cc
index 22a4ec4..b2f5142 100644
--- a/compiler/dex/quick/arm64/utility_arm64.cc
+++ b/compiler/dex/quick/arm64/utility_arm64.cc
@@ -488,7 +488,9 @@
       break;
     case kOpRevsh:
       // Binary, but rm is encoded twice.
-      return NewLIR2(kA64Rev162rr | wide, r_dest_src1.GetReg(), r_src2.GetReg());
+      NewLIR2(kA64Rev162rr | wide, r_dest_src1.GetReg(), r_src2.GetReg());
+      // "sxth r1, r2" is "sbfm r1, r2, #0, #15"
+      return NewLIR4(kA64Sbfm4rrdd | wide, r_dest_src1.GetReg(), r_dest_src1.GetReg(), 0, 15);
       break;
     case kOp2Byte:
       DCHECK_EQ(shift, ENCODE_NO_SHIFT);

compiler/dex/quick/gen_invoke.cc

diff --git a/compiler/dex/quick/gen_invoke.cc b/compiler/dex/quick/gen_invoke.cc
index 55b68e6..b821fb3 100755
--- a/compiler/dex/quick/gen_invoke.cc
+++ b/compiler/dex/quick/gen_invoke.cc
@@ -1385,8 +1385,8 @@
 }
 
 bool Mir2Lir::GenInlinedReverseBytes(CallInfo* info, OpSize size) {
-  if (cu_->instruction_set == kMips || cu_->instruction_set == kArm64) {
-    // TODO - add Mips implementation; Enable Arm64.
+  if (cu_->instruction_set == kMips) {
+    // TODO - add Mips implementation.
     return false;
   }
   RegLocation rl_src_i = info->args[0];