Quick compiler: restore optimizations
This CL re-enables optizations on the Quick compile path.
Notes:
o Although all optimization are enabled, several are now useless
because of llvm and bitcode constraints:
- Large method de-optimization (i.e. - skipping expensive dataflow
analysis) can't be done because we have to do the analysis to
produce a CFG that makes the bitcode verifier happy.
- Small method pattern matching isn't applicable w/ bitcode (though
I can probably do something similar in the Quick backend, but
looking for bitcode instead of dex patterns).
- Branch fusing doesn't translate to bitcode.
- Bitcode generation has de-optimized code layout. We'll try to
repair the damage in a subsequent CL.
o There is an ugly workaround related to the way we're loading and
unloading the compiler .so containing llvm. [See comment in compiler.cc]
o We're still running single-threaded - need to add the magic to allow
multi-threaded use of llvm.
o With the CL, the phone boots, all target tests pass and all cts VM
tests pass (except those being dealt with via a verifier change).
o Compile time is pretty bad - when flashing it's best to follow
with an adb sync to avoid on-device compilation of system apps.
Change-Id: I1c98f9e64aefbcbd24b957c71544c28450eb2023
diff --git a/src/compiler/codegen/RallocUtil.cc b/src/compiler/codegen/RallocUtil.cc
index 9d1878a..8fa110a 100644
--- a/src/compiler/codegen/RallocUtil.cc
+++ b/src/compiler/codegen/RallocUtil.cc
@@ -161,6 +161,20 @@
}
}
+void oatRecordCorePromotion(CompilationUnit* cUnit, int reg, int sReg)
+{
+ int pMapIdx = SRegToPMap(cUnit, sReg);
+ int vReg = SRegToVReg(cUnit, sReg);
+ oatGetRegInfo(cUnit, reg)->inUse = true;
+ cUnit->coreSpillMask |= (1 << reg);
+ // Include reg for later sort
+ cUnit->coreVmapTable.push_back(reg << VREG_NUM_WIDTH |
+ (vReg & ((1 << VREG_NUM_WIDTH) - 1)));
+ cUnit->numCoreSpills++;
+ cUnit->promotionMap[pMapIdx].coreLocation = kLocPhysReg;
+ cUnit->promotionMap[pMapIdx].coreReg = reg;
+}
+
/* Reserve a callee-save register. Return -1 if none available */
extern int oatAllocPreservedCoreReg(CompilationUnit* cUnit, int sReg)
{
@@ -168,21 +182,24 @@
RegisterInfo* coreRegs = cUnit->regPool->coreRegs;
for (int i = 0; i < cUnit->regPool->numCoreRegs; i++) {
if (!coreRegs[i].isTemp && !coreRegs[i].inUse) {
- int vReg = SRegToVReg(cUnit, sReg);
- int pMapIdx = SRegToPMap(cUnit, sReg);
res = coreRegs[i].reg;
- coreRegs[i].inUse = true;
- cUnit->coreSpillMask |= (1 << res);
- cUnit->coreVmapTable.push_back(vReg);
- cUnit->numCoreSpills++;
- cUnit->promotionMap[pMapIdx].coreLocation = kLocPhysReg;
- cUnit->promotionMap[pMapIdx].coreReg = res;
+ oatRecordCorePromotion(cUnit, res, sReg);
break;
}
}
return res;
}
+void oatRecordFpPromotion(CompilationUnit* cUnit, int reg, int sReg)
+{
+ int pMapIdx = SRegToPMap(cUnit, sReg);
+ int vReg = SRegToVReg(cUnit, sReg);
+ oatGetRegInfo(cUnit, reg)->inUse = true;
+ oatMarkPreservedSingle(cUnit, vReg, reg);
+ cUnit->promotionMap[pMapIdx].fpLocation = kLocPhysReg;
+ cUnit->promotionMap[pMapIdx].fpReg = reg;
+}
+
/*
* Reserve a callee-save fp single register. Try to fullfill request for
* even/odd allocation, but go ahead and allocate anything if not
@@ -195,13 +212,8 @@
for (int i = 0; i < cUnit->regPool->numFPRegs; i++) {
if (!FPRegs[i].isTemp && !FPRegs[i].inUse &&
((FPRegs[i].reg & 0x1) == 0) == even) {
- int vReg = SRegToVReg(cUnit, sReg);
- int pMapIdx = SRegToPMap(cUnit, sReg);
res = FPRegs[i].reg;
- FPRegs[i].inUse = true;
- oatMarkPreservedSingle(cUnit, vReg, res);
- cUnit->promotionMap[pMapIdx].fpLocation = kLocPhysReg;
- cUnit->promotionMap[pMapIdx].fpReg = res;
+ oatRecordFpPromotion(cUnit, res, sReg);
break;
}
}
@@ -1237,6 +1249,9 @@
}
}
}
+ if (cUnit->printMe) {
+ oatDumpPromotionMap(cUnit);
+ }
}
/* Returns sp-relative offset in bytes for a VReg */