Fixes for x86 compiler optimizations.
x86 works with all but a few optimizations turned on, and the broken
ones are still disabled for now. This change includes:
- Flagging of opcodes to incidate register use and def. Also, made
flagging more complete for loads/stores and set/use ccodes.
- Fixes to load store elimination, though it still doesn't work yet.
- Prevent double values that are loaded or stored from losing their
FP_DOUBLE flag. Later optimizations use this sizing.
- Renumbering of DOUBLE registers so they alias with FP regs when
masked.
- Add support in the disassembler to recognize shifts.
Change-Id: I758cdce418409fdd84206ce295005d5c9ab635f8
diff --git a/src/compiler/codegen/CodegenUtil.cc b/src/compiler/codegen/CodegenUtil.cc
index c189eb2..428b443 100644
--- a/src/compiler/codegen/CodegenUtil.cc
+++ b/src/compiler/codegen/CodegenUtil.cc
@@ -76,10 +76,17 @@
int shift;
int regId = reg & 0x1f;
+#if defined(TARGET_X86)
+ /*
+ * Double registers in x86 are just a single FP register
+ */
+ seed = 1;
+#else
/*
* Each double register is equal to a pair of single-precision FP registers
*/
seed = DOUBLEREG(reg) ? 3 : 1;
+#endif
/* FP register starts at bit position 16 */
shift = FPREG(reg) ? kFPReg0 : 0;
/* Expand the double register id into single offset */
@@ -140,6 +147,16 @@
setupRegMask(&lir->defMask, lir->operands[1]);
}
+#if defined(TARGET_X86)
+ if (flags & REG_DEFA) {
+ setupRegMask(&lir->defMask, rAX);
+ }
+
+ if (flags & REG_DEFD) {
+ setupRegMask(&lir->defMask, rDX);
+ }
+#endif
+
if (flags & REG_DEF_SP) {
lir->defMask |= ENCODE_REG_SP;
}
@@ -150,6 +167,7 @@
}
#endif
+#if defined(TARGET_ARM)
if (flags & REG_DEF_LIST0) {
lir->defMask |= ENCODE_REG_LIST(lir->operands[0]);
}
@@ -158,7 +176,6 @@
lir->defMask |= ENCODE_REG_LIST(lir->operands[1]);
}
-#if defined(TARGET_ARM)
if (flags & REG_DEF_FPCS_LIST0) {
lir->defMask |= ENCODE_REG_FPCS_LIST(lir->operands[0]);
}
@@ -191,6 +208,20 @@
}
}
+#if defined(TARGET_X86)
+ if (flags & REG_USEA) {
+ setupRegMask(&lir->useMask, rAX);
+ }
+
+ if (flags & REG_USEC) {
+ setupRegMask(&lir->useMask, rCX);
+ }
+
+ if (flags & REG_USED) {
+ setupRegMask(&lir->useMask, rDX);
+ }
+#endif
+
#if defined(TARGET_ARM)
if (flags & REG_USE_PC) {
lir->useMask |= ENCODE_REG_PC;
@@ -201,6 +232,7 @@
lir->useMask |= ENCODE_REG_SP;
}
+#if defined(TARGET_ARM)
if (flags & REG_USE_LIST0) {
lir->useMask |= ENCODE_REG_LIST(lir->operands[0]);
}
@@ -209,7 +241,6 @@
lir->useMask |= ENCODE_REG_LIST(lir->operands[1]);
}
-#if defined(TARGET_ARM)
if (flags & REG_USE_FPCS_LIST0) {
lir->useMask |= ENCODE_REG_FPCS_LIST(lir->operands[0]);
}