Quick compiler: more refactoring

Focus on header file cleanup here.  Note: target_list.h
is transitional, and upcoming CLs will do additional header
file reorganization.

Change-Id: If86e1a8c1c43305762fe37b157a9d3c17d911ea7
diff --git a/src/compiler/compiler_ir.h b/src/compiler/compiler_ir.h
index 6c6442d..f73fe92 100644
--- a/src/compiler/compiler_ir.h
+++ b/src/compiler/compiler_ir.h
@@ -18,8 +18,8 @@
 #define ART_SRC_COMPILER_COMPILER_IR_H_
 
 #include <vector>
-
-#include "codegen/optimizer.h"
+#include "dex_instruction.h"
+#include "compiler.h"
 #include "compiler_utility.h"
 #include "oat_compilation_unit.h"
 #include "safe_map.h"
@@ -38,6 +38,10 @@
 // Minimum field size to contain Dalvik vReg number
 #define VREG_NUM_WIDTH 16
 
+struct ArenaBitVector;
+struct LIR;
+class LLVMInfo;
+
 enum RegisterClass {
   kCoreReg,
   kFPReg,
@@ -73,9 +77,9 @@
 
 struct PromotionMap {
   RegLocationType coreLocation:3;
-  u1 coreReg;
+  uint8_t coreReg;
   RegLocationType fpLocation:3;
-  u1 fpReg;
+  uint8_t fpReg;
   bool firstInPair;
 };
 
@@ -89,8 +93,8 @@
   unsigned ref:1;       // Something GC cares about
   unsigned highWord:1;  // High word of pair?
   unsigned home:1;      // Does this represent the home location?
-  u1 lowReg;            // First physical register
-  u1 highReg;           // 2nd physical register (if wide)
+  uint8_t lowReg;            // First physical register
+  uint8_t highReg;           // 2nd physical register (if wide)
   int32_t sRegLow;      // SSA name for low Dalvik word
   int32_t origSReg;     // TODO: remove after Bitcode gen complete
                         // and consolodate usage w/ sRegLow
@@ -229,8 +233,8 @@
     unsigned int unused:25;
   } flags;
   int aliasInfo;              // For Dalvik register & litpool disambiguation
-  u8 useMask;                 // Resource mask for use
-  u8 defMask;                 // Resource mask for def
+  uint64_t useMask;           // Resource mask for use
+  uint64_t defMask;           // Resource mask for def
 };
 
 /* Shared pseudo opcodes - must be < 0 */
@@ -601,8 +605,8 @@
   int currentDalvikOffset;
   GrowableList switchTables;
   GrowableList fillArrayData;
-  const u2* insns;
-  u4 insnsSize;
+  const uint16_t* insns;
+  uint32_t insnsSize;
   bool disableDataflow; // Skip dataflow analysis if possible
   SafeMap<unsigned int, BasicBlock*> blockMap; // findBlock lookup cache
   SafeMap<unsigned int, unsigned int> blockIdMap; // Block collapse lookup cache
@@ -797,7 +801,7 @@
 
 struct SwitchTable {
   int offset;
-  const u2* table;            // Original dex table
+  const uint16_t* table;            // Original dex table
   int vaddr;                  // Dalvik offset of switch opcode
   LIR* anchor;                // Reference instruction for relative offsets
   LIR** targets;              // Array of case targets
@@ -805,7 +809,7 @@
 
 struct FillArrayData {
   int offset;
-  const u2* table;           // Original dex table
+  const uint16_t* table;           // Original dex table
   int size;
   int vaddr;                 // Dalvik offset of FILL_ARRAY_DATA opcode
 };