Major registor allocation rework - stage 1.
Direct usage of registers abstracted out.
Live values tracked locally. Redundant loads and stores suppressed.
Address of registers and register pairs unified w/ single "location" mechanism
Register types inferred using existing dataflow analysis pass.
Interim (i.e. Hack) mechanism for storing register liveness info. Rewrite TBD.
Stubbed-out code for linear scan allocation (for loop and long traces)
Moved optimistic lock check for monitor-enter/exit inline for Thumb2
Minor restructuring, renaming and general cleanup of codegen
Renaming of enums to follow coding convention
Formatting fixes introduced by the enum renaming
Rewrite of RallocUtil.c and addition of linear scan to come in stage 2.
diff --git a/vm/compiler/Dataflow.h b/vm/compiler/Dataflow.h
index 384d430..72c8b25 100644
--- a/vm/compiler/Dataflow.h
+++ b/vm/compiler/Dataflow.h
@@ -38,6 +38,9 @@
kNullNRangeCheck0,
kNullNRangeCheck1,
kNullNRangeCheck2,
+ kFPA,
+ kFPB,
+ kFPC,
} DataFlowAttributes;
#define DF_NOP 0
@@ -58,6 +61,9 @@
#define DF_NULL_N_RANGE_CHECK_0 (1 << kNullNRangeCheck0)
#define DF_NULL_N_RANGE_CHECK_1 (1 << kNullNRangeCheck1)
#define DF_NULL_N_RANGE_CHECK_2 (1 << kNullNRangeCheck2)
+#define DF_FP_A (1 << kFPA)
+#define DF_FP_B (1 << kFPB)
+#define DF_FP_C (1 << kFPC)
#define DF_HAS_USES (DF_UA | DF_UB | DF_UC | DF_UA_WIDE | \
DF_UB_WIDE | DF_UC_WIDE)
@@ -72,7 +78,7 @@
#define DF_B_IS_REG (DF_UB | DF_UB_WIDE)
#define DF_C_IS_REG (DF_UC | DF_UC_WIDE)
-extern int dvmCompilerDataFlowAttributes[MIR_OP_LAST];
+extern int dvmCompilerDataFlowAttributes[kMirOpLast];
typedef struct BasicBlockDataFlow {
BitVector *useV;
@@ -85,8 +91,10 @@
typedef struct SSARepresentation {
int numUses;
int *uses;
+ bool *fpUse;
int numDefs;
int *defs;
+ bool *fpDef;
} SSARepresentation;
typedef struct InductionVariableInfo {