Get rid of the copies of the opcode table pointers.

This inclduded fixing all the accessor functions to refer to the
global ones defined in InstrUtils.[ch] instead of taking separate
"table pointer" arguments.

This did end up adding a few more truly global references to some of
the code paths, particularly when performing dex optimization, so I
went ahead and measured the time to do a cold first-boot both before
and after the change (on real hardware). The times were identical (to
one-second granularity), so I'm reasonably comfortable making this
change.

Change-Id: I604d9f7882bad4245bb11371218d13b06c3a5375
diff --git a/vm/compiler/Frontend.c b/vm/compiler/Frontend.c
index af704af..4e5a882 100644
--- a/vm/compiler/Frontend.c
+++ b/vm/compiler/Frontend.c
@@ -34,7 +34,7 @@
     if (opcode == OP_NOP && instr != 0) {
         return 0;
     } else {
-        insnWidth = gDvm.instrInfo.widths[opcode];
+        insnWidth = dexGetInstrWidth(opcode);
         if (insnWidth < 0) {
             insnWidth = -insnWidth;
         }
@@ -205,7 +205,7 @@
 static int analyzeInlineTarget(DecodedInstruction *dalvikInsn, int attributes,
                                int offset)
 {
-    int flags = dexGetInstrFlags(gDvm.instrInfo.flags, dalvikInsn->opCode);
+    int flags = dexGetInstrFlags(dalvikInsn->opCode);
     int dalvikOpCode = dalvikInsn->opCode;
 
     if ((flags & kInstrInvoke) &&
@@ -570,8 +570,7 @@
         dvmCompilerAppendMIR(curBB, insn);
         cUnit.numInsts++;
 
-        int flags =
-            dexGetInstrFlags(gDvm.instrInfo.flags, insn->dalvikInsn.opCode);
+        int flags = dexGetInstrFlags(insn->dalvikInsn.opCode);
 
         if ((flags & kInstrInvoke) &&
             (insn->dalvikInsn.opCode != OP_INVOKE_DIRECT_EMPTY)) {
@@ -644,8 +643,7 @@
         /* Link the taken and fallthrough blocks */
         BasicBlock *searchBB;
 
-        int flags = dexGetInstrFlags(gDvm.instrInfo.flags,
-                                     lastInsn->dalvikInsn.opCode);
+        int flags = dexGetInstrFlags(lastInsn->dalvikInsn.opCode);
 
         if (flags & kInstrInvoke) {
             cUnit.hasInvoke = true;
@@ -1208,9 +1206,8 @@
                      * aligned to 4-byte boundary (alignment instruction to be
                      * inserted later.
                      */
-                    if (dexGetInstrFlags(gDvm.instrInfo.flags,
-                           curBB->lastMIRInsn->dalvikInsn.opCode) &
-                        kInstrInvoke) {
+                    if (dexGetInstrFlags(curBB->lastMIRInsn->dalvikInsn.opCode)
+                            & kInstrInvoke) {
                         newBB->isFallThroughFromInvoke = true;
                     }
 
diff --git a/vm/compiler/InlineTransformation.c b/vm/compiler/InlineTransformation.c
index f93558c..92488b1 100644
--- a/vm/compiler/InlineTransformation.c
+++ b/vm/compiler/InlineTransformation.c
@@ -85,7 +85,7 @@
     /* Now setup the Dalvik instruction with converted src/dst registers */
     newGetterMIR->dalvikInsn = getterInsn;
 
-    newGetterMIR->width = gDvm.instrInfo.widths[getterInsn.opCode];
+    newGetterMIR->width = dexGetInstrWidth(getterInsn.opCode);
 
     newGetterMIR->OptimizationFlags |= MIR_CALLEE;
 
@@ -164,7 +164,7 @@
     /* Now setup the Dalvik instruction with converted src/dst registers */
     newSetterMIR->dalvikInsn = setterInsn;
 
-    newSetterMIR->width = gDvm.instrInfo.widths[setterInsn.opCode];
+    newSetterMIR->width = dexGetInstrWidth(setterInsn.opCode);
 
     newSetterMIR->OptimizationFlags |= MIR_CALLEE;
 
@@ -296,7 +296,7 @@
             continue;
         MIR *lastMIRInsn = bb->lastMIRInsn;
         int opCode = lastMIRInsn->dalvikInsn.opCode;
-        int flags = dexGetInstrFlags(gDvm.instrInfo.flags, opCode);
+        int flags = dexGetInstrFlags(opCode);
 
         /* No invoke - continue */
         if ((flags & kInstrInvoke) == 0)
diff --git a/vm/compiler/Loop.c b/vm/compiler/Loop.c
index de05644..6492187 100644
--- a/vm/compiler/Loop.c
+++ b/vm/compiler/Loop.c
@@ -311,7 +311,7 @@
         /* Skip extended MIR instructions */
         if (dInsn->opCode > 255) continue;
 
-        int instrFlags = dexGetInstrFlags(gDvm.instrInfo.flags, dInsn->opCode);
+        int instrFlags = dexGetInstrFlags(dInsn->opCode);
 
         /* Instruction is clean */
         if ((instrFlags & kInstrCanThrow) == 0) continue;
diff --git a/vm/compiler/codegen/arm/CodegenDriver.c b/vm/compiler/codegen/arm/CodegenDriver.c
index 17c356b..8e1d9a2 100644
--- a/vm/compiler/codegen/arm/CodegenDriver.c
+++ b/vm/compiler/codegen/arm/CodegenDriver.c
@@ -1233,7 +1233,7 @@
  */
 static void genInterpSingleStep(CompilationUnit *cUnit, MIR *mir)
 {
-    int flags = dexGetInstrFlags(gDvm.instrInfo.flags, mir->dalvikInsn.opCode);
+    int flags = dexGetInstrFlags(mir->dalvikInsn.opCode);
     int flagsToCheck = kInstrCanBranch | kInstrCanSwitch | kInstrCanReturn |
                        kInstrCanThrow;
 
@@ -1283,7 +1283,7 @@
     if (isEnter) {
         /* Get dPC of next insn */
         loadConstant(cUnit, r4PC, (int)(cUnit->method->insns + mir->offset +
-                 dexGetInstrWidth(gDvm.instrInfo.widths, OP_MONITOR_ENTER)));
+                 dexGetInstrWidth(OP_MONITOR_ENTER)));
 #if defined(WITH_DEADLOCK_PREDICTION)
         genDispatchToHandler(cUnit, TEMPLATE_MONITOR_ENTER_DEBUG);
 #else
@@ -1297,7 +1297,7 @@
         ArmLIR *branchOver = genCmpImmBranch(cUnit, kArmCondNe, r0, 0);
         loadConstant(cUnit, r0,
                      (int) (cUnit->method->insns + mir->offset +
-                     dexGetInstrWidth(gDvm.instrInfo.widths, OP_MONITOR_EXIT)));
+                     dexGetInstrWidth(OP_MONITOR_EXIT)));
         genDispatchToHandler(cUnit, TEMPLATE_THROW_EXCEPTION_COMMON);
         ArmLIR *target = newLIR0(cUnit, kArmPseudoTargetLabel);
         target->defMask = ENCODE_ALL;
@@ -4097,8 +4097,7 @@
 
 
             OpCode dalvikOpCode = mir->dalvikInsn.opCode;
-            InstructionFormat dalvikFormat =
-                dexGetInstrFormat(gDvm.instrInfo.formats, dalvikOpCode);
+            InstructionFormat dalvikFormat = dexGetInstrFormat(dalvikOpCode);
             char *note;
             if (mir->OptimizationFlags & MIR_INLINED) {
                 note = " (I)";
diff --git a/vm/compiler/codegen/arm/Thumb2/Gen.c b/vm/compiler/codegen/arm/Thumb2/Gen.c
index d689160..3d689c9 100644
--- a/vm/compiler/codegen/arm/Thumb2/Gen.c
+++ b/vm/compiler/codegen/arm/Thumb2/Gen.c
@@ -225,7 +225,7 @@
 
     /* Get dPC of next insn */
     loadConstant(cUnit, r4PC, (int)(cUnit->method->insns + mir->offset +
-                 dexGetInstrWidth(gDvm.instrInfo.widths, OP_MONITOR_ENTER)));
+                 dexGetInstrWidth(OP_MONITOR_ENTER)));
     // Export PC (part 2)
     newLIR3(cUnit, kThumb2StrRRI8Predec, r3, rFP,
             sizeof(StackSaveArea) -
@@ -289,7 +289,7 @@
     ArmLIR *branchOver = genCmpImmBranch(cUnit, kArmCondNe, r0, 0);
     loadConstant(cUnit, r0,
                  (int) (cUnit->method->insns + mir->offset +
-                 dexGetInstrWidth(gDvm.instrInfo.widths, OP_MONITOR_EXIT)));
+                 dexGetInstrWidth(OP_MONITOR_EXIT)));
     genDispatchToHandler(cUnit, TEMPLATE_THROW_EXCEPTION_COMMON);
 
     // Resume here