Move the compiler into C++.
Change-Id: Idffbdb02c29e2be03a75f5a0a664603f2299504a
diff --git a/vm/compiler/Compiler.c b/vm/compiler/Compiler.cpp
similarity index 98%
rename from vm/compiler/Compiler.c
rename to vm/compiler/Compiler.cpp
index 4f2261b..b0c2e60 100644
--- a/vm/compiler/Compiler.c
+++ b/vm/compiler/Compiler.cpp
@@ -22,6 +22,9 @@
#include "interp/Jit.h"
#include "CompilerInternals.h"
+extern "C" void dvmCompilerTemplateStart(void);
+extern "C" void dmvCompilerTemplateEnd(void);
+
static inline bool workQueueLength(void)
{
return gDvmJit.compilerQueueLength;
@@ -99,8 +102,8 @@
*/
if (gDvmJit.compilerQueueLength == COMPILER_WORK_QUEUE_SIZE ||
gDvmJit.codeCacheFull == true) {
- result = false;
- goto unlockAndExit;
+ dvmUnlockMutex(&gDvmJit.compilerLock);
+ return false;
}
for (numWork = gDvmJit.compilerQueueLength,
@@ -108,8 +111,10 @@
numWork > 0;
numWork--) {
/* Already enqueued */
- if (gDvmJit.compilerWorkQueue[i++].pc == pc)
- goto unlockAndExit;
+ if (gDvmJit.compilerWorkQueue[i++].pc == pc) {
+ dvmUnlockMutex(&gDvmJit.compilerLock);
+ return true;
+ }
/* Wrap around */
if (i == COMPILER_WORK_QUEUE_SIZE)
i = 0;
@@ -134,7 +139,6 @@
cc = pthread_cond_signal(&gDvmJit.compilerQueueActivity);
assert(cc == 0);
-unlockAndExit:
dvmUnlockMutex(&gDvmJit.compilerLock);
return result;
}
@@ -160,8 +164,6 @@
bool dvmCompilerSetupCodeCache(void)
{
- extern void dvmCompilerTemplateStart(void);
- extern void dmvCompilerTemplateEnd(void);
int fd;
/* Allocate the code cache */
diff --git a/vm/compiler/Compiler.h b/vm/compiler/Compiler.h
index 384cb14..3ceb447 100644
--- a/vm/compiler/Compiler.h
+++ b/vm/compiler/Compiler.h
@@ -227,7 +227,7 @@
bool dvmCompilerClearVisitedFlag(struct CompilationUnit *cUnit,
struct BasicBlock *bb);
char *dvmCompilerGetDalvikDisassembly(const DecodedInstruction *insn,
- char *note);
+ const char *note);
char *dvmCompilerFullDisassembler(const struct CompilationUnit *cUnit,
const struct MIR *mir);
char *dvmCompilerGetSSAString(struct CompilationUnit *cUnit,
diff --git a/vm/compiler/CompilerIR.h b/vm/compiler/CompilerIR.h
index bdb69ce..bec052a 100644
--- a/vm/compiler/CompilerIR.h
+++ b/vm/compiler/CompilerIR.h
@@ -42,7 +42,7 @@
} RegLocation;
#define INVALID_SREG (-1)
-#define INVALID_REG (-1)
+#define INVALID_REG (0x3F)
typedef enum BBType {
/* For coding convenience reasons chaining cell types should appear first */
diff --git a/vm/compiler/Dataflow.c b/vm/compiler/Dataflow.cpp
similarity index 98%
rename from vm/compiler/Dataflow.c
rename to vm/compiler/Dataflow.cpp
index c3355e9..28bed68 100644
--- a/vm/compiler/Dataflow.c
+++ b/vm/compiler/Dataflow.cpp
@@ -1587,17 +1587,17 @@
* ssaToDalvikMap list to get the subscript[31..16]/dalvik_reg[15..0] mapping.
*/
char *dvmCompilerGetDalvikDisassembly(const DecodedInstruction *insn,
- char *note)
+ const char *note)
{
char buffer[256];
- int opcode = insn->opcode;
+ Opcode opcode = insn->opcode;
int dfAttributes = dvmCompilerDataFlowAttributes[opcode];
int flags;
char *ret;
buffer[0] = 0;
- if (opcode >= kMirOpFirst) {
- if (opcode == kMirOpPhi) {
+ if ((int)opcode >= (int)kMirOpFirst) {
+ if ((int)opcode == (int)kMirOpPhi) {
strcpy(buffer, "PHI");
}
else {
@@ -1658,13 +1658,13 @@
if (dfAttributes & DF_B_IS_REG) {
snprintf(buffer + strlen(buffer), 256, ", v%d", insn->vB);
}
- else if (opcode < kMirOpFirst) {
+ else if ((int)opcode < (int)kMirOpFirst) {
snprintf(buffer + strlen(buffer), 256, ", (#%d)", insn->vB);
}
if (dfAttributes & DF_C_IS_REG) {
snprintf(buffer + strlen(buffer), 256, ", v%d", insn->vC);
}
- else if (opcode < kMirOpFirst) {
+ else if ((int)opcode < (int)kMirOpFirst) {
snprintf(buffer + strlen(buffer), 256, ", (#%d)", insn->vC);
}
}
@@ -1696,6 +1696,7 @@
int dfAttributes = dvmCompilerDataFlowAttributes[opcode];
char *ret;
int length;
+ OpcodeFlags flags;
buffer[0] = 0;
if (opcode >= kMirOpFirst) {
@@ -1715,10 +1716,10 @@
}
goto done;
} else {
- strcpy(buffer, dexGetOpcodeName(opcode));
+ strcpy(buffer, dexGetOpcodeName((Opcode)opcode));
}
- int flags = dexGetFlagsFromOpcode(opcode);
+ flags = dexGetFlagsFromOpcode((Opcode)opcode);
/* For branches, decode the instructions to print out the branch targets */
if (flags & kInstrCanBranch) {
InstructionFormat dalvikFormat = dexGetFormatFromOpcode(insn->opcode);
@@ -1774,7 +1775,8 @@
}
}
if (opcode < kMirOpFirst) {
- InstructionFormat dalvikFormat = dexGetFormatFromOpcode(opcode);
+ InstructionFormat dalvikFormat =
+ dexGetFormatFromOpcode((Opcode)opcode);
switch (dalvikFormat) {
case kFmt11n: // op vA, #+B
case kFmt21s: // op vAA, #+BBBB
@@ -2196,7 +2198,7 @@
/* If the bb doesn't have a phi it cannot contain an induction variable */
if (bb->firstMIRInsn == NULL ||
- bb->firstMIRInsn->dalvikInsn.opcode != kMirOpPhi) {
+ (int)bb->firstMIRInsn->dalvikInsn.opcode != (int)kMirOpPhi) {
return false;
}
@@ -2215,7 +2217,7 @@
*/
MIR *phi;
for (phi = bb->firstMIRInsn; phi; phi = phi->next) {
- if (phi->dalvikInsn.opcode != kMirOpPhi) break;
+ if ((int)phi->dalvikInsn.opcode != (int)kMirOpPhi) break;
if (phi->ssaRep->defs[0] == mir->ssaRep->uses[0] &&
phi->ssaRep->uses[1] == mir->ssaRep->defs[0]) {
diff --git a/vm/compiler/Frontend.c b/vm/compiler/Frontend.cpp
similarity index 99%
rename from vm/compiler/Frontend.c
rename to vm/compiler/Frontend.cpp
index 1338acc..da693ea 100644
--- a/vm/compiler/Frontend.c
+++ b/vm/compiler/Frontend.cpp
@@ -23,7 +23,7 @@
static inline bool contentIsInsn(const u2 *codePtr) {
u2 instr = *codePtr;
- Opcode opcode = instr & 0xff;
+ Opcode opcode = (Opcode)(instr & 0xff);
/*
* Since the low 8-bit in metadata may look like OP_NOP, we need to check
diff --git a/vm/compiler/InlineTransformation.c b/vm/compiler/InlineTransformation.cpp
similarity index 97%
rename from vm/compiler/InlineTransformation.c
rename to vm/compiler/InlineTransformation.cpp
index 6cf2d43..387dd61 100644
--- a/vm/compiler/InlineTransformation.c
+++ b/vm/compiler/InlineTransformation.cpp
@@ -102,7 +102,7 @@
if (isPredicted) {
MIR *invokeMIRSlow = (MIR *)dvmCompilerNew(sizeof(MIR), true);
*invokeMIRSlow = *invokeMIR;
- invokeMIR->dalvikInsn.opcode = kMirOpCheckInlinePrediction;
+ invokeMIR->dalvikInsn.opcode = (Opcode)kMirOpCheckInlinePrediction;
/* Use vC to denote the first argument (ie this) */
if (!isRange) {
@@ -181,7 +181,7 @@
if (isPredicted) {
MIR *invokeMIRSlow = (MIR *)dvmCompilerNew(sizeof(MIR), true);
*invokeMIRSlow = *invokeMIR;
- invokeMIR->dalvikInsn.opcode = kMirOpCheckInlinePrediction;
+ invokeMIR->dalvikInsn.opcode = (Opcode)kMirOpCheckInlinePrediction;
/* Use vC to denote the first argument (ie this) */
if (!isRange) {
@@ -249,7 +249,7 @@
{
MIR *invokeMIRSlow = (MIR *)dvmCompilerNew(sizeof(MIR), true);
*invokeMIRSlow = *invokeMIR;
- invokeMIR->dalvikInsn.opcode = kMirOpCheckInlinePrediction;
+ invokeMIR->dalvikInsn.opcode = (Opcode)kMirOpCheckInlinePrediction;
dvmCompilerInsertMIRAfter(invokeBB, invokeMIR, invokeMIRSlow);
invokeMIRSlow->OptimizationFlags |= MIR_INLINED_PRED;
@@ -300,8 +300,8 @@
if (bb->blockType != kDalvikByteCode)
continue;
MIR *lastMIRInsn = bb->lastMIRInsn;
- int opcode = lastMIRInsn->dalvikInsn.opcode;
- int flags = dexGetFlagsFromOpcode(opcode);
+ Opcode opcode = lastMIRInsn->dalvikInsn.opcode;
+ int flags = (int)dexGetFlagsFromOpcode(opcode);
/* No invoke - continue */
if ((flags & kInstrInvoke) == 0)
diff --git a/vm/compiler/IntermediateRep.c b/vm/compiler/IntermediateRep.cpp
similarity index 100%
rename from vm/compiler/IntermediateRep.c
rename to vm/compiler/IntermediateRep.cpp
diff --git a/vm/compiler/Loop.c b/vm/compiler/Loop.cpp
similarity index 97%
rename from vm/compiler/Loop.c
rename to vm/compiler/Loop.cpp
index 54517e4..89b8e0f 100644
--- a/vm/compiler/Loop.c
+++ b/vm/compiler/Loop.cpp
@@ -153,7 +153,7 @@
dvmAbort();
break;
}
- return -1;
+ return (Opcode)-1; // unreached
}
/*
@@ -447,7 +447,7 @@
MIR *rangeCheckMIR = (MIR *)dvmCompilerNew(sizeof(MIR), true);
rangeCheckMIR->dalvikInsn.opcode = (loopAnalysis->isCountUpLoop) ?
- kMirOpNullNRangeUpCheck : kMirOpNullNRangeDownCheck;
+ (Opcode)kMirOpNullNRangeUpCheck : (Opcode)kMirOpNullNRangeDownCheck;
rangeCheckMIR->dalvikInsn.vA = arrayReg;
rangeCheckMIR->dalvikInsn.vB = idxReg;
rangeCheckMIR->dalvikInsn.vC = loopAnalysis->endConditionReg;
@@ -466,7 +466,7 @@
if (loopAnalysis->arrayAccessInfo->numUsed != 0) {
if (loopAnalysis->isCountUpLoop) {
MIR *boundCheckMIR = (MIR *)dvmCompilerNew(sizeof(MIR), true);
- boundCheckMIR->dalvikInsn.opcode = kMirOpLowerBound;
+ boundCheckMIR->dalvikInsn.opcode = (Opcode)kMirOpLowerBound;
boundCheckMIR->dalvikInsn.vA = idxReg;
boundCheckMIR->dalvikInsn.vB = globalMinC;
dvmCompilerAppendMIR(entry, boundCheckMIR);
@@ -474,7 +474,7 @@
if (loopAnalysis->loopBranchOpcode == OP_IF_LT ||
loopAnalysis->loopBranchOpcode == OP_IF_LE) {
MIR *boundCheckMIR = (MIR *)dvmCompilerNew(sizeof(MIR), true);
- boundCheckMIR->dalvikInsn.opcode = kMirOpLowerBound;
+ boundCheckMIR->dalvikInsn.opcode = (Opcode)kMirOpLowerBound;
boundCheckMIR->dalvikInsn.vA = loopAnalysis->endConditionReg;
boundCheckMIR->dalvikInsn.vB = globalMinC;
/*
@@ -492,7 +492,7 @@
if (globalMinC < 0) {
MIR *boundCheckMIR = (MIR *)dvmCompilerNew(sizeof(MIR),
true);
- boundCheckMIR->dalvikInsn.opcode = kMirOpPunt;
+ boundCheckMIR->dalvikInsn.opcode = (Opcode)kMirOpPunt;
dvmCompilerAppendMIR(entry, boundCheckMIR);
}
} else if (loopAnalysis->loopBranchOpcode == OP_IF_LEZ) {
@@ -500,7 +500,7 @@
if (globalMinC < -1) {
MIR *boundCheckMIR = (MIR *)dvmCompilerNew(sizeof(MIR),
true);
- boundCheckMIR->dalvikInsn.opcode = kMirOpPunt;
+ boundCheckMIR->dalvikInsn.opcode = (Opcode)kMirOpPunt;
dvmCompilerAppendMIR(entry, boundCheckMIR);
}
} else {
diff --git a/vm/compiler/Ralloc.c b/vm/compiler/Ralloc.cpp
similarity index 100%
rename from vm/compiler/Ralloc.c
rename to vm/compiler/Ralloc.cpp
diff --git a/vm/compiler/SSATransformation.c b/vm/compiler/SSATransformation.cpp
similarity index 98%
rename from vm/compiler/SSATransformation.c
rename to vm/compiler/SSATransformation.cpp
index 6d7dd23..091ed13 100644
--- a/vm/compiler/SSATransformation.c
+++ b/vm/compiler/SSATransformation.cpp
@@ -486,7 +486,7 @@
/* Variable will be clobbered before being used - no need for phi */
if (!dvmIsBitSet(phiBB->dataFlowInfo->liveInV, dalvikReg)) continue;
MIR *phi = (MIR *) dvmCompilerNew(sizeof(MIR), true);
- phi->dalvikInsn.opcode = kMirOpPhi;
+ phi->dalvikInsn.opcode = (Opcode)kMirOpPhi;
phi->dalvikInsn.vA = dalvikReg;
phi->offset = phiBB->startOffset;
dvmCompilerPrependMIR(phiBB, phi);
@@ -507,7 +507,8 @@
/* Phi nodes are at the beginning of each block */
for (mir = bb->firstMIRInsn; mir; mir = mir->next) {
- if (mir->dalvikInsn.opcode != kMirOpPhi) return true;
+ if (mir->dalvikInsn.opcode != (Opcode)kMirOpPhi)
+ return true;
int ssaReg = mir->ssaRep->defs[0];
int encodedDalvikValue =
(int) dvmGrowableListGetElement(cUnit->ssaToDalvikMap, ssaReg);
diff --git a/vm/compiler/Utility.c b/vm/compiler/Utility.cpp
similarity index 99%
rename from vm/compiler/Utility.c
rename to vm/compiler/Utility.cpp
index 2599e0a..c75e5fe 100644
--- a/vm/compiler/Utility.c
+++ b/vm/compiler/Utility.cpp
@@ -157,7 +157,7 @@
void dvmCompilerDumpCompilationUnit(CompilationUnit *cUnit)
{
BasicBlock *bb;
- char *blockTypeNames[] = {
+ const char *blockTypeNames[] = {
"Normal Chaining Cell",
"Hot Chaining Cell",
"Singleton Chaining Cell",
diff --git a/vm/compiler/codegen/CodegenFactory.c b/vm/compiler/codegen/CodegenFactory.cpp
similarity index 100%
rename from vm/compiler/codegen/CodegenFactory.c
rename to vm/compiler/codegen/CodegenFactory.cpp
diff --git a/vm/compiler/codegen/CompilerCodegen.h b/vm/compiler/codegen/CompilerCodegen.h
index efa913f..8223d2a 100644
--- a/vm/compiler/codegen/CompilerCodegen.h
+++ b/vm/compiler/codegen/CompilerCodegen.h
@@ -19,6 +19,10 @@
#include "compiler/CompilerIR.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
/* Maximal number of switch cases to have inline chains */
#define MAX_CHAINED_SWITCH_CASES 64
@@ -34,6 +38,9 @@
/* Assemble LIR into machine code */
void dvmCompilerAssembleLIR(CompilationUnit *cUnit, JitTranslationInfo *info);
+/* Perform translation chain operation. */
+void* dvmJitChain(void* tgtAddr, u4* branchAddr);
+
/* Install class objects in the literal pool */
void dvmJitInstallClassObjectPointers(CompilationUnit *cUnit,
char *codeAddress);
@@ -68,4 +75,8 @@
/* Implemented in codegen/<target>/<target_variant>/ArchVariant.c */
void dvmCompilerGenMemBarrier(CompilationUnit *cUnit, int barrierKind);
+#ifdef __cplusplus
+}
+#endif
+
#endif /* _DALVIK_VM_COMPILERCODEGEN_H_ */
diff --git a/vm/compiler/codegen/RallocUtil.c b/vm/compiler/codegen/RallocUtil.cpp
similarity index 100%
rename from vm/compiler/codegen/RallocUtil.c
rename to vm/compiler/codegen/RallocUtil.cpp
diff --git a/vm/compiler/codegen/arm/ArchFactory.c b/vm/compiler/codegen/arm/ArchFactory.cpp
similarity index 100%
rename from vm/compiler/codegen/arm/ArchFactory.c
rename to vm/compiler/codegen/arm/ArchFactory.cpp
diff --git a/vm/compiler/codegen/arm/ArchUtility.c b/vm/compiler/codegen/arm/ArchUtility.cpp
similarity index 98%
rename from vm/compiler/codegen/arm/ArchUtility.c
rename to vm/compiler/codegen/arm/ArchUtility.cpp
index edcbf86..f3a2a4b 100644
--- a/vm/compiler/codegen/arm/ArchUtility.c
+++ b/vm/compiler/codegen/arm/ArchUtility.cpp
@@ -18,7 +18,7 @@
#include "libdex/DexOpcodes.h"
#include "ArmLIR.h"
-static char *shiftNames[4] = {
+static const char *shiftNames[4] = {
"lsl",
"lsr",
"asr",
@@ -73,14 +73,14 @@
* Interpret a format string and build a string no longer than size
* See format key in Assemble.c.
*/
-static void buildInsnString(char *fmt, ArmLIR *lir, char* buf,
+static void buildInsnString(const char *fmt, ArmLIR *lir, char* buf,
unsigned char *baseAddr, int size)
{
int i;
char *bufEnd = &buf[size-1];
- char *fmtEnd = &fmt[strlen(fmt)];
+ const char *fmtEnd = &fmt[strlen(fmt)];
char tbuf[256];
- char *name;
+ const char *name;
char nc;
while (fmt < fmtEnd) {
int operand;
diff --git a/vm/compiler/codegen/arm/ArmLIR.h b/vm/compiler/codegen/arm/ArmLIR.h
index c47c291..864f5b6 100644
--- a/vm/compiler/codegen/arm/ArmLIR.h
+++ b/vm/compiler/codegen/arm/ArmLIR.h
@@ -734,8 +734,8 @@
} fieldLoc[4];
ArmOpcode opcode;
int flags;
- char *name;
- char* fmt;
+ const char* name;
+ const char* fmt;
int size;
} ArmEncodingMap;
diff --git a/vm/compiler/codegen/arm/ArmRallocUtil.c b/vm/compiler/codegen/arm/ArmRallocUtil.cpp
similarity index 100%
rename from vm/compiler/codegen/arm/ArmRallocUtil.c
rename to vm/compiler/codegen/arm/ArmRallocUtil.cpp
diff --git a/vm/compiler/codegen/arm/Assemble.c b/vm/compiler/codegen/arm/Assemble.cpp
similarity index 99%
rename from vm/compiler/codegen/arm/Assemble.c
rename to vm/compiler/codegen/arm/Assemble.cpp
index 83fec33..16804ba 100644
--- a/vm/compiler/codegen/arm/Assemble.c
+++ b/vm/compiler/codegen/arm/Assemble.cpp
@@ -1754,6 +1754,8 @@
newRechainCount = PREDICTED_CHAIN_COUNTER_AVOID;
goto done;
#else
+ PredictedChainingCell newCell;
+ int baseAddr, branchOffset, tgtAddr;
if (dvmIsNativeMethod(method)) {
UNPROTECT_CODE_CACHE(cell, sizeof(*cell));
@@ -1768,7 +1770,7 @@
PROTECT_CODE_CACHE(cell, sizeof(*cell));
goto done;
}
- int tgtAddr = (int) dvmJitGetTraceAddr(method->insns);
+ tgtAddr = (int) dvmJitGetTraceAddr(method->insns);
/*
* Compilation not made yet for the callee. Reset the counter to a small
@@ -1782,14 +1784,12 @@
goto done;
}
- PredictedChainingCell newCell;
-
if (cell->clazz == NULL) {
newRechainCount = self->icRechainCount;
}
- int baseAddr = (int) cell + 4; // PC is cur_addr + 4
- int branchOffset = tgtAddr - baseAddr;
+ baseAddr = (int) cell + 4; // PC is cur_addr + 4
+ branchOffset = tgtAddr - baseAddr;
newCell.branch = assembleChainingBranch(branchOffset, true);
newCell.clazz = clazz;
diff --git a/vm/compiler/codegen/arm/CalloutHelper.h b/vm/compiler/codegen/arm/CalloutHelper.h
index 931cf0f..3bfb299 100644
--- a/vm/compiler/codegen/arm/CalloutHelper.h
+++ b/vm/compiler/codegen/arm/CalloutHelper.h
@@ -19,6 +19,10 @@
#ifndef _DALVIK_VM_COMPILER_CODEGEN_ARM_CALLOUT_HELPER_H
#define _DALVIK_VM_COMPILER_CODEGEN_ARM_CALLOUT_HELPER_H
+#ifdef __cplusplus
+extern "C" {
+#endif
+
/*
* Declare/comment prototypes of all native callout functions invoked by the
* JIT'ed code here and use the LOAD_FUNC_ADDR macro to load the address into
@@ -121,4 +125,8 @@
* dvmLockObject // MONITOR_ENTER
*/
+#ifdef __cplusplus
+}
+#endif
+
#endif /* _DALVIK_VM_COMPILER_CODEGEN_ARM_CALLOUT_HELPER_H */
diff --git a/vm/compiler/codegen/arm/Codegen.h b/vm/compiler/codegen/arm/Codegen.h
index 330619b..afeb340 100644
--- a/vm/compiler/codegen/arm/Codegen.h
+++ b/vm/compiler/codegen/arm/Codegen.h
@@ -25,6 +25,10 @@
#include "compiler/CompilerIR.h"
#include "CalloutHelper.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
#if defined(_CODEGEN_C)
/*
* loadConstant() sometimes needs to add a small imm to a pre-existing constant
@@ -63,3 +67,7 @@
extern ArmLIR* dvmCompilerRegCopyNoInsert(CompilationUnit *cUnit, int rDest,
int rSrc);
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/vm/compiler/codegen/arm/CodegenCommon.c b/vm/compiler/codegen/arm/CodegenCommon.cpp
similarity index 100%
rename from vm/compiler/codegen/arm/CodegenCommon.c
rename to vm/compiler/codegen/arm/CodegenCommon.cpp
diff --git a/vm/compiler/codegen/arm/CodegenDriver.c b/vm/compiler/codegen/arm/CodegenDriver.cpp
similarity index 99%
rename from vm/compiler/codegen/arm/CodegenDriver.c
rename to vm/compiler/codegen/arm/CodegenDriver.cpp
index 6060ab7..c38b16a 100644
--- a/vm/compiler/codegen/arm/CodegenDriver.c
+++ b/vm/compiler/codegen/arm/CodegenDriver.cpp
@@ -769,7 +769,7 @@
bool checkZero = false;
bool unary = false;
int retReg = r0;
- void *callTgt;
+ int (*callTgt)(int, int);
RegLocation rlResult;
bool shiftOp = false;
@@ -2155,7 +2155,7 @@
cond = kArmCondLe;
break;
default:
- cond = 0;
+ cond = (ArmConditionCode)0;
LOGE("Unexpected opcode (%d) for Fmt21t\n", dalvikOpcode);
dvmCompilerAbort(cUnit);
}
@@ -2294,7 +2294,7 @@
RegLocation rlDest = dvmCompilerGetDest(cUnit, mir, 0);
RegLocation rlResult;
int lit = mir->dalvikInsn.vC;
- OpKind op = 0; /* Make gcc happy */
+ OpKind op = (OpKind)0; /* Make gcc happy */
int shiftOp = false;
bool isDiv = false;
@@ -2700,7 +2700,7 @@
cond = kArmCondLe;
break;
default:
- cond = 0;
+ cond = (ArmConditionCode)0;
LOGE("Unexpected opcode (%d) for Fmt22t\n", dalvikOpcode);
dvmCompilerAbort(cUnit);
}
@@ -3904,7 +3904,7 @@
}
}
-static char *extendedMIROpNames[kMirOpLast - kMirOpFirst] = {
+static const char *extendedMIROpNames[kMirOpLast - kMirOpFirst] = {
"kMirOpPhi",
"kMirOpNullNRangeUpCheck",
"kMirOpNullNRangeDownCheck",
@@ -4135,7 +4135,7 @@
strcpy(msg, extendedMIROpNames[opOffset]);
newLIR1(cUnit, kArmPseudoExtended, (int) msg);
- switch (mir->dalvikInsn.opcode) {
+ switch ((ExtendedMIROpcode)mir->dalvikInsn.opcode) {
case kMirOpPhi: {
char *ssaString = dvmCompilerGetSSAString(cUnit, mir->ssaRep);
newLIR1(cUnit, kArmPseudoSSARep, (int) ssaString);
@@ -4238,6 +4238,7 @@
/* Used to hold the labels of each block */
ArmLIR *labelList =
(ArmLIR *) dvmCompilerNew(sizeof(ArmLIR) * cUnit->numBlocks, true);
+ ArmLIR *headLIR = NULL;
GrowableList chainingListByType[kChainingCellGap];
int i;
@@ -4365,15 +4366,12 @@
continue;
}
- ArmLIR *headLIR = NULL;
- BasicBlock *nextBB = bb;
-
/*
* Try to build a longer optimization unit. Currently if the previous
* block ends with a goto, we continue adding instructions and don't
* reset the register allocation pool.
*/
- for (; nextBB != NULL; nextBB = cUnit->nextCodegenBlock) {
+ for (BasicBlock *nextBB = bb; nextBB != NULL; nextBB = cUnit->nextCodegenBlock) {
bb = nextBB;
bb->visited = true;
cUnit->nextCodegenBlock = NULL;
@@ -4389,16 +4387,15 @@
dvmCompilerResetDefTracking(cUnit);
}
- if (mir->dalvikInsn.opcode >= kMirOpFirst) {
+ if ((int)mir->dalvikInsn.opcode >= (int)kMirOpFirst) {
handleExtendedMIR(cUnit, mir);
continue;
}
-
Opcode dalvikOpcode = mir->dalvikInsn.opcode;
InstructionFormat dalvikFormat =
dexGetFormatFromOpcode(dalvikOpcode);
- char *note;
+ const char *note;
if (mir->OptimizationFlags & MIR_INLINED) {
note = " (I)";
} else if (mir->OptimizationFlags & MIR_INLINED_PRED) {
@@ -4690,7 +4687,7 @@
break;
}
case kWorkOrderProfileMode:
- dvmJitChangeProfileMode((TraceProfilingModes)work->info);
+ dvmJitChangeProfileMode((TraceProfilingModes)(int)work->info);
isCompile = false;
break;
default:
diff --git a/vm/compiler/codegen/arm/FP/Thumb2VFP.c b/vm/compiler/codegen/arm/FP/Thumb2VFP.cpp
similarity index 95%
rename from vm/compiler/codegen/arm/FP/Thumb2VFP.c
rename to vm/compiler/codegen/arm/FP/Thumb2VFP.cpp
index 61698c2..aed4950 100644
--- a/vm/compiler/codegen/arm/FP/Thumb2VFP.c
+++ b/vm/compiler/codegen/arm/FP/Thumb2VFP.cpp
@@ -54,7 +54,8 @@
rlSrc1 = loadValue(cUnit, rlSrc1, kFPReg);
rlSrc2 = loadValue(cUnit, rlSrc2, kFPReg);
rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kFPReg, true);
- newLIR3(cUnit, op, rlResult.lowReg, rlSrc1.lowReg, rlSrc2.lowReg);
+ newLIR3(cUnit, (ArmOpcode)op, rlResult.lowReg, rlSrc1.lowReg,
+ rlSrc2.lowReg);
storeValue(cUnit, rlDest, rlResult);
return false;
}
@@ -100,7 +101,7 @@
rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kFPReg, true);
assert(rlDest.wide);
assert(rlResult.wide);
- newLIR3(cUnit, op, S2D(rlResult.lowReg, rlResult.highReg),
+ newLIR3(cUnit, (ArmOpcode)op, S2D(rlResult.lowReg, rlResult.highReg),
S2D(rlSrc1.lowReg, rlSrc1.highReg),
S2D(rlSrc2.lowReg, rlSrc2.highReg));
storeValueWide(cUnit, rlDest, rlResult);
@@ -169,12 +170,13 @@
if (longDest) {
rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kFPReg, true);
- newLIR2(cUnit, op, S2D(rlResult.lowReg, rlResult.highReg), srcReg);
+ newLIR2(cUnit, (ArmOpcode)op, S2D(rlResult.lowReg, rlResult.highReg),
+ srcReg);
storeValueWide(cUnit, rlDest, rlResult);
} else {
rlDest = dvmCompilerGetDest(cUnit, mir, 0);
rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kFPReg, true);
- newLIR2(cUnit, op, rlResult.lowReg, srcReg);
+ newLIR2(cUnit, (ArmOpcode)op, rlResult.lowReg, srcReg);
storeValue(cUnit, rlDest, rlResult);
}
return false;
diff --git a/vm/compiler/codegen/arm/FP/ThumbPortableFP.c b/vm/compiler/codegen/arm/FP/ThumbPortableFP.cpp
similarity index 100%
rename from vm/compiler/codegen/arm/FP/ThumbPortableFP.c
rename to vm/compiler/codegen/arm/FP/ThumbPortableFP.cpp
diff --git a/vm/compiler/codegen/arm/FP/ThumbVFP.c b/vm/compiler/codegen/arm/FP/ThumbVFP.cpp
similarity index 100%
rename from vm/compiler/codegen/arm/FP/ThumbVFP.c
rename to vm/compiler/codegen/arm/FP/ThumbVFP.cpp
diff --git a/vm/compiler/codegen/arm/GlobalOptimizations.c b/vm/compiler/codegen/arm/GlobalOptimizations.cpp
similarity index 100%
rename from vm/compiler/codegen/arm/GlobalOptimizations.c
rename to vm/compiler/codegen/arm/GlobalOptimizations.cpp
diff --git a/vm/compiler/codegen/arm/LocalOptimizations.c b/vm/compiler/codegen/arm/LocalOptimizations.cpp
similarity index 100%
rename from vm/compiler/codegen/arm/LocalOptimizations.c
rename to vm/compiler/codegen/arm/LocalOptimizations.cpp
diff --git a/vm/compiler/codegen/arm/Thumb/Factory.c b/vm/compiler/codegen/arm/Thumb/Factory.cpp
similarity index 100%
rename from vm/compiler/codegen/arm/Thumb/Factory.c
rename to vm/compiler/codegen/arm/Thumb/Factory.cpp
diff --git a/vm/compiler/codegen/arm/Thumb/Gen.c b/vm/compiler/codegen/arm/Thumb/Gen.cpp
similarity index 100%
rename from vm/compiler/codegen/arm/Thumb/Gen.c
rename to vm/compiler/codegen/arm/Thumb/Gen.cpp
diff --git a/vm/compiler/codegen/arm/Thumb/Ralloc.c b/vm/compiler/codegen/arm/Thumb/Ralloc.cpp
similarity index 100%
rename from vm/compiler/codegen/arm/Thumb/Ralloc.c
rename to vm/compiler/codegen/arm/Thumb/Ralloc.cpp
diff --git a/vm/compiler/codegen/arm/Thumb2/Factory.c b/vm/compiler/codegen/arm/Thumb2/Factory.cpp
similarity index 100%
rename from vm/compiler/codegen/arm/Thumb2/Factory.c
rename to vm/compiler/codegen/arm/Thumb2/Factory.cpp
diff --git a/vm/compiler/codegen/arm/Thumb2/Gen.c b/vm/compiler/codegen/arm/Thumb2/Gen.cpp
similarity index 99%
rename from vm/compiler/codegen/arm/Thumb2/Gen.c
rename to vm/compiler/codegen/arm/Thumb2/Gen.cpp
index f54b7eb..fcf0fe3 100644
--- a/vm/compiler/codegen/arm/Thumb2/Gen.c
+++ b/vm/compiler/codegen/arm/Thumb2/Gen.cpp
@@ -165,7 +165,7 @@
* is not met.
*/
static ArmLIR *genIT(CompilationUnit *cUnit, ArmConditionCode code,
- char *guide)
+ const char *guide)
{
int mask;
int condBit = code & 1;
diff --git a/vm/compiler/codegen/arm/Thumb2/Ralloc.c b/vm/compiler/codegen/arm/Thumb2/Ralloc.cpp
similarity index 100%
rename from vm/compiler/codegen/arm/Thumb2/Ralloc.c
rename to vm/compiler/codegen/arm/Thumb2/Ralloc.cpp
diff --git a/vm/compiler/codegen/arm/armv5te-vfp/ArchVariant.c b/vm/compiler/codegen/arm/armv5te-vfp/ArchVariant.cpp
similarity index 100%
rename from vm/compiler/codegen/arm/armv5te-vfp/ArchVariant.c
rename to vm/compiler/codegen/arm/armv5te-vfp/ArchVariant.cpp
diff --git a/vm/compiler/codegen/arm/armv5te-vfp/Codegen.c b/vm/compiler/codegen/arm/armv5te-vfp/Codegen.cpp
similarity index 100%
rename from vm/compiler/codegen/arm/armv5te-vfp/Codegen.c
rename to vm/compiler/codegen/arm/armv5te-vfp/Codegen.cpp
diff --git a/vm/compiler/codegen/arm/armv5te/ArchVariant.c b/vm/compiler/codegen/arm/armv5te/ArchVariant.cpp
similarity index 100%
rename from vm/compiler/codegen/arm/armv5te/ArchVariant.c
rename to vm/compiler/codegen/arm/armv5te/ArchVariant.cpp
diff --git a/vm/compiler/codegen/arm/armv5te/Codegen.c b/vm/compiler/codegen/arm/armv5te/Codegen.cpp
similarity index 100%
rename from vm/compiler/codegen/arm/armv5te/Codegen.c
rename to vm/compiler/codegen/arm/armv5te/Codegen.cpp
diff --git a/vm/compiler/codegen/arm/armv5te/MethodCodegenDriver.c b/vm/compiler/codegen/arm/armv5te/MethodCodegenDriver.cpp
similarity index 100%
rename from vm/compiler/codegen/arm/armv5te/MethodCodegenDriver.c
rename to vm/compiler/codegen/arm/armv5te/MethodCodegenDriver.cpp
diff --git a/vm/compiler/codegen/arm/armv7-a-neon/ArchVariant.c b/vm/compiler/codegen/arm/armv7-a-neon/ArchVariant.cpp
similarity index 100%
rename from vm/compiler/codegen/arm/armv7-a-neon/ArchVariant.c
rename to vm/compiler/codegen/arm/armv7-a-neon/ArchVariant.cpp
diff --git a/vm/compiler/codegen/arm/armv7-a-neon/Codegen.c b/vm/compiler/codegen/arm/armv7-a-neon/Codegen.cpp
similarity index 100%
rename from vm/compiler/codegen/arm/armv7-a-neon/Codegen.c
rename to vm/compiler/codegen/arm/armv7-a-neon/Codegen.cpp
diff --git a/vm/compiler/codegen/arm/armv7-a-neon/MethodCodegenDriver.c b/vm/compiler/codegen/arm/armv7-a-neon/MethodCodegenDriver.cpp
similarity index 100%
rename from vm/compiler/codegen/arm/armv7-a-neon/MethodCodegenDriver.c
rename to vm/compiler/codegen/arm/armv7-a-neon/MethodCodegenDriver.cpp
diff --git a/vm/compiler/codegen/arm/armv7-a/ArchVariant.c b/vm/compiler/codegen/arm/armv7-a/ArchVariant.cpp
similarity index 94%
rename from vm/compiler/codegen/arm/armv7-a/ArchVariant.c
rename to vm/compiler/codegen/arm/armv7-a/ArchVariant.cpp
index 59d7c95..245ff78 100644
--- a/vm/compiler/codegen/arm/armv7-a/ArchVariant.c
+++ b/vm/compiler/codegen/arm/armv7-a/ArchVariant.cpp
@@ -14,6 +14,8 @@
* limitations under the License.
*/
+extern "C" void dvmCompilerTemplateStart(void);
+
/*
* Determine the initial instruction set to be used for this trace.
* Later components may decide to change this.
@@ -23,16 +25,15 @@
return DALVIK_JIT_THUMB2;
}
-/* Architecture-specific initializations and checks go here */
-bool dvmCompilerArchVariantInit(void)
-{
- /* First, declare dvmCompiler_TEMPLATE_XXX for each template */
-#define JIT_TEMPLATE(X) extern void dvmCompiler_TEMPLATE_##X();
+/* First, declare dvmCompiler_TEMPLATE_XXX for each template */
+#define JIT_TEMPLATE(X) extern "C" void dvmCompiler_TEMPLATE_##X();
#include "../../../template/armv5te-vfp/TemplateOpList.h"
#undef JIT_TEMPLATE
+/* Architecture-specific initializations and checks go here */
+bool dvmCompilerArchVariantInit(void)
+{
int i = 0;
- extern void dvmCompilerTemplateStart(void);
/*
* Then, populate the templateEntryOffsets array with the offsets from the
diff --git a/vm/compiler/codegen/arm/armv7-a/ArchVariant.h b/vm/compiler/codegen/arm/armv7-a/ArchVariant.h
index fa01210..747ecc1 100644
--- a/vm/compiler/codegen/arm/armv7-a/ArchVariant.h
+++ b/vm/compiler/codegen/arm/armv7-a/ArchVariant.h
@@ -17,6 +17,10 @@
#ifndef _DALVIK_VM_COMPILER_CODEGEN_ARM_ARMV5TE_VFP_ARCHVARIANT_H
#define _DALVIK_VM_COMPILER_CODEGEN_ARM_ARMV5TE_VFP_ARCHVARIANT_H
+#ifdef __cplusplus
+extern "C" {
+#endif
+
/* Create the TemplateOpcode enum */
#define JIT_TEMPLATE(X) TEMPLATE_##X,
typedef enum {
@@ -31,4 +35,8 @@
} TemplateOpcode;
#undef JIT_TEMPLATE
+#ifdef __cplusplus
+}
+#endif
+
#endif /* _DALVIK_VM_COMPILER_CODEGEN_ARM_ARMV5TE_VFP_ARCHVARIANT_H */
diff --git a/vm/compiler/codegen/arm/armv7-a/Codegen.c b/vm/compiler/codegen/arm/armv7-a/Codegen.cpp
similarity index 80%
rename from vm/compiler/codegen/arm/armv7-a/Codegen.c
rename to vm/compiler/codegen/arm/armv7-a/Codegen.cpp
index 36771ef..e1b0ee9 100644
--- a/vm/compiler/codegen/arm/armv7-a/Codegen.c
+++ b/vm/compiler/codegen/arm/armv7-a/Codegen.cpp
@@ -29,28 +29,28 @@
#include "ArchVariant.h"
/* Arm codegen building blocks */
-#include "../CodegenCommon.c"
+#include "../CodegenCommon.cpp"
/* Thumb2-specific factory utilities */
-#include "../Thumb2/Factory.c"
+#include "../Thumb2/Factory.cpp"
/* Target independent factory utilities */
-#include "../../CodegenFactory.c"
+#include "../../CodegenFactory.cpp"
/* Arm-specific factory utilities */
-#include "../ArchFactory.c"
+#include "../ArchFactory.cpp"
/* Thumb2-specific codegen routines */
-#include "../Thumb2/Gen.c"
+#include "../Thumb2/Gen.cpp"
/* Thumb2+VFP codegen routines */
-#include "../FP/Thumb2VFP.c"
+#include "../FP/Thumb2VFP.cpp"
/* Thumb2-specific register allocation */
-#include "../Thumb2/Ralloc.c"
+#include "../Thumb2/Ralloc.cpp"
/* MIR2LIR dispatcher and architectural independent codegen routines */
-#include "../CodegenDriver.c"
+#include "../CodegenDriver.cpp"
/* Driver for method-based JIT */
-#include "../armv7-a-neon/MethodCodegenDriver.c"
+#include "../armv7-a-neon/MethodCodegenDriver.cpp"
/* Architecture manifest */
-#include "ArchVariant.c"
+#include "ArchVariant.cpp"
diff --git a/vm/compiler/codegen/x86/ArchUtility.c b/vm/compiler/codegen/x86/ArchUtility.cpp
similarity index 100%
rename from vm/compiler/codegen/x86/ArchUtility.c
rename to vm/compiler/codegen/x86/ArchUtility.cpp
diff --git a/vm/compiler/codegen/x86/Assemble.c b/vm/compiler/codegen/x86/Assemble.cpp
similarity index 100%
rename from vm/compiler/codegen/x86/Assemble.c
rename to vm/compiler/codegen/x86/Assemble.cpp
diff --git a/vm/compiler/codegen/x86/CodegenDriver.c b/vm/compiler/codegen/x86/CodegenDriver.cpp
similarity index 100%
rename from vm/compiler/codegen/x86/CodegenDriver.c
rename to vm/compiler/codegen/x86/CodegenDriver.cpp
diff --git a/vm/compiler/codegen/x86/ia32/ArchVariant.c b/vm/compiler/codegen/x86/ia32/ArchVariant.cpp
similarity index 95%
rename from vm/compiler/codegen/x86/ia32/ArchVariant.c
rename to vm/compiler/codegen/x86/ia32/ArchVariant.cpp
index 90f14a3..4dd528e 100644
--- a/vm/compiler/codegen/x86/ia32/ArchVariant.c
+++ b/vm/compiler/codegen/x86/ia32/ArchVariant.cpp
@@ -28,14 +28,14 @@
return DALVIK_JIT_IA32;
}
-/* Architecture-specific initializations and checks go here */
-bool dvmCompilerArchVariantInit(void)
-{
- /* First, declare dvmCompiler_TEMPLATE_XXX for each template */
-#define JIT_TEMPLATE(X) extern void dvmCompiler_TEMPLATE_##X();
+/* First, declare dvmCompiler_TEMPLATE_XXX for each template */
+#define JIT_TEMPLATE(X) extern "C" void dvmCompiler_TEMPLATE_##X();
#include "../../../template/ia32/TemplateOpList.h"
#undef JIT_TEMPLATE
+/* Architecture-specific initializations and checks go here */
+bool dvmCompilerArchVariantInit(void)
+{
int i = 0;
extern void dvmCompilerTemplateStart(void);
diff --git a/vm/compiler/codegen/x86/ia32/Codegen.c b/vm/compiler/codegen/x86/ia32/Codegen.cpp
similarity index 100%
rename from vm/compiler/codegen/x86/ia32/Codegen.c
rename to vm/compiler/codegen/x86/ia32/Codegen.cpp