Enable JIT parameters to be initialized in an architecture dependent way.
The search for optimial value is still ongoing. The current settings are:
v5 v7
JIT profile table 512 2048
JIT code cache 512K 1M
JIT threshold 200 40
diff --git a/vm/compiler/Compiler.c b/vm/compiler/Compiler.c
index 2fafd4e..1d52198 100644
--- a/vm/compiler/Compiler.c
+++ b/vm/compiler/Compiler.c
@@ -126,7 +126,7 @@
extern void dmvCompilerTemplateEnd(void);
/* Allocate the code cache */
- gDvmJit.codeCache = mmap(0, CODE_CACHE_SIZE,
+ gDvmJit.codeCache = mmap(0, gDvmJit.codeCacheSize,
PROT_READ | PROT_WRITE | PROT_EXEC,
MAP_PRIVATE | MAP_ANON, -1, 0);
if (gDvmJit.codeCache == MAP_FAILED) {
diff --git a/vm/compiler/Compiler.h b/vm/compiler/Compiler.h
index 153e845..ccc91dd 100644
--- a/vm/compiler/Compiler.h
+++ b/vm/compiler/Compiler.h
@@ -19,7 +19,6 @@
#ifndef _DALVIK_VM_COMPILER
#define _DALVIK_VM_COMPILER
-#define CODE_CACHE_SIZE 1024*1024
#define MAX_JIT_RUN_LEN 64
#define COMPILER_WORK_QUEUE_SIZE 100
#define COMPILER_IC_PATCH_QUEUE_SIZE 64
diff --git a/vm/compiler/codegen/arm/Assemble.c b/vm/compiler/codegen/arm/Assemble.c
index 826a3d2..fd7c76b 100644
--- a/vm/compiler/codegen/arm/Assemble.c
+++ b/vm/compiler/codegen/arm/Assemble.c
@@ -1216,7 +1216,7 @@
cUnit->totalSize = offset;
- if (gDvmJit.codeCacheByteUsed + cUnit->totalSize > CODE_CACHE_SIZE) {
+ if (gDvmJit.codeCacheByteUsed + cUnit->totalSize > gDvmJit.codeCacheSize) {
gDvmJit.codeCacheFull = true;
cUnit->baseAddr = NULL;
return;
@@ -1504,7 +1504,7 @@
/* Initialize the min/max address range */
minAddr = (PredictedChainingCell *)
- ((char *) gDvmJit.codeCache + CODE_CACHE_SIZE);
+ ((char *) gDvmJit.codeCache + gDvmJit.codeCacheSize);
maxAddr = (PredictedChainingCell *) gDvmJit.codeCache;
for (i = 0; i < gDvmJit.compilerICPatchIndex; i++) {
diff --git a/vm/compiler/codegen/arm/armv5te-vfp/ArchVariant.c b/vm/compiler/codegen/arm/armv5te-vfp/ArchVariant.c
index 9a602f6..b5706f5 100644
--- a/vm/compiler/codegen/arm/armv5te-vfp/ArchVariant.c
+++ b/vm/compiler/codegen/arm/armv5te-vfp/ArchVariant.c
@@ -52,6 +52,7 @@
gDvmJit.jitTableSize = 1 << 9; // 512
gDvmJit.jitTableMask = gDvmJit.jitTableSize - 1;
gDvmJit.threshold = 200;
+ gDvmJit.codeCacheSize = 512*1024;
#if defined(WITH_SELF_VERIFICATION)
/* Force into blocking mode */
diff --git a/vm/compiler/codegen/arm/armv5te/ArchVariant.c b/vm/compiler/codegen/arm/armv5te/ArchVariant.c
index 2d080e4..1311510 100644
--- a/vm/compiler/codegen/arm/armv5te/ArchVariant.c
+++ b/vm/compiler/codegen/arm/armv5te/ArchVariant.c
@@ -52,6 +52,7 @@
gDvmJit.jitTableSize = 1 << 9; // 512
gDvmJit.jitTableMask = gDvmJit.jitTableSize - 1;
gDvmJit.threshold = 200;
+ gDvmJit.codeCacheSize = 512*1024;
#if defined(WITH_SELF_VERIFICATION)
/* Force into blocking mode */
diff --git a/vm/compiler/codegen/arm/armv7-a/ArchVariant.c b/vm/compiler/codegen/arm/armv7-a/ArchVariant.c
index cd8754c..1579d12 100644
--- a/vm/compiler/codegen/arm/armv7-a/ArchVariant.c
+++ b/vm/compiler/codegen/arm/armv7-a/ArchVariant.c
@@ -14,7 +14,6 @@
* limitations under the License.
*/
-
/*
* Determine the initial instruction set to be used for this trace.
* Later components may decide to change this.
@@ -48,6 +47,7 @@
gDvmJit.jitTableSize = 1 << 12; // 4096
gDvmJit.jitTableMask = gDvmJit.jitTableSize - 1;
gDvmJit.threshold = 40;
+ gDvmJit.codeCacheSize = 1024*1024;
#if defined(WITH_SELF_VERIFICATION)
/* Force into blocking */