commit cc6600c2702c0b29457836acde1cfc4f25c63b67
author Ben Cheng <bccheng@android.com> Mon Jun 22 14:45:16 2009 -0700
committer Ben Cheng <bccheng@android.com> Mon Jun 22 15:14:34 2009 -0700
tree 31d291df3cb735082aac0f191a8883dc7f2835f7
parent 48f1824fd36241067e7bed2302cc00b2d880be7f

The address of dvmMterpCommonExceptionThrown should be loaded in a position-independent way since these handlers are copied into the code cache.

BTW fixed a couple recently introduced compiler warnings in Codegen.c.

vm/compiler/codegen/armv5te/Codegen.c

diff --git a/vm/compiler/codegen/armv5te/Codegen.c b/vm/compiler/codegen/armv5te/Codegen.c
index b4f7c73..b272e48 100644
--- a/vm/compiler/codegen/armv5te/Codegen.c
+++ b/vm/compiler/codegen/armv5te/Codegen.c
@@ -2861,7 +2861,8 @@
          */
         newLIR1(cUnit, ARMV5TE_16BIT_DATA, 0);
         newLIR1(cUnit, ARMV5TE_16BIT_DATA, 0);
-        cUnit->chainCellOffsetLIR = newLIR1(cUnit, ARMV5TE_16BIT_DATA, CHAIN_CELL_OFFSET_TAG);
+        cUnit->chainCellOffsetLIR =
+            (LIR *) newLIR1(cUnit, ARMV5TE_16BIT_DATA, CHAIN_CELL_OFFSET_TAG);
         cUnit->headerSize = 6;
         newLIR2(cUnit, ARMV5TE_MOV_RR_HL, r0, rpc & THUMB_REG_MASK);
         newLIR2(cUnit, ARMV5TE_SUB_RI8, r0, 10);
@@ -2870,7 +2871,8 @@
         newLIR3(cUnit, ARMV5TE_STR_RRI5, r1, r0, 0);
     } else {
          /* Just reserve 2 bytes for the chain cell offset */
-        cUnit->chainCellOffsetLIR = newLIR1(cUnit, ARMV5TE_16BIT_DATA, CHAIN_CELL_OFFSET_TAG);
+        cUnit->chainCellOffsetLIR =
+            (LIR *) newLIR1(cUnit, ARMV5TE_16BIT_DATA, CHAIN_CELL_OFFSET_TAG);
         cUnit->headerSize = 2;
     }
 

vm/compiler/template/armv5te/footer.S

diff --git a/vm/compiler/template/armv5te/footer.S b/vm/compiler/template/armv5te/footer.S
index e961e29..29073c3 100644
--- a/vm/compiler/template/armv5te/footer.S
+++ b/vm/compiler/template/armv5te/footer.S
@@ -34,11 +34,12 @@
     bne     .LhandleException             @ no, handle exception
     bx      r2
 
-/* FIXME - untested */
+/* NOTE - this path can be exercised if the JIT threshold is set to 5 */
 .LhandleException:
-    ldr     rIBASE, .LdvmAsmInstructionStart
+    ldr     r0, .LdvmMterpCommonExceptionThrown @ PIC way of getting &func
+    ldr     rIBASE, .LdvmAsmInstructionStart    @ same as above
     ldr     rPC, [r10, #offStackSaveArea_savedPc] @ reload rPC
-    b       dvmMterpCommonExceptionThrown
+    mov     pc, r0                  @ branch to dvmMterpCommonExceptionThrown
 
     .align  2
 .LdvmAsmInstructionStart:
@@ -47,6 +48,8 @@
     .word   dvmJitToInterpNoChain
 .LdvmMterpStdBail:
     .word   dvmMterpStdBail
+.LdvmMterpCommonExceptionThrown:
+    .word   dvmMterpCommonExceptionThrown
 .L__aeabi_cdcmple:
     .word   __aeabi_cdcmple
 .L__aeabi_cfcmple:

vm/compiler/template/out/CompilerTemplateAsm-armv5te.S

diff --git a/vm/compiler/template/out/CompilerTemplateAsm-armv5te.S b/vm/compiler/template/out/CompilerTemplateAsm-armv5te.S
index c1b4733..0831100 100644
--- a/vm/compiler/template/out/CompilerTemplateAsm-armv5te.S
+++ b/vm/compiler/template/out/CompilerTemplateAsm-armv5te.S
@@ -1132,9 +1132,10 @@
 
 /* FIXME - untested */
 .LhandleException:
-    ldr     rIBASE, .LdvmAsmInstructionStart
+    ldr     r0, .LdvmMterpCommonExceptionThrown @ PIC way of getting &func
+    ldr     rIBASE, .LdvmAsmInstructionStart    @ same as above
     ldr     rPC, [r10, #offStackSaveArea_savedPc] @ reload rPC
-    b       dvmMterpCommonExceptionThrown
+    mov     pc, r0                  @ branch to dvmMterpCommonExceptionThrown
 
     .align  2
 .LdvmAsmInstructionStart:
@@ -1143,6 +1144,8 @@
     .word   dvmJitToInterpNoChain
 .LdvmMterpStdBail:
     .word   dvmMterpStdBail
+.LdvmMterpCommonExceptionThrown:
+    .word   dvmMterpCommonExceptionThrown
 .L__aeabi_cdcmple:
     .word   __aeabi_cdcmple
 .L__aeabi_cfcmple: