Remove unused labels, variables, and functions. Enable warnings.
Change-Id: Icbe24eaf1ad499f28b68b6a5f05368271a0a7e86
diff --git a/vm/compiler/codegen/arm/ArchUtility.c b/vm/compiler/codegen/arm/ArchUtility.c
index b0478f4..31e7c0b 100644
--- a/vm/compiler/codegen/arm/ArchUtility.c
+++ b/vm/compiler/codegen/arm/ArchUtility.c
@@ -239,7 +239,6 @@
char opName[256];
int offset = lir->generic.offset;
int dest = lir->operands[0];
- u2 *cPtr = (u2*)baseAddr;
const bool dumpNop = false;
/* Handle pseudo-ops individually, and all regular insns as a group */
diff --git a/vm/compiler/codegen/arm/Assemble.c b/vm/compiler/codegen/arm/Assemble.c
index 05d311b..3c00ece 100644
--- a/vm/compiler/codegen/arm/Assemble.c
+++ b/vm/compiler/codegen/arm/Assemble.c
@@ -1420,6 +1420,7 @@
* Attempt to enqueue a work order to patch an inline cache for a predicted
* chaining cell for virtual/interface calls.
*/
+#if !defined(WITH_SELF_VERIFICATION)
static bool inlineCachePatchEnqueue(PredictedChainingCell *cellAddr,
PredictedChainingCell *newContent)
{
@@ -1474,6 +1475,7 @@
dvmUnlockMutex(&gDvmJit.compilerICPatchLock);
return result;
}
+#endif
/*
* This method is called from the invoke templates for virtual and interface
@@ -1641,8 +1643,6 @@
int cellSize;
u4* pChainCells;
u4* pStart;
- u4 thumb1;
- u4 thumb2;
u4 newInst;
int i,j;
PredictedChainingCell *predChainCell;
@@ -2246,7 +2246,6 @@
//LOGD("*** THUMB2 - Addr: 0x%x Insn: 0x%x", lr, insn);
int opcode12 = (insn >> 20) & 0xFFF;
- int opcode6 = (insn >> 6) & 0x3F;
int opcode4 = (insn >> 8) & 0xF;
int imm2 = (insn >> 4) & 0x3;
int imm8 = insn & 0xFF;
diff --git a/vm/compiler/codegen/arm/CodegenDriver.c b/vm/compiler/codegen/arm/CodegenDriver.c
index 515e8af..711431e 100644
--- a/vm/compiler/codegen/arm/CodegenDriver.c
+++ b/vm/compiler/codegen/arm/CodegenDriver.c
@@ -197,7 +197,6 @@
static void selfVerificationBranchInsertPass(CompilationUnit *cUnit)
{
ArmLIR *thisLIR;
- ArmLIR *branchLIR = dvmCompilerNew(sizeof(ArmLIR), true);
TemplateOpCode opCode = TEMPLATE_MEM_OP_DECODE;
for (thisLIR = (ArmLIR *) cUnit->firstLIRInsn;
@@ -237,7 +236,6 @@
/* Load a wide field from an object instance */
static void genIGetWide(CompilationUnit *cUnit, MIR *mir, int fieldOffset)
{
- DecodedInstruction *dInsn = &mir->dalvikInsn;
RegLocation rlObj = dvmCompilerGetSrc(cUnit, mir, 0);
RegLocation rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
RegLocation rlResult;
@@ -262,7 +260,6 @@
/* Store a wide field to an object instance */
static void genIPutWide(CompilationUnit *cUnit, MIR *mir, int fieldOffset)
{
- DecodedInstruction *dInsn = &mir->dalvikInsn;
RegLocation rlSrc = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
RegLocation rlObj = dvmCompilerGetSrc(cUnit, mir, 2);
rlObj = loadValue(cUnit, rlObj, kCoreReg);
@@ -287,9 +284,7 @@
static void genIGet(CompilationUnit *cUnit, MIR *mir, OpSize size,
int fieldOffset)
{
- int regPtr;
RegLocation rlResult;
- DecodedInstruction *dInsn = &mir->dalvikInsn;
RegLocation rlObj = dvmCompilerGetSrc(cUnit, mir, 0);
RegLocation rlDest = dvmCompilerGetDest(cUnit, mir, 0);
rlObj = loadValue(cUnit, rlObj, kCoreReg);
@@ -312,12 +307,10 @@
static void genIPut(CompilationUnit *cUnit, MIR *mir, OpSize size,
int fieldOffset)
{
- DecodedInstruction *dInsn = &mir->dalvikInsn;
RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
RegLocation rlObj = dvmCompilerGetSrc(cUnit, mir, 1);
rlObj = loadValue(cUnit, rlObj, kCoreReg);
rlSrc = loadValue(cUnit, rlSrc, kAnyReg);
- int regPtr;
genNullCheck(cUnit, rlObj.sRegLow, rlObj.lowReg, mir->offset,
NULL);/* null object? */
@@ -1185,6 +1178,7 @@
* The return LIR is a branch based on the comparison result. The actual branch
* target will be setup in the caller.
*/
+#if 0
static ArmLIR *genCheckPredictedChain(CompilationUnit *cUnit,
ArmLIR *predChainingCell,
ArmLIR *retChainingCell,
@@ -1235,6 +1229,7 @@
return opCondBranch(cUnit, kArmCondEq);
}
+#endif
/* Geneate a branch to go back to the interpreter */
static void genPuntToInterp(CompilationUnit *cUnit, unsigned int offset)
@@ -2183,8 +2178,7 @@
* "len < 0": bail to the interpreter to re-execute the
* instruction
*/
- ArmLIR *pcrLabel =
- genRegImmCheck(cUnit, kArmCondMi, r1, 0, mir->offset, NULL);
+ genRegImmCheck(cUnit, kArmCondMi, r1, 0, mir->offset, NULL);
loadConstant(cUnit, r2, ALLOC_DONT_TRACK);
opReg(cUnit, kOpBlx, r3);
dvmCompilerClobberCallRegs(cUnit);
@@ -2653,10 +2647,6 @@
dvmCompilerFlushAllRegs(cUnit); /* Everything to home location */
loadValueDirectFixed(cUnit, rlSrc, r1);
dvmCompilerLockAllTemps(cUnit);
- const u2 *switchData =
- cUnit->method->insns + mir->offset + mir->dalvikInsn.vB;
- u2 size = switchData[1];
-
if (dalvikOpCode == OP_PACKED_SWITCH) {
LOAD_FUNC_ADDR(cUnit, r4PC, (int)findPackedSwitchIndex);
} else {
@@ -2848,7 +2838,6 @@
case OP_INVOKE_INTERFACE:
case OP_INVOKE_INTERFACE_RANGE: {
ArmLIR *predChainingCell = &labelList[bb->taken->id];
- int methodIndex = dInsn->vB;
/* Ensure that nothing is both live and dirty */
dvmCompilerFlushAllRegs(cUnit);
@@ -3219,8 +3208,6 @@
const InlineOperation* inLineTable = dvmGetInlineOpsTable();
int offset = offsetof(InterpState, retval);
int operation = dInsn->vB;
- int tReg1;
- int tReg2;
switch (operation) {
case INLINE_EMPTYINLINEMETHOD:
return false; /* Nop */
@@ -3473,7 +3460,6 @@
DecodedInstruction *dInsn = &mir->dalvikInsn;
const int lenOffset = offsetof(ArrayObject, length);
const int maxC = dInsn->arg[0];
- const int minC = dInsn->arg[1];
int regLength;
RegLocation rlArray = cUnit->regLocation[mir->dalvikInsn.vA];
RegLocation rlIdxEnd = cUnit->regLocation[mir->dalvikInsn.vC];
@@ -3522,7 +3508,6 @@
const int lenOffset = offsetof(ArrayObject, length);
const int regLength = dvmCompilerAllocTemp(cUnit);
const int maxC = dInsn->arg[0];
- const int minC = dInsn->arg[1];
RegLocation rlArray = cUnit->regLocation[mir->dalvikInsn.vA];
RegLocation rlIdxInit = cUnit->regLocation[mir->dalvikInsn.vB];
diff --git a/vm/compiler/codegen/arm/CodegenFactory.c b/vm/compiler/codegen/arm/CodegenFactory.c
index 824e1a0..157bd1f 100644
--- a/vm/compiler/codegen/arm/CodegenFactory.c
+++ b/vm/compiler/codegen/arm/CodegenFactory.c
@@ -112,7 +112,6 @@
static RegLocation loadValue(CompilationUnit *cUnit, RegLocation rlSrc,
RegisterClass opKind)
{
- RegisterInfo *pReg;
rlSrc = dvmCompilerEvalLoc(cUnit, rlSrc, opKind, false);
if (rlSrc.location == kLocDalvikFrame) {
loadValueDirect(cUnit, rlSrc, rlSrc.lowReg);
@@ -129,7 +128,6 @@
static void storeValue(CompilationUnit *cUnit, RegLocation rlDest,
RegLocation rlSrc)
{
- RegisterInfo *pRegLo;
LIR *defStart;
LIR *defEnd;
assert(!rlDest.wide);
@@ -179,8 +177,6 @@
static RegLocation loadValueWide(CompilationUnit *cUnit, RegLocation rlSrc,
RegisterClass opKind)
{
- RegisterInfo *pRegLo;
- RegisterInfo *pRegHi;
assert(rlSrc.wide);
rlSrc = dvmCompilerEvalLoc(cUnit, rlSrc, opKind, false);
if (rlSrc.location == kLocDalvikFrame) {
@@ -202,11 +198,8 @@
static void storeValueWide(CompilationUnit *cUnit, RegLocation rlDest,
RegLocation rlSrc)
{
- RegisterInfo *pRegLo;
- RegisterInfo *pRegHi;
LIR *defStart;
LIR *defEnd;
- bool srcFP = FPREG(rlSrc.lowReg) && FPREG(rlSrc.highReg);
assert(FPREG(rlSrc.lowReg)==FPREG(rlSrc.highReg));
assert(rlDest.wide);
assert(rlSrc.wide);
diff --git a/vm/compiler/codegen/arm/FP/Thumb2VFP.c b/vm/compiler/codegen/arm/FP/Thumb2VFP.c
index 9149646..b5bcf99 100644
--- a/vm/compiler/codegen/arm/FP/Thumb2VFP.c
+++ b/vm/compiler/codegen/arm/FP/Thumb2VFP.c
@@ -183,7 +183,6 @@
static bool genInlineSqrt(CompilationUnit *cUnit, MIR *mir)
{
ArmLIR *branch;
- DecodedInstruction *dInsn = &mir->dalvikInsn;
RegLocation rlSrc = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
RegLocation rlDest = inlinedTargetWide(cUnit, mir, true);
rlSrc = loadValueWide(cUnit, rlSrc, kFPReg);
@@ -212,7 +211,6 @@
{
bool isDouble;
int defaultResult;
- bool ltNaNBias;
RegLocation rlResult;
switch(mir->dalvikInsn.opCode) {
diff --git a/vm/compiler/codegen/arm/LocalOptimizations.c b/vm/compiler/codegen/arm/LocalOptimizations.c
index 85dfa8e..729486c 100644
--- a/vm/compiler/codegen/arm/LocalOptimizations.c
+++ b/vm/compiler/codegen/arm/LocalOptimizations.c
@@ -78,8 +78,6 @@
continue;
}
if (isDalvikStore(thisLIR)) {
- int dRegId = DECODE_ALIAS_INFO_REG(thisLIR->aliasInfo);
- int dRegIdHi = dRegId + DECODE_ALIAS_INFO_WIDE(thisLIR->aliasInfo);
int nativeRegId = thisLIR->operands[0];
ArmLIR *checkLIR;
int sinkDistance = 0;
@@ -208,7 +206,6 @@
if (isDalvikLoad(thisLIR)) {
int dRegId = DECODE_ALIAS_INFO_REG(thisLIR->aliasInfo);
- int dRegIdHi = dRegId + DECODE_ALIAS_INFO_WIDE(thisLIR->aliasInfo);
int nativeRegId = thisLIR->operands[0];
ArmLIR *checkLIR;
int hoistDistance = 0;
diff --git a/vm/compiler/codegen/arm/RallocUtil.c b/vm/compiler/codegen/arm/RallocUtil.c
index e357ba6..80ce968 100644
--- a/vm/compiler/codegen/arm/RallocUtil.c
+++ b/vm/compiler/codegen/arm/RallocUtil.c
@@ -463,14 +463,6 @@
dvmCompilerAbort(cUnit);
}
-static void lockArgRegs(CompilationUnit *cUnit)
-{
- dvmCompilerLockTemp(cUnit, r0);
- dvmCompilerLockTemp(cUnit, r1);
- dvmCompilerLockTemp(cUnit, r2);
- dvmCompilerLockTemp(cUnit, r3);
-}
-
/* Clobber all regs that might be used by an external C call */
extern void dvmCompilerClobberCallRegs(CompilationUnit *cUnit)
{
@@ -698,12 +690,6 @@
infoHi->partner = lowReg;
}
-static void markRegSingle(CompilationUnit *cUnit, int reg)
-{
- RegisterInfo *info = getRegInfo(cUnit, reg);
- info->pair = false;
-}
-
extern void dvmCompilerMarkClean(CompilationUnit *cUnit, int reg)
{
RegisterInfo *info = getRegInfo(cUnit, reg);
@@ -722,13 +708,6 @@
info->inUse = true;
}
-/* Return true if live & dirty */
-static bool isDirty(CompilationUnit *cUnit, int reg)
-{
- RegisterInfo *info = getRegInfo(cUnit, reg);
- return (info && info->live && info->dirty);
-}
-
void copyRegInfo(CompilationUnit *cUnit, int newReg, int oldReg)
{
RegisterInfo *newInfo = getRegInfo(cUnit, newReg);
@@ -870,7 +849,6 @@
extern RegLocation dvmCompilerEvalLoc(CompilationUnit *cUnit, RegLocation loc,
int regClass, bool update)
{
- RegisterInfo *infoLo = NULL;
int newReg;
if (loc.wide)
return evalLocWide(cUnit, loc, regClass, update);
diff --git a/vm/compiler/codegen/arm/Thumb2/Factory.c b/vm/compiler/codegen/arm/Thumb2/Factory.c
index 0141a0f..c7b52fd 100644
--- a/vm/compiler/codegen/arm/Thumb2/Factory.c
+++ b/vm/compiler/codegen/arm/Thumb2/Factory.c
@@ -23,10 +23,8 @@
*/
static int coreTemps[] = {r0, r1, r2, r3, r4PC, r7, r8, r9, r10, r11, r12};
-static int corePreserved[] = {};
static int fpTemps[] = {fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23,
fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31};
-static int fpPreserved[] = {};
static int encodeImmSingle(int value)
{
@@ -579,7 +577,6 @@
static ArmLIR *opRegImm(CompilationUnit *cUnit, OpKind op, int rDestSrc1,
int value)
{
- ArmLIR *res;
bool neg = (value < 0);
int absValue = (neg) ? -value : value;
bool shortForm = (((absValue & 0xff) == absValue) && LOWREG(rDestSrc1));
@@ -813,7 +810,6 @@
ArmOpCode opCode = kThumbBkpt;
bool shortForm = false;
bool thumb2Form = (displacement < 4092 && displacement >= 0);
- int shortMax = 128;
bool allLowRegs = (LOWREG(rBase) && LOWREG(rDest));
int encodedDisp = displacement;
@@ -948,7 +944,6 @@
ArmOpCode opCode = kThumbBkpt;
bool shortForm = false;
bool thumb2Form = (displacement < 4092 && displacement >= 0);
- int shortMax = 128;
bool allLowRegs = (LOWREG(rBase) && LOWREG(rSrc));
int encodedDisp = displacement;
diff --git a/vm/compiler/codegen/arm/Thumb2/Gen.c b/vm/compiler/codegen/arm/Thumb2/Gen.c
index 1782bec..de75be7 100644
--- a/vm/compiler/codegen/arm/Thumb2/Gen.c
+++ b/vm/compiler/codegen/arm/Thumb2/Gen.c
@@ -87,7 +87,6 @@
void dvmCompilerInitializeRegAlloc(CompilationUnit *cUnit)
{
- int i;
int numTemps = sizeof(coreTemps)/sizeof(int);
int numFPTemps = sizeof(fpTemps)/sizeof(int);
RegisterPool *pool = dvmCompilerNew(sizeof(*pool), true);
@@ -193,7 +192,6 @@
static void genMonitorEnter(CompilationUnit *cUnit, MIR *mir)
{
RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
- bool enter = (mir->dalvikInsn.opCode == OP_MONITOR_ENTER);
ArmLIR *target;
ArmLIR *hopTarget;
ArmLIR *branch;