Re-organize target-independent JIT code.
Most of CodegenFactory.c is at a high-enough abstraction level to reuse
for other targets. This CL moves the target-depending routines into a
new source file (ArchFactory.c) and what's left up a level into the
target-independent directory.
Change-Id: I792d5dc6b2dc8aa6aaa384039da464db2c766123
diff --git a/vm/compiler/codegen/arm/CodegenFactory.c b/vm/compiler/codegen/CodegenFactory.c
similarity index 72%
rename from vm/compiler/codegen/arm/CodegenFactory.c
rename to vm/compiler/codegen/CodegenFactory.c
index 1de9f90..aad6512 100644
--- a/vm/compiler/codegen/arm/CodegenFactory.c
+++ b/vm/compiler/codegen/CodegenFactory.c
@@ -15,25 +15,31 @@
*/
/*
- * This file contains codegen and support common to all supported
- * ARM variants. It is included by:
+ * This file contains target-independent codegen and support, and is
+ * included by:
*
- * Codegen-$(TARGET_ARCH_VARIANT).c
+ * $(TARGET_ARCH)/Codegen-$(TARGET_ARCH_VARIANT).c
*
* which combines this common code with specific support found in the
- * applicable directory below this one.
+ * applicable directories below this one.
+ *
+ * Prior to including this file, TGT_LIR should be #defined.
+ * For example, for arm:
+ * #define TGT_LIR ArmLIR
+ * and for x86:
+ * #define TGT_LIR X86LIR
*/
/* Load a word at base + displacement. Displacement must be word multiple */
-static ArmLIR *loadWordDisp(CompilationUnit *cUnit, int rBase, int displacement,
- int rDest)
+static TGT_LIR *loadWordDisp(CompilationUnit *cUnit, int rBase,
+ int displacement, int rDest)
{
return loadBaseDisp(cUnit, NULL, rBase, displacement, rDest, kWord,
INVALID_SREG);
}
-static ArmLIR *storeWordDisp(CompilationUnit *cUnit, int rBase,
+static TGT_LIR *storeWordDisp(CompilationUnit *cUnit, int rBase,
int displacement, int rSrc)
{
return storeBaseDisp(cUnit, rBase, displacement, rSrc, kWord);
@@ -45,7 +51,7 @@
* register liveness. That is the responsibility of the caller.
*/
static void loadValueDirect(CompilationUnit *cUnit, RegLocation rlSrc,
- int reg1)
+ int reg1)
{
rlSrc = dvmCompilerUpdateLoc(cUnit, rlSrc);
if (rlSrc.location == kLocPhysReg) {
@@ -196,7 +202,7 @@
}
static void storeValueWide(CompilationUnit *cUnit, RegLocation rlDest,
- RegLocation rlSrc)
+ RegLocation rlSrc)
{
LIR *defStart;
LIR *defEnd;
@@ -257,91 +263,3 @@
}
}
}
-
-/*
- * Perform a "reg cmp imm" operation and jump to the PCR region if condition
- * satisfies.
- */
-static ArmLIR *genRegImmCheck(CompilationUnit *cUnit,
- ArmConditionCode cond, int reg,
- int checkValue, int dOffset,
- ArmLIR *pcrLabel)
-{
- ArmLIR *branch = genCmpImmBranch(cUnit, cond, reg, checkValue);
- return genCheckCommon(cUnit, dOffset, branch, pcrLabel);
-}
-
-/*
- * Perform null-check on a register. sReg is the ssa register being checked,
- * and mReg is the machine register holding the actual value. If internal state
- * indicates that sReg has been checked before the check request is ignored.
- */
-static ArmLIR *genNullCheck(CompilationUnit *cUnit, int sReg, int mReg,
- int dOffset, ArmLIR *pcrLabel)
-{
- /* This particular Dalvik register has been null-checked */
- if (dvmIsBitSet(cUnit->regPool->nullCheckedRegs, sReg)) {
- return pcrLabel;
- }
- dvmSetBit(cUnit->regPool->nullCheckedRegs, sReg);
- return genRegImmCheck(cUnit, kArmCondEq, mReg, 0, dOffset, pcrLabel);
-}
-
-
-
-/*
- * Perform a "reg cmp reg" operation and jump to the PCR region if condition
- * satisfies.
- */
-static ArmLIR *genRegRegCheck(CompilationUnit *cUnit,
- ArmConditionCode cond,
- int reg1, int reg2, int dOffset,
- ArmLIR *pcrLabel)
-{
- ArmLIR *res;
- res = opRegReg(cUnit, kOpCmp, reg1, reg2);
- ArmLIR *branch = opCondBranch(cUnit, cond);
- genCheckCommon(cUnit, dOffset, branch, pcrLabel);
- return res;
-}
-
-/*
- * Perform zero-check on a register. Similar to genNullCheck but the value being
- * checked does not have a corresponding Dalvik register.
- */
-static ArmLIR *genZeroCheck(CompilationUnit *cUnit, int mReg,
- int dOffset, ArmLIR *pcrLabel)
-{
- return genRegImmCheck(cUnit, kArmCondEq, mReg, 0, dOffset, pcrLabel);
-}
-
-/* Perform bound check on two registers */
-static ArmLIR *genBoundsCheck(CompilationUnit *cUnit, int rIndex,
- int rBound, int dOffset, ArmLIR *pcrLabel)
-{
- return genRegRegCheck(cUnit, kArmCondCs, rIndex, rBound, dOffset,
- pcrLabel);
-}
-
-/*
- * Jump to the out-of-line handler in ARM mode to finish executing the
- * remaining of more complex instructions.
- */
-static void genDispatchToHandler(CompilationUnit *cUnit, TemplateOpCode opCode)
-{
- /*
- * NOTE - In practice BLX only needs one operand, but since the assembler
- * may abort itself and retry due to other out-of-range conditions we
- * cannot really use operand[0] to store the absolute target address since
- * it may get clobbered by the final relative offset. Therefore,
- * we fake BLX_1 is a two operand instruction and the absolute target
- * address is stored in operand[1].
- */
- dvmCompilerClobberHandlerRegs(cUnit);
- newLIR2(cUnit, kThumbBlx1,
- (int) gDvmJit.codeCache + templateEntryOffsets[opCode],
- (int) gDvmJit.codeCache + templateEntryOffsets[opCode]);
- newLIR2(cUnit, kThumbBlx2,
- (int) gDvmJit.codeCache + templateEntryOffsets[opCode],
- (int) gDvmJit.codeCache + templateEntryOffsets[opCode]);
-}
diff --git a/vm/compiler/codegen/arm/ArchFactory.c b/vm/compiler/codegen/arm/ArchFactory.c
new file mode 100644
index 0000000..1fe0412
--- /dev/null
+++ b/vm/compiler/codegen/arm/ArchFactory.c
@@ -0,0 +1,109 @@
+/*
+ * Copyright (C) 2010 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ * This file contains arm-specific codegen factory support.
+ * It is included by
+ *
+ * Codegen-$(TARGET_ARCH_VARIANT).c
+ *
+ */
+
+/*
+ * Perform a "reg cmp imm" operation and jump to the PCR region if condition
+ * satisfies.
+ */
+static TGT_LIR *genRegImmCheck(CompilationUnit *cUnit,
+ ArmConditionCode cond, int reg,
+ int checkValue, int dOffset,
+ TGT_LIR *pcrLabel)
+{
+ TGT_LIR *branch = genCmpImmBranch(cUnit, cond, reg, checkValue);
+ return genCheckCommon(cUnit, dOffset, branch, pcrLabel);
+}
+
+/*
+ * Perform null-check on a register. sReg is the ssa register being checked,
+ * and mReg is the machine register holding the actual value. If internal state
+ * indicates that sReg has been checked before the check request is ignored.
+ */
+static TGT_LIR *genNullCheck(CompilationUnit *cUnit, int sReg, int mReg,
+ int dOffset, TGT_LIR *pcrLabel)
+{
+ /* This particular Dalvik register has been null-checked */
+ if (dvmIsBitSet(cUnit->regPool->nullCheckedRegs, sReg)) {
+ return pcrLabel;
+ }
+ dvmSetBit(cUnit->regPool->nullCheckedRegs, sReg);
+ return genRegImmCheck(cUnit, kArmCondEq, mReg, 0, dOffset, pcrLabel);
+}
+
+/*
+ * Perform a "reg cmp reg" operation and jump to the PCR region if condition
+ * satisfies.
+ */
+static TGT_LIR *genRegRegCheck(CompilationUnit *cUnit,
+ ArmConditionCode cond,
+ int reg1, int reg2, int dOffset,
+ TGT_LIR *pcrLabel)
+{
+ TGT_LIR *res;
+ res = opRegReg(cUnit, kOpCmp, reg1, reg2);
+ TGT_LIR *branch = opCondBranch(cUnit, cond);
+ genCheckCommon(cUnit, dOffset, branch, pcrLabel);
+ return res;
+}
+
+/*
+ * Perform zero-check on a register. Similar to genNullCheck but the value being
+ * checked does not have a corresponding Dalvik register.
+ */
+static TGT_LIR *genZeroCheck(CompilationUnit *cUnit, int mReg,
+ int dOffset, TGT_LIR *pcrLabel)
+{
+ return genRegImmCheck(cUnit, kArmCondEq, mReg, 0, dOffset, pcrLabel);
+}
+
+/* Perform bound check on two registers */
+static TGT_LIR *genBoundsCheck(CompilationUnit *cUnit, int rIndex,
+ int rBound, int dOffset, TGT_LIR *pcrLabel)
+{
+ return genRegRegCheck(cUnit, kArmCondCs, rIndex, rBound, dOffset,
+ pcrLabel);
+}
+
+/*
+ * Jump to the out-of-line handler in ARM mode to finish executing the
+ * remaining of more complex instructions.
+ */
+static void genDispatchToHandler(CompilationUnit *cUnit, TemplateOpCode opCode)
+{
+ /*
+ * NOTE - In practice BLX only needs one operand, but since the assembler
+ * may abort itself and retry due to other out-of-range conditions we
+ * cannot really use operand[0] to store the absolute target address since
+ * it may get clobbered by the final relative offset. Therefore,
+ * we fake BLX_1 is a two operand instruction and the absolute target
+ * address is stored in operand[1].
+ */
+ dvmCompilerClobberHandlerRegs(cUnit);
+ newLIR2(cUnit, kThumbBlx1,
+ (int) gDvmJit.codeCache + templateEntryOffsets[opCode],
+ (int) gDvmJit.codeCache + templateEntryOffsets[opCode]);
+ newLIR2(cUnit, kThumbBlx2,
+ (int) gDvmJit.codeCache + templateEntryOffsets[opCode],
+ (int) gDvmJit.codeCache + templateEntryOffsets[opCode]);
+}
diff --git a/vm/compiler/codegen/arm/armv5te-vfp/Codegen.c b/vm/compiler/codegen/arm/armv5te-vfp/Codegen.c
index 2554754..35fc092 100644
--- a/vm/compiler/codegen/arm/armv5te-vfp/Codegen.c
+++ b/vm/compiler/codegen/arm/armv5te-vfp/Codegen.c
@@ -15,6 +15,7 @@
*/
#define _CODEGEN_C
#define _ARMV5TE_VFP
+#define TGT_LIR ArmLIR
#include "Dalvik.h"
#include "interp/InterpDefs.h"
@@ -28,13 +29,15 @@
#include "compiler/Loop.h"
#include "ArchVariant.h"
-/* Architectural independent building blocks */
+/* Arm codegen building blocks */
#include "../CodegenCommon.c"
/* Thumb-specific factory utilities */
#include "../Thumb/Factory.c"
-/* Factory utilities dependent on arch-specific features */
-#include "../CodegenFactory.c"
+/* Target independent factory utilities */
+#include "../../CodegenFactory.c"
+/* Arm-specific factory utilities */
+#include "../ArchFactory.c"
/* Thumb-specific codegen routines */
#include "../Thumb/Gen.c"
diff --git a/vm/compiler/codegen/arm/armv5te/Codegen.c b/vm/compiler/codegen/arm/armv5te/Codegen.c
index 37d7028..aad36ae 100644
--- a/vm/compiler/codegen/arm/armv5te/Codegen.c
+++ b/vm/compiler/codegen/arm/armv5te/Codegen.c
@@ -15,6 +15,7 @@
*/
#define _CODEGEN_C
#define _ARMV5TE
+#define TGT_LIR ArmLIR
#include "Dalvik.h"
#include "interp/InterpDefs.h"
@@ -28,13 +29,15 @@
#include "compiler/Loop.h"
#include "ArchVariant.h"
-/* Architectural independent building blocks */
+/* Arm codegen building blocks */
#include "../CodegenCommon.c"
-/* Architectural independent building blocks */
+/* Thumb-specific building blocks */
#include "../Thumb/Factory.c"
-/* Factory utilities dependent on arch-specific features */
-#include "../CodegenFactory.c"
+/* Target independent factory utilities */
+#include "../../CodegenFactory.c"
+/* Arm-specific factory utilities */
+#include "../ArchFactory.c"
/* Thumb-specific codegen routines */
#include "../Thumb/Gen.c"
diff --git a/vm/compiler/codegen/arm/armv7-a-neon/Codegen.c b/vm/compiler/codegen/arm/armv7-a-neon/Codegen.c
index 2cf8e53..8b0bb91 100644
--- a/vm/compiler/codegen/arm/armv7-a-neon/Codegen.c
+++ b/vm/compiler/codegen/arm/armv7-a-neon/Codegen.c
@@ -15,6 +15,7 @@
*/
#define _CODEGEN_C
#define _ARMV7_A_NEON
+#define TGT_LIR ArmLIR
#include "Dalvik.h"
#include "interp/InterpDefs.h"
@@ -28,13 +29,15 @@
#include "compiler/Loop.h"
#include "ArchVariant.h"
-/* Architectural independent building blocks */
+/* Arm codegen building blocks */
#include "../CodegenCommon.c"
/* Thumb2-specific factory utilities */
#include "../Thumb2/Factory.c"
-/* Factory utilities dependent on arch-specific features */
-#include "../CodegenFactory.c"
+/* Target indepedent factory utilities */
+#include "../../CodegenFactory.c"
+/* Arm-specific factory utilities */
+#include "../ArchFactory.c"
/* Thumb2-specific codegen routines */
#include "../Thumb2/Gen.c"
diff --git a/vm/compiler/codegen/arm/armv7-a/Codegen.c b/vm/compiler/codegen/arm/armv7-a/Codegen.c
index 14d923f..9626492 100644
--- a/vm/compiler/codegen/arm/armv7-a/Codegen.c
+++ b/vm/compiler/codegen/arm/armv7-a/Codegen.c
@@ -15,6 +15,7 @@
*/
#define _CODEGEN_C
#define _ARMV7_A
+#define TGT_LIR
#include "Dalvik.h"
#include "interp/InterpDefs.h"
@@ -28,13 +29,15 @@
#include "compiler/Loop.h"
#include "ArchVariant.h"
-/* Architectural independent building blocks */
+/* Arm codegen building blocks */
#include "../CodegenCommon.c"
/* Thumb2-specific factory utilities */
#include "../Thumb2/Factory.c"
-/* Factory utilities dependent on arch-specific features */
-#include "../CodegenFactory.c"
+/* Target independent factory utilities */
+#include "../../CodegenFactory.c"
+/* Arm-specific factory utilities */
+#include "../ArchFactory.c"
/* Thumb2-specific codegen routines */
#include "../Thumb2/Gen.c"