Rename some instruction/opcode types and utilities.
A lot of this is more about properties of opcodes as opposed to
inspecting instructions per se, and the new naming attempts to
make it clear what is being queried and what sort of data is being
returned.
Change-Id: Ice6f9f2ebf4f1cfa8c99597419aa13d1134a33b2
diff --git a/vm/compiler/Frontend.c b/vm/compiler/Frontend.c
index 9015719..a44c489 100644
--- a/vm/compiler/Frontend.c
+++ b/vm/compiler/Frontend.c
@@ -34,7 +34,7 @@
if (opcode == OP_NOP && instr != 0) {
return 0;
} else {
- insnWidth = dexGetInstrWidth(opcode);
+ insnWidth = dexGetWidthFromOpcode(opcode);
if (insnWidth < 0) {
insnWidth = -insnWidth;
}
@@ -205,7 +205,7 @@
static int analyzeInlineTarget(DecodedInstruction *dalvikInsn, int attributes,
int offset)
{
- int flags = dexGetInstrFlags(dalvikInsn->opcode);
+ int flags = dexGetFlagsFromOpcode(dalvikInsn->opcode);
int dalvikOpcode = dalvikInsn->opcode;
if (flags & kInstrInvoke) {
@@ -569,7 +569,7 @@
dvmCompilerAppendMIR(curBB, insn);
cUnit.numInsts++;
- int flags = dexGetInstrFlags(insn->dalvikInsn.opcode);
+ int flags = dexGetFlagsFromOpcode(insn->dalvikInsn.opcode);
if (flags & kInstrInvoke) {
assert(numInsts == 1);
@@ -641,7 +641,7 @@
/* Link the taken and fallthrough blocks */
BasicBlock *searchBB;
- int flags = dexGetInstrFlags(lastInsn->dalvikInsn.opcode);
+ int flags = dexGetFlagsFromOpcode(lastInsn->dalvikInsn.opcode);
if (flags & kInstrInvoke) {
cUnit.hasInvoke = true;
@@ -1201,7 +1201,7 @@
* aligned to 4-byte boundary (alignment instruction to be
* inserted later.
*/
- if (dexGetInstrFlags(curBB->lastMIRInsn->dalvikInsn.opcode)
+ if (dexGetFlagsFromOpcode(curBB->lastMIRInsn->dalvikInsn.opcode)
& kInstrInvoke) {
newBB->isFallThroughFromInvoke = true;
}
diff --git a/vm/compiler/InlineTransformation.c b/vm/compiler/InlineTransformation.c
index a632d6c..0b1330f 100644
--- a/vm/compiler/InlineTransformation.c
+++ b/vm/compiler/InlineTransformation.c
@@ -85,7 +85,7 @@
/* Now setup the Dalvik instruction with converted src/dst registers */
newGetterMIR->dalvikInsn = getterInsn;
- newGetterMIR->width = dexGetInstrWidth(getterInsn.opcode);
+ newGetterMIR->width = dexGetWidthFromOpcode(getterInsn.opcode);
newGetterMIR->OptimizationFlags |= MIR_CALLEE;
@@ -164,7 +164,7 @@
/* Now setup the Dalvik instruction with converted src/dst registers */
newSetterMIR->dalvikInsn = setterInsn;
- newSetterMIR->width = dexGetInstrWidth(setterInsn.opcode);
+ newSetterMIR->width = dexGetWidthFromOpcode(setterInsn.opcode);
newSetterMIR->OptimizationFlags |= MIR_CALLEE;
@@ -296,7 +296,7 @@
continue;
MIR *lastMIRInsn = bb->lastMIRInsn;
int opcode = lastMIRInsn->dalvikInsn.opcode;
- int flags = dexGetInstrFlags(opcode);
+ int flags = dexGetFlagsFromOpcode(opcode);
/* No invoke - continue */
if ((flags & kInstrInvoke) == 0)
diff --git a/vm/compiler/Loop.c b/vm/compiler/Loop.c
index 13e133c..c03d6f5 100644
--- a/vm/compiler/Loop.c
+++ b/vm/compiler/Loop.c
@@ -311,7 +311,7 @@
/* Skip extended MIR instructions */
if (dInsn->opcode >= kNumDalvikInstructions) continue;
- int instrFlags = dexGetInstrFlags(dInsn->opcode);
+ int instrFlags = dexGetFlagsFromOpcode(dInsn->opcode);
/* Instruction is clean */
if ((instrFlags & kInstrCanThrow) == 0) continue;
diff --git a/vm/compiler/codegen/arm/CodegenDriver.c b/vm/compiler/codegen/arm/CodegenDriver.c
index 9892f56..55fee0e 100644
--- a/vm/compiler/codegen/arm/CodegenDriver.c
+++ b/vm/compiler/codegen/arm/CodegenDriver.c
@@ -1233,7 +1233,7 @@
*/
static void genInterpSingleStep(CompilationUnit *cUnit, MIR *mir)
{
- int flags = dexGetInstrFlags(mir->dalvikInsn.opcode);
+ int flags = dexGetFlagsFromOpcode(mir->dalvikInsn.opcode);
int flagsToCheck = kInstrCanBranch | kInstrCanSwitch | kInstrCanReturn |
kInstrCanThrow;
@@ -1283,7 +1283,7 @@
if (isEnter) {
/* Get dPC of next insn */
loadConstant(cUnit, r4PC, (int)(cUnit->method->insns + mir->offset +
- dexGetInstrWidth(OP_MONITOR_ENTER)));
+ dexGetWidthFromOpcode(OP_MONITOR_ENTER)));
#if defined(WITH_DEADLOCK_PREDICTION)
genDispatchToHandler(cUnit, TEMPLATE_MONITOR_ENTER_DEBUG);
#else
@@ -1297,7 +1297,7 @@
ArmLIR *branchOver = genCmpImmBranch(cUnit, kArmCondNe, r0, 0);
loadConstant(cUnit, r0,
(int) (cUnit->method->insns + mir->offset +
- dexGetInstrWidth(OP_MONITOR_EXIT)));
+ dexGetWidthFromOpcode(OP_MONITOR_EXIT)));
genDispatchToHandler(cUnit, TEMPLATE_THROW_EXCEPTION_COMMON);
ArmLIR *target = newLIR0(cUnit, kArmPseudoTargetLabel);
target->defMask = ENCODE_ALL;
@@ -4097,7 +4097,7 @@
Opcode dalvikOpcode = mir->dalvikInsn.opcode;
- InstructionFormat dalvikFormat = dexGetInstrFormat(dalvikOpcode);
+ InstructionFormat dalvikFormat = dexGetFormatFromOpcode(dalvikOpcode);
char *note;
if (mir->OptimizationFlags & MIR_INLINED) {
note = " (I)";
diff --git a/vm/compiler/codegen/arm/Thumb2/Gen.c b/vm/compiler/codegen/arm/Thumb2/Gen.c
index f1f6df3..825b271 100644
--- a/vm/compiler/codegen/arm/Thumb2/Gen.c
+++ b/vm/compiler/codegen/arm/Thumb2/Gen.c
@@ -225,7 +225,7 @@
/* Get dPC of next insn */
loadConstant(cUnit, r4PC, (int)(cUnit->method->insns + mir->offset +
- dexGetInstrWidth(OP_MONITOR_ENTER)));
+ dexGetWidthFromOpcode(OP_MONITOR_ENTER)));
// Export PC (part 2)
newLIR3(cUnit, kThumb2StrRRI8Predec, r3, rFP,
sizeof(StackSaveArea) -
@@ -289,7 +289,7 @@
ArmLIR *branchOver = genCmpImmBranch(cUnit, kArmCondNe, r0, 0);
loadConstant(cUnit, r0,
(int) (cUnit->method->insns + mir->offset +
- dexGetInstrWidth(OP_MONITOR_EXIT)));
+ dexGetWidthFromOpcode(OP_MONITOR_EXIT)));
genDispatchToHandler(cUnit, TEMPLATE_THROW_EXCEPTION_COMMON);
// Resume here