| Ben Cheng | ba4fc8b | 2009-06-01 13:00:29 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2009 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | #include "Dalvik.h" |
| 18 | #include "CompilerInternals.h" |
| 19 | |
| 20 | /* Allocate a new basic block */ |
| 21 | BasicBlock *dvmCompilerNewBB(BBType blockType) |
| 22 | { |
| 23 | BasicBlock *bb = dvmCompilerNew(sizeof(BasicBlock), true); |
| 24 | bb->blockType = blockType; |
| 25 | return bb; |
| 26 | } |
| 27 | |
| 28 | /* Insert an MIR instruction to the end of a basic block */ |
| 29 | void dvmCompilerAppendMIR(BasicBlock *bb, MIR *mir) |
| 30 | { |
| 31 | if (bb->firstMIRInsn == NULL) { |
| Ben Cheng | 4238ec2 | 2009-08-24 16:32:22 -0700 | [diff] [blame] | 32 | assert(bb->lastMIRInsn == NULL); |
| Ben Cheng | ba4fc8b | 2009-06-01 13:00:29 -0700 | [diff] [blame] | 33 | bb->lastMIRInsn = bb->firstMIRInsn = mir; |
| 34 | mir->prev = mir->next = NULL; |
| 35 | } else { |
| 36 | bb->lastMIRInsn->next = mir; |
| 37 | mir->prev = bb->lastMIRInsn; |
| 38 | mir->next = NULL; |
| 39 | bb->lastMIRInsn = mir; |
| 40 | } |
| 41 | } |
| 42 | |
| Ben Cheng | 4238ec2 | 2009-08-24 16:32:22 -0700 | [diff] [blame] | 43 | /* Insert an MIR instruction to the head of a basic block */ |
| 44 | void dvmCompilerPrependMIR(BasicBlock *bb, MIR *mir) |
| 45 | { |
| 46 | if (bb->firstMIRInsn == NULL) { |
| 47 | assert(bb->lastMIRInsn == NULL); |
| 48 | bb->lastMIRInsn = bb->firstMIRInsn = mir; |
| 49 | mir->prev = mir->next = NULL; |
| 50 | } else { |
| 51 | bb->firstMIRInsn->prev = mir; |
| 52 | mir->next = bb->firstMIRInsn; |
| 53 | mir->prev = NULL; |
| 54 | bb->firstMIRInsn = mir; |
| 55 | } |
| 56 | } |
| 57 | |
| Ben Cheng | ba4fc8b | 2009-06-01 13:00:29 -0700 | [diff] [blame] | 58 | /* |
| 59 | * Append an LIR instruction to the LIR list maintained by a compilation |
| 60 | * unit |
| 61 | */ |
| 62 | void dvmCompilerAppendLIR(CompilationUnit *cUnit, LIR *lir) |
| 63 | { |
| 64 | if (cUnit->firstLIRInsn == NULL) { |
| 65 | assert(cUnit->lastLIRInsn == NULL); |
| 66 | cUnit->lastLIRInsn = cUnit->firstLIRInsn = lir; |
| 67 | lir->prev = lir->next = NULL; |
| 68 | } else { |
| 69 | cUnit->lastLIRInsn->next = lir; |
| 70 | lir->prev = cUnit->lastLIRInsn; |
| 71 | lir->next = NULL; |
| 72 | cUnit->lastLIRInsn = lir; |
| 73 | } |
| 74 | } |
| Ben Cheng | e9695e5 | 2009-06-16 16:11:47 -0700 | [diff] [blame] | 75 | |
| 76 | /* |
| 77 | * Insert an LIR instruction before the current instruction, which cannot be the |
| 78 | * first instruction. |
| 79 | * |
| 80 | * prevLIR <-> newLIR <-> currentLIR |
| 81 | */ |
| 82 | void dvmCompilerInsertLIRBefore(LIR *currentLIR, LIR *newLIR) |
| 83 | { |
| 84 | if (currentLIR->prev == NULL) |
| 85 | dvmAbort(); |
| 86 | LIR *prevLIR = currentLIR->prev; |
| 87 | |
| 88 | prevLIR->next = newLIR; |
| 89 | newLIR->prev = prevLIR; |
| 90 | newLIR->next = currentLIR; |
| 91 | currentLIR->prev = newLIR; |
| 92 | } |
| Ben Cheng | dcf3e5d | 2009-09-11 13:42:05 -0700 | [diff] [blame] | 93 | |
| 94 | /* |
| 95 | * Insert an LIR instruction after the current instruction, which cannot be the |
| 96 | * first instruction. |
| 97 | * |
| 98 | * currentLIR -> newLIR -> oldNext |
| 99 | */ |
| 100 | void dvmCompilerInsertLIRAfter(LIR *currentLIR, LIR *newLIR) |
| 101 | { |
| 102 | newLIR->prev = currentLIR; |
| 103 | newLIR->next = currentLIR->next; |
| 104 | currentLIR->next = newLIR; |
| 105 | newLIR->next->prev = newLIR; |
| 106 | } |