mads.s.ager@gmail.com | 9a4089a | 2008-09-01 08:55:01 +0000 | [diff] [blame] | 1 | // Copyright (c) 1994-2006 Sun Microsystems Inc. |
| 2 | // All Rights Reserved. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 3 | // |
mads.s.ager@gmail.com | 9a4089a | 2008-09-01 08:55:01 +0000 | [diff] [blame] | 4 | // Redistribution and use in source and binary forms, with or without |
| 5 | // modification, are permitted provided that the following conditions |
| 6 | // are met: |
| 7 | // |
| 8 | // - Redistributions of source code must retain the above copyright notice, |
| 9 | // this list of conditions and the following disclaimer. |
| 10 | // |
| 11 | // - Redistribution in binary form must reproduce the above copyright |
| 12 | // notice, this list of conditions and the following disclaimer in the |
| 13 | // documentation and/or other materials provided with the |
| 14 | // distribution. |
| 15 | // |
| 16 | // - Neither the name of Sun Microsystems or the names of contributors may |
| 17 | // be used to endorse or promote products derived from this software without |
| 18 | // specific prior written permission. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 19 | // |
| 20 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 21 | // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
mads.s.ager@gmail.com | 9a4089a | 2008-09-01 08:55:01 +0000 | [diff] [blame] | 22 | // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
| 23 | // FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
| 24 | // COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 25 | // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 26 | // (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| 27 | // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 28 | // HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
| 29 | // STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 30 | // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED |
| 31 | // OF THE POSSIBILITY OF SUCH DAMAGE. |
| 32 | |
sgjesse@chromium.org | b302e56 | 2010-02-03 11:26:59 +0000 | [diff] [blame] | 33 | // The original source code covered by the above license above has been |
| 34 | // modified significantly by Google Inc. |
vegorov@chromium.org | 74f333b | 2011-04-06 11:17:46 +0000 | [diff] [blame^] | 35 | // Copyright 2011 the V8 project authors. All rights reserved. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 36 | |
| 37 | #include "v8.h" |
| 38 | |
erik.corry@gmail.com | 9dfbea4 | 2010-05-21 12:58:28 +0000 | [diff] [blame] | 39 | #if defined(V8_TARGET_ARCH_ARM) |
| 40 | |
ager@chromium.org | 3a37e9b | 2009-04-27 09:26:21 +0000 | [diff] [blame] | 41 | #include "arm/assembler-arm-inl.h" |
mads.s.ager@gmail.com | 9a4089a | 2008-09-01 08:55:01 +0000 | [diff] [blame] | 42 | #include "serialize.h" |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 43 | |
kasperl@chromium.org | 71affb5 | 2009-05-26 05:44:31 +0000 | [diff] [blame] | 44 | namespace v8 { |
| 45 | namespace internal { |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 46 | |
kmillikin@chromium.org | c36ce6e | 2011-04-04 08:25:31 +0000 | [diff] [blame] | 47 | #ifdef DEBUG |
| 48 | bool CpuFeatures::initialized_ = false; |
| 49 | #endif |
| 50 | unsigned CpuFeatures::supported_ = 0; |
| 51 | unsigned CpuFeatures::found_by_runtime_probing_ = 0; |
| 52 | |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 53 | |
| 54 | #ifdef __arm__ |
| 55 | static uint64_t CpuFeaturesImpliedByCompiler() { |
| 56 | uint64_t answer = 0; |
| 57 | #ifdef CAN_USE_ARMV7_INSTRUCTIONS |
| 58 | answer |= 1u << ARMv7; |
| 59 | #endif // def CAN_USE_ARMV7_INSTRUCTIONS |
| 60 | // If the compiler is allowed to use VFP then we can use VFP too in our code |
| 61 | // generation even when generating snapshots. This won't work for cross |
| 62 | // compilation. |
| 63 | #if defined(__VFP_FP__) && !defined(__SOFTFP__) |
| 64 | answer |= 1u << VFP3; |
| 65 | #endif // defined(__VFP_FP__) && !defined(__SOFTFP__) |
| 66 | #ifdef CAN_USE_VFP_INSTRUCTIONS |
| 67 | answer |= 1u << VFP3; |
| 68 | #endif // def CAN_USE_VFP_INSTRUCTIONS |
| 69 | return answer; |
| 70 | } |
| 71 | #endif // def __arm__ |
| 72 | |
| 73 | |
kmillikin@chromium.org | c36ce6e | 2011-04-04 08:25:31 +0000 | [diff] [blame] | 74 | void CpuFeatures::Probe() { |
| 75 | ASSERT(!initialized_); |
| 76 | #ifdef DEBUG |
| 77 | initialized_ = true; |
| 78 | #endif |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 79 | #ifndef __arm__ |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 80 | // For the simulator=arm build, use VFP when FLAG_enable_vfp3 is enabled. |
| 81 | if (FLAG_enable_vfp3) { |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 82 | supported_ |= 1u << VFP3; |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 83 | } |
| 84 | // For the simulator=arm build, use ARMv7 when FLAG_enable_armv7 is enabled |
| 85 | if (FLAG_enable_armv7) { |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 86 | supported_ |= 1u << ARMv7; |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 87 | } |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 88 | #else // def __arm__ |
kmillikin@chromium.org | c36ce6e | 2011-04-04 08:25:31 +0000 | [diff] [blame] | 89 | if (Serializer::enabled()) { |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 90 | supported_ |= OS::CpuFeaturesImpliedByPlatform(); |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 91 | supported_ |= CpuFeaturesImpliedByCompiler(); |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 92 | return; // No features if we might serialize. |
| 93 | } |
| 94 | |
| 95 | if (OS::ArmCpuHasFeature(VFP3)) { |
| 96 | // This implementation also sets the VFP flags if |
| 97 | // runtime detection of VFP returns true. |
| 98 | supported_ |= 1u << VFP3; |
| 99 | found_by_runtime_probing_ |= 1u << VFP3; |
| 100 | } |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 101 | |
| 102 | if (OS::ArmCpuHasFeature(ARMv7)) { |
| 103 | supported_ |= 1u << ARMv7; |
| 104 | found_by_runtime_probing_ |= 1u << ARMv7; |
| 105 | } |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 106 | #endif |
| 107 | } |
| 108 | |
| 109 | |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 110 | // ----------------------------------------------------------------------------- |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 111 | // Implementation of RelocInfo |
| 112 | |
| 113 | const int RelocInfo::kApplyMask = 0; |
| 114 | |
| 115 | |
erik.corry@gmail.com | 9dfbea4 | 2010-05-21 12:58:28 +0000 | [diff] [blame] | 116 | bool RelocInfo::IsCodedSpecially() { |
| 117 | // The deserializer needs to know whether a pointer is specially coded. Being |
| 118 | // specially coded on ARM means that it is a movw/movt instruction. We don't |
| 119 | // generate those yet. |
| 120 | return false; |
| 121 | } |
| 122 | |
| 123 | |
| 124 | |
iposva@chromium.org | 245aa85 | 2009-02-10 00:49:54 +0000 | [diff] [blame] | 125 | void RelocInfo::PatchCode(byte* instructions, int instruction_count) { |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 126 | // Patch the code at the current address with the supplied instructions. |
ager@chromium.org | 4af710e | 2009-09-15 12:20:11 +0000 | [diff] [blame] | 127 | Instr* pc = reinterpret_cast<Instr*>(pc_); |
| 128 | Instr* instr = reinterpret_cast<Instr*>(instructions); |
| 129 | for (int i = 0; i < instruction_count; i++) { |
| 130 | *(pc + i) = *(instr + i); |
| 131 | } |
| 132 | |
| 133 | // Indicate that code has changed. |
| 134 | CPU::FlushICache(pc_, instruction_count * Assembler::kInstrSize); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 135 | } |
| 136 | |
| 137 | |
| 138 | // Patch the code at the current PC with a call to the target address. |
iposva@chromium.org | 245aa85 | 2009-02-10 00:49:54 +0000 | [diff] [blame] | 139 | // Additional guard instructions can be added if required. |
| 140 | void RelocInfo::PatchCodeWithCall(Address target, int guard_bytes) { |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 141 | // Patch the code at the current address with a call to the target. |
| 142 | UNIMPLEMENTED(); |
| 143 | } |
| 144 | |
| 145 | |
| 146 | // ----------------------------------------------------------------------------- |
| 147 | // Implementation of Operand and MemOperand |
| 148 | // See assembler-arm-inl.h for inlined constructors |
| 149 | |
| 150 | Operand::Operand(Handle<Object> handle) { |
| 151 | rm_ = no_reg; |
| 152 | // Verify all Objects referred by code are NOT in new space. |
| 153 | Object* obj = *handle; |
sgjesse@chromium.org | ea88ce9 | 2011-03-23 11:19:56 +0000 | [diff] [blame] | 154 | ASSERT(!HEAP->InNewSpace(obj)); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 155 | if (obj->IsHeapObject()) { |
| 156 | imm32_ = reinterpret_cast<intptr_t>(handle.location()); |
ager@chromium.org | 236ad96 | 2008-09-25 09:45:57 +0000 | [diff] [blame] | 157 | rmode_ = RelocInfo::EMBEDDED_OBJECT; |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 158 | } else { |
| 159 | // no relocation needed |
| 160 | imm32_ = reinterpret_cast<intptr_t>(obj); |
ager@chromium.org | 236ad96 | 2008-09-25 09:45:57 +0000 | [diff] [blame] | 161 | rmode_ = RelocInfo::NONE; |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 162 | } |
| 163 | } |
| 164 | |
| 165 | |
| 166 | Operand::Operand(Register rm, ShiftOp shift_op, int shift_imm) { |
| 167 | ASSERT(is_uint5(shift_imm)); |
| 168 | ASSERT(shift_op != ROR || shift_imm != 0); // use RRX if you mean it |
| 169 | rm_ = rm; |
| 170 | rs_ = no_reg; |
| 171 | shift_op_ = shift_op; |
| 172 | shift_imm_ = shift_imm & 31; |
| 173 | if (shift_op == RRX) { |
| 174 | // encoded as ROR with shift_imm == 0 |
| 175 | ASSERT(shift_imm == 0); |
| 176 | shift_op_ = ROR; |
| 177 | shift_imm_ = 0; |
| 178 | } |
| 179 | } |
| 180 | |
| 181 | |
| 182 | Operand::Operand(Register rm, ShiftOp shift_op, Register rs) { |
| 183 | ASSERT(shift_op != RRX); |
| 184 | rm_ = rm; |
| 185 | rs_ = no_reg; |
| 186 | shift_op_ = shift_op; |
| 187 | rs_ = rs; |
| 188 | } |
| 189 | |
| 190 | |
| 191 | MemOperand::MemOperand(Register rn, int32_t offset, AddrMode am) { |
| 192 | rn_ = rn; |
| 193 | rm_ = no_reg; |
| 194 | offset_ = offset; |
| 195 | am_ = am; |
| 196 | } |
| 197 | |
| 198 | MemOperand::MemOperand(Register rn, Register rm, AddrMode am) { |
| 199 | rn_ = rn; |
| 200 | rm_ = rm; |
| 201 | shift_op_ = LSL; |
| 202 | shift_imm_ = 0; |
| 203 | am_ = am; |
| 204 | } |
| 205 | |
| 206 | |
| 207 | MemOperand::MemOperand(Register rn, Register rm, |
| 208 | ShiftOp shift_op, int shift_imm, AddrMode am) { |
| 209 | ASSERT(is_uint5(shift_imm)); |
| 210 | rn_ = rn; |
| 211 | rm_ = rm; |
| 212 | shift_op_ = shift_op; |
| 213 | shift_imm_ = shift_imm & 31; |
| 214 | am_ = am; |
| 215 | } |
| 216 | |
| 217 | |
| 218 | // ----------------------------------------------------------------------------- |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 219 | // Specific instructions, constants, and masks. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 220 | |
mads.s.ager | 31e7138 | 2008-08-13 09:32:07 +0000 | [diff] [blame] | 221 | // add(sp, sp, 4) instruction (aka Pop()) |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 222 | const Instr kPopInstruction = |
| 223 | al | PostIndex | 4 | LeaveCC | I | sp.code() * B16 | sp.code() * B12; |
mads.s.ager | 31e7138 | 2008-08-13 09:32:07 +0000 | [diff] [blame] | 224 | // str(r, MemOperand(sp, 4, NegPreIndex), al) instruction (aka push(r)) |
| 225 | // register r is not encoded. |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 226 | const Instr kPushRegPattern = |
mads.s.ager | 31e7138 | 2008-08-13 09:32:07 +0000 | [diff] [blame] | 227 | al | B26 | 4 | NegPreIndex | sp.code() * B16; |
| 228 | // ldr(r, MemOperand(sp, 4, PostIndex), al) instruction (aka pop(r)) |
| 229 | // register r is not encoded. |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 230 | const Instr kPopRegPattern = |
mads.s.ager | 31e7138 | 2008-08-13 09:32:07 +0000 | [diff] [blame] | 231 | al | B26 | L | 4 | PostIndex | sp.code() * B16; |
ager@chromium.org | 4af710e | 2009-09-15 12:20:11 +0000 | [diff] [blame] | 232 | // mov lr, pc |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 233 | const Instr kMovLrPc = al | MOV | pc.code() | lr.code() * B12; |
whesse@chromium.org | cec079d | 2010-03-22 14:44:04 +0000 | [diff] [blame] | 234 | // ldr rd, [pc, #offset] |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 235 | const Instr kLdrPCMask = kCondMask | 15 * B24 | 7 * B20 | 15 * B16; |
whesse@chromium.org | cec079d | 2010-03-22 14:44:04 +0000 | [diff] [blame] | 236 | const Instr kLdrPCPattern = al | 5 * B24 | L | pc.code() * B16; |
| 237 | // blxcc rm |
| 238 | const Instr kBlxRegMask = |
| 239 | 15 * B24 | 15 * B20 | 15 * B16 | 15 * B12 | 15 * B8 | 15 * B4; |
| 240 | const Instr kBlxRegPattern = |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 241 | B24 | B21 | 15 * B16 | 15 * B12 | 15 * B8 | BLX; |
whesse@chromium.org | 2c186ca | 2010-06-16 11:32:39 +0000 | [diff] [blame] | 242 | const Instr kMovMvnMask = 0x6d * B21 | 0xf * B16; |
| 243 | const Instr kMovMvnPattern = 0xd * B21; |
| 244 | const Instr kMovMvnFlip = B22; |
ricow@chromium.org | 5ad5ace | 2010-06-23 09:06:43 +0000 | [diff] [blame] | 245 | const Instr kMovLeaveCCMask = 0xdff * B16; |
| 246 | const Instr kMovLeaveCCPattern = 0x1a0 * B16; |
| 247 | const Instr kMovwMask = 0xff * B20; |
| 248 | const Instr kMovwPattern = 0x30 * B20; |
| 249 | const Instr kMovwLeaveCCFlip = 0x5 * B21; |
whesse@chromium.org | 2c186ca | 2010-06-16 11:32:39 +0000 | [diff] [blame] | 250 | const Instr kCmpCmnMask = 0xdd * B20 | 0xf * B12; |
| 251 | const Instr kCmpCmnPattern = 0x15 * B20; |
| 252 | const Instr kCmpCmnFlip = B21; |
whesse@chromium.org | 2c186ca | 2010-06-16 11:32:39 +0000 | [diff] [blame] | 253 | const Instr kAddSubFlip = 0x6 * B21; |
| 254 | const Instr kAndBicFlip = 0xe * B21; |
| 255 | |
erik.corry@gmail.com | 9dfbea4 | 2010-05-21 12:58:28 +0000 | [diff] [blame] | 256 | // A mask for the Rd register for push, pop, ldr, str instructions. |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 257 | const Instr kLdrRegFpOffsetPattern = |
erik.corry@gmail.com | 9dfbea4 | 2010-05-21 12:58:28 +0000 | [diff] [blame] | 258 | al | B26 | L | Offset | fp.code() * B16; |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 259 | const Instr kStrRegFpOffsetPattern = |
erik.corry@gmail.com | 9dfbea4 | 2010-05-21 12:58:28 +0000 | [diff] [blame] | 260 | al | B26 | Offset | fp.code() * B16; |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 261 | const Instr kLdrRegFpNegOffsetPattern = |
erik.corry@gmail.com | 9dfbea4 | 2010-05-21 12:58:28 +0000 | [diff] [blame] | 262 | al | B26 | L | NegOffset | fp.code() * B16; |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 263 | const Instr kStrRegFpNegOffsetPattern = |
erik.corry@gmail.com | 9dfbea4 | 2010-05-21 12:58:28 +0000 | [diff] [blame] | 264 | al | B26 | NegOffset | fp.code() * B16; |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 265 | const Instr kLdrStrInstrTypeMask = 0xffff0000; |
| 266 | const Instr kLdrStrInstrArgumentMask = 0x0000ffff; |
| 267 | const Instr kLdrStrOffsetMask = 0x00000fff; |
| 268 | |
mads.s.ager | 31e7138 | 2008-08-13 09:32:07 +0000 | [diff] [blame] | 269 | |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 270 | // Spare buffer. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 271 | static const int kMinimalBufferSize = 4*KB; |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 272 | |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 273 | |
kmillikin@chromium.org | c36ce6e | 2011-04-04 08:25:31 +0000 | [diff] [blame] | 274 | Assembler::Assembler(Isolate* arg_isolate, void* buffer, int buffer_size) |
| 275 | : AssemblerBase(arg_isolate), |
sgjesse@chromium.org | ea88ce9 | 2011-03-23 11:19:56 +0000 | [diff] [blame] | 276 | positions_recorder_(this), |
ricow@chromium.org | badaffc | 2011-03-17 12:15:27 +0000 | [diff] [blame] | 277 | allow_peephole_optimization_(false), |
| 278 | emit_debug_code_(FLAG_debug_code) { |
kasperl@chromium.org | a555126 | 2010-12-07 12:49:48 +0000 | [diff] [blame] | 279 | allow_peephole_optimization_ = FLAG_peephole_optimization; |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 280 | if (buffer == NULL) { |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 281 | // Do our own buffer management. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 282 | if (buffer_size <= kMinimalBufferSize) { |
| 283 | buffer_size = kMinimalBufferSize; |
| 284 | |
sgjesse@chromium.org | ea88ce9 | 2011-03-23 11:19:56 +0000 | [diff] [blame] | 285 | if (isolate()->assembler_spare_buffer() != NULL) { |
| 286 | buffer = isolate()->assembler_spare_buffer(); |
| 287 | isolate()->set_assembler_spare_buffer(NULL); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 288 | } |
| 289 | } |
| 290 | if (buffer == NULL) { |
| 291 | buffer_ = NewArray<byte>(buffer_size); |
| 292 | } else { |
| 293 | buffer_ = static_cast<byte*>(buffer); |
| 294 | } |
| 295 | buffer_size_ = buffer_size; |
| 296 | own_buffer_ = true; |
| 297 | |
| 298 | } else { |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 299 | // Use externally provided buffer instead. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 300 | ASSERT(buffer_size > 0); |
| 301 | buffer_ = static_cast<byte*>(buffer); |
| 302 | buffer_size_ = buffer_size; |
| 303 | own_buffer_ = false; |
| 304 | } |
| 305 | |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 306 | // Setup buffer pointers. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 307 | ASSERT(buffer_ != NULL); |
| 308 | pc_ = buffer_; |
| 309 | reloc_info_writer.Reposition(buffer_ + buffer_size, pc_); |
| 310 | num_prinfo_ = 0; |
| 311 | next_buffer_check_ = 0; |
fschneider@chromium.org | 013f3e1 | 2010-04-26 13:27:52 +0000 | [diff] [blame] | 312 | const_pool_blocked_nesting_ = 0; |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 313 | no_const_pool_before_ = 0; |
| 314 | last_const_pool_end_ = 0; |
| 315 | last_bound_pos_ = 0; |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 316 | } |
| 317 | |
| 318 | |
| 319 | Assembler::~Assembler() { |
fschneider@chromium.org | 013f3e1 | 2010-04-26 13:27:52 +0000 | [diff] [blame] | 320 | ASSERT(const_pool_blocked_nesting_ == 0); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 321 | if (own_buffer_) { |
sgjesse@chromium.org | ea88ce9 | 2011-03-23 11:19:56 +0000 | [diff] [blame] | 322 | if (isolate()->assembler_spare_buffer() == NULL && |
| 323 | buffer_size_ == kMinimalBufferSize) { |
| 324 | isolate()->set_assembler_spare_buffer(buffer_); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 325 | } else { |
| 326 | DeleteArray(buffer_); |
| 327 | } |
| 328 | } |
| 329 | } |
| 330 | |
| 331 | |
| 332 | void Assembler::GetCode(CodeDesc* desc) { |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 333 | // Emit constant pool if necessary. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 334 | CheckConstPool(true, false); |
| 335 | ASSERT(num_prinfo_ == 0); |
| 336 | |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 337 | // Setup code descriptor. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 338 | desc->buffer = buffer_; |
| 339 | desc->buffer_size = buffer_size_; |
| 340 | desc->instr_size = pc_offset(); |
| 341 | desc->reloc_size = (buffer_ + buffer_size_) - reloc_info_writer.pos(); |
| 342 | } |
| 343 | |
| 344 | |
| 345 | void Assembler::Align(int m) { |
| 346 | ASSERT(m >= 4 && IsPowerOf2(m)); |
| 347 | while ((pc_offset() & (m - 1)) != 0) { |
| 348 | nop(); |
| 349 | } |
| 350 | } |
| 351 | |
| 352 | |
ricow@chromium.org | 5ad5ace | 2010-06-23 09:06:43 +0000 | [diff] [blame] | 353 | void Assembler::CodeTargetAlign() { |
| 354 | // Preferred alignment of jump targets on some ARM chips. |
| 355 | Align(8); |
| 356 | } |
| 357 | |
| 358 | |
sgjesse@chromium.org | 496c03a | 2011-02-14 12:05:43 +0000 | [diff] [blame] | 359 | Condition Assembler::GetCondition(Instr instr) { |
| 360 | return Instruction::ConditionField(instr); |
| 361 | } |
| 362 | |
| 363 | |
fschneider@chromium.org | 013f3e1 | 2010-04-26 13:27:52 +0000 | [diff] [blame] | 364 | bool Assembler::IsBranch(Instr instr) { |
| 365 | return (instr & (B27 | B25)) == (B27 | B25); |
| 366 | } |
| 367 | |
| 368 | |
| 369 | int Assembler::GetBranchOffset(Instr instr) { |
| 370 | ASSERT(IsBranch(instr)); |
| 371 | // Take the jump offset in the lower 24 bits, sign extend it and multiply it |
| 372 | // with 4 to get the offset in bytes. |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 373 | return ((instr & kImm24Mask) << 8) >> 6; |
fschneider@chromium.org | 013f3e1 | 2010-04-26 13:27:52 +0000 | [diff] [blame] | 374 | } |
| 375 | |
| 376 | |
| 377 | bool Assembler::IsLdrRegisterImmediate(Instr instr) { |
| 378 | return (instr & (B27 | B26 | B25 | B22 | B20)) == (B26 | B20); |
| 379 | } |
| 380 | |
| 381 | |
| 382 | int Assembler::GetLdrRegisterImmediateOffset(Instr instr) { |
| 383 | ASSERT(IsLdrRegisterImmediate(instr)); |
| 384 | bool positive = (instr & B23) == B23; |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 385 | int offset = instr & kOff12Mask; // Zero extended offset. |
fschneider@chromium.org | 013f3e1 | 2010-04-26 13:27:52 +0000 | [diff] [blame] | 386 | return positive ? offset : -offset; |
| 387 | } |
| 388 | |
| 389 | |
| 390 | Instr Assembler::SetLdrRegisterImmediateOffset(Instr instr, int offset) { |
| 391 | ASSERT(IsLdrRegisterImmediate(instr)); |
| 392 | bool positive = offset >= 0; |
| 393 | if (!positive) offset = -offset; |
| 394 | ASSERT(is_uint12(offset)); |
| 395 | // Set bit indicating whether the offset should be added. |
| 396 | instr = (instr & ~B23) | (positive ? B23 : 0); |
| 397 | // Set the actual offset. |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 398 | return (instr & ~kOff12Mask) | offset; |
fschneider@chromium.org | 013f3e1 | 2010-04-26 13:27:52 +0000 | [diff] [blame] | 399 | } |
| 400 | |
| 401 | |
whesse@chromium.org | ba5a61b | 2010-07-26 11:44:40 +0000 | [diff] [blame] | 402 | bool Assembler::IsStrRegisterImmediate(Instr instr) { |
| 403 | return (instr & (B27 | B26 | B25 | B22 | B20)) == B26; |
| 404 | } |
| 405 | |
| 406 | |
| 407 | Instr Assembler::SetStrRegisterImmediateOffset(Instr instr, int offset) { |
| 408 | ASSERT(IsStrRegisterImmediate(instr)); |
| 409 | bool positive = offset >= 0; |
| 410 | if (!positive) offset = -offset; |
| 411 | ASSERT(is_uint12(offset)); |
| 412 | // Set bit indicating whether the offset should be added. |
| 413 | instr = (instr & ~B23) | (positive ? B23 : 0); |
| 414 | // Set the actual offset. |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 415 | return (instr & ~kOff12Mask) | offset; |
whesse@chromium.org | ba5a61b | 2010-07-26 11:44:40 +0000 | [diff] [blame] | 416 | } |
| 417 | |
| 418 | |
| 419 | bool Assembler::IsAddRegisterImmediate(Instr instr) { |
| 420 | return (instr & (B27 | B26 | B25 | B24 | B23 | B22 | B21)) == (B25 | B23); |
| 421 | } |
| 422 | |
| 423 | |
| 424 | Instr Assembler::SetAddRegisterImmediateOffset(Instr instr, int offset) { |
| 425 | ASSERT(IsAddRegisterImmediate(instr)); |
| 426 | ASSERT(offset >= 0); |
| 427 | ASSERT(is_uint12(offset)); |
| 428 | // Set the offset. |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 429 | return (instr & ~kOff12Mask) | offset; |
whesse@chromium.org | ba5a61b | 2010-07-26 11:44:40 +0000 | [diff] [blame] | 430 | } |
| 431 | |
| 432 | |
erik.corry@gmail.com | 9dfbea4 | 2010-05-21 12:58:28 +0000 | [diff] [blame] | 433 | Register Assembler::GetRd(Instr instr) { |
| 434 | Register reg; |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 435 | reg.code_ = Instruction::RdValue(instr); |
erik.corry@gmail.com | 9dfbea4 | 2010-05-21 12:58:28 +0000 | [diff] [blame] | 436 | return reg; |
| 437 | } |
| 438 | |
| 439 | |
sgjesse@chromium.org | 496c03a | 2011-02-14 12:05:43 +0000 | [diff] [blame] | 440 | Register Assembler::GetRn(Instr instr) { |
| 441 | Register reg; |
| 442 | reg.code_ = Instruction::RnValue(instr); |
| 443 | return reg; |
| 444 | } |
| 445 | |
| 446 | |
| 447 | Register Assembler::GetRm(Instr instr) { |
| 448 | Register reg; |
| 449 | reg.code_ = Instruction::RmValue(instr); |
| 450 | return reg; |
| 451 | } |
| 452 | |
| 453 | |
erik.corry@gmail.com | 9dfbea4 | 2010-05-21 12:58:28 +0000 | [diff] [blame] | 454 | bool Assembler::IsPush(Instr instr) { |
| 455 | return ((instr & ~kRdMask) == kPushRegPattern); |
| 456 | } |
| 457 | |
| 458 | |
| 459 | bool Assembler::IsPop(Instr instr) { |
| 460 | return ((instr & ~kRdMask) == kPopRegPattern); |
| 461 | } |
| 462 | |
| 463 | |
| 464 | bool Assembler::IsStrRegFpOffset(Instr instr) { |
| 465 | return ((instr & kLdrStrInstrTypeMask) == kStrRegFpOffsetPattern); |
| 466 | } |
| 467 | |
| 468 | |
| 469 | bool Assembler::IsLdrRegFpOffset(Instr instr) { |
| 470 | return ((instr & kLdrStrInstrTypeMask) == kLdrRegFpOffsetPattern); |
| 471 | } |
| 472 | |
| 473 | |
| 474 | bool Assembler::IsStrRegFpNegOffset(Instr instr) { |
| 475 | return ((instr & kLdrStrInstrTypeMask) == kStrRegFpNegOffsetPattern); |
| 476 | } |
| 477 | |
| 478 | |
| 479 | bool Assembler::IsLdrRegFpNegOffset(Instr instr) { |
| 480 | return ((instr & kLdrStrInstrTypeMask) == kLdrRegFpNegOffsetPattern); |
| 481 | } |
| 482 | |
| 483 | |
ager@chromium.org | beb2571 | 2010-11-29 08:02:25 +0000 | [diff] [blame] | 484 | bool Assembler::IsLdrPcImmediateOffset(Instr instr) { |
| 485 | // Check the instruction is indeed a |
| 486 | // ldr<cond> <Rd>, [pc +/- offset_12]. |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 487 | return (instr & (kLdrPCMask & ~kCondMask)) == 0x051f0000; |
ager@chromium.org | beb2571 | 2010-11-29 08:02:25 +0000 | [diff] [blame] | 488 | } |
| 489 | |
| 490 | |
sgjesse@chromium.org | 496c03a | 2011-02-14 12:05:43 +0000 | [diff] [blame] | 491 | bool Assembler::IsTstImmediate(Instr instr) { |
| 492 | return (instr & (B27 | B26 | I | kOpCodeMask | S | kRdMask)) == |
| 493 | (I | TST | S); |
| 494 | } |
| 495 | |
| 496 | |
| 497 | bool Assembler::IsCmpRegister(Instr instr) { |
| 498 | return (instr & (B27 | B26 | I | kOpCodeMask | S | kRdMask | B4)) == |
| 499 | (CMP | S); |
| 500 | } |
| 501 | |
| 502 | |
| 503 | bool Assembler::IsCmpImmediate(Instr instr) { |
| 504 | return (instr & (B27 | B26 | I | kOpCodeMask | S | kRdMask)) == |
| 505 | (I | CMP | S); |
| 506 | } |
| 507 | |
| 508 | |
| 509 | Register Assembler::GetCmpImmediateRegister(Instr instr) { |
| 510 | ASSERT(IsCmpImmediate(instr)); |
| 511 | return GetRn(instr); |
| 512 | } |
| 513 | |
| 514 | |
| 515 | int Assembler::GetCmpImmediateRawImmediate(Instr instr) { |
| 516 | ASSERT(IsCmpImmediate(instr)); |
| 517 | return instr & kOff12Mask; |
| 518 | } |
| 519 | |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 520 | // Labels refer to positions in the (to be) generated code. |
| 521 | // There are bound, linked, and unused labels. |
| 522 | // |
| 523 | // Bound labels refer to known positions in the already |
| 524 | // generated code. pos() is the position the label refers to. |
| 525 | // |
| 526 | // Linked labels refer to unknown positions in the code |
| 527 | // to be generated; pos() is the position of the last |
| 528 | // instruction using the label. |
| 529 | |
| 530 | |
| 531 | // The link chain is terminated by a negative code position (must be aligned) |
| 532 | const int kEndOfChain = -4; |
| 533 | |
| 534 | |
| 535 | int Assembler::target_at(int pos) { |
| 536 | Instr instr = instr_at(pos); |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 537 | if ((instr & ~kImm24Mask) == 0) { |
ager@chromium.org | 18ad94b | 2009-09-02 08:22:29 +0000 | [diff] [blame] | 538 | // Emitted label constant, not part of a branch. |
| 539 | return instr - (Code::kHeaderSize - kHeapObjectTag); |
| 540 | } |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 541 | ASSERT((instr & 7*B25) == 5*B25); // b, bl, or blx imm24 |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 542 | int imm26 = ((instr & kImm24Mask) << 8) >> 6; |
| 543 | if ((Instruction::ConditionField(instr) == kSpecialCondition) && |
| 544 | ((instr & B24) != 0)) { |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 545 | // blx uses bit 24 to encode bit 2 of imm26 |
| 546 | imm26 += 2; |
fschneider@chromium.org | 013f3e1 | 2010-04-26 13:27:52 +0000 | [diff] [blame] | 547 | } |
ager@chromium.org | 18ad94b | 2009-09-02 08:22:29 +0000 | [diff] [blame] | 548 | return pos + kPcLoadDelta + imm26; |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 549 | } |
| 550 | |
| 551 | |
| 552 | void Assembler::target_at_put(int pos, int target_pos) { |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 553 | Instr instr = instr_at(pos); |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 554 | if ((instr & ~kImm24Mask) == 0) { |
ager@chromium.org | 18ad94b | 2009-09-02 08:22:29 +0000 | [diff] [blame] | 555 | ASSERT(target_pos == kEndOfChain || target_pos >= 0); |
| 556 | // Emitted label constant, not part of a branch. |
| 557 | // Make label relative to Code* of generated Code object. |
| 558 | instr_at_put(pos, target_pos + (Code::kHeaderSize - kHeapObjectTag)); |
| 559 | return; |
| 560 | } |
| 561 | int imm26 = target_pos - (pos + kPcLoadDelta); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 562 | ASSERT((instr & 7*B25) == 5*B25); // b, bl, or blx imm24 |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 563 | if (Instruction::ConditionField(instr) == kSpecialCondition) { |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 564 | // blx uses bit 24 to encode bit 2 of imm26 |
| 565 | ASSERT((imm26 & 1) == 0); |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 566 | instr = (instr & ~(B24 | kImm24Mask)) | ((imm26 & 2) >> 1)*B24; |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 567 | } else { |
| 568 | ASSERT((imm26 & 3) == 0); |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 569 | instr &= ~kImm24Mask; |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 570 | } |
| 571 | int imm24 = imm26 >> 2; |
| 572 | ASSERT(is_int24(imm24)); |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 573 | instr_at_put(pos, instr | (imm24 & kImm24Mask)); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 574 | } |
| 575 | |
| 576 | |
| 577 | void Assembler::print(Label* L) { |
| 578 | if (L->is_unused()) { |
| 579 | PrintF("unused label\n"); |
| 580 | } else if (L->is_bound()) { |
| 581 | PrintF("bound label to %d\n", L->pos()); |
| 582 | } else if (L->is_linked()) { |
| 583 | Label l = *L; |
| 584 | PrintF("unbound label"); |
| 585 | while (l.is_linked()) { |
| 586 | PrintF("@ %d ", l.pos()); |
| 587 | Instr instr = instr_at(l.pos()); |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 588 | if ((instr & ~kImm24Mask) == 0) { |
ager@chromium.org | 18ad94b | 2009-09-02 08:22:29 +0000 | [diff] [blame] | 589 | PrintF("value\n"); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 590 | } else { |
ager@chromium.org | 18ad94b | 2009-09-02 08:22:29 +0000 | [diff] [blame] | 591 | ASSERT((instr & 7*B25) == 5*B25); // b, bl, or blx |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 592 | Condition cond = Instruction::ConditionField(instr); |
ager@chromium.org | 18ad94b | 2009-09-02 08:22:29 +0000 | [diff] [blame] | 593 | const char* b; |
| 594 | const char* c; |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 595 | if (cond == kSpecialCondition) { |
ager@chromium.org | 18ad94b | 2009-09-02 08:22:29 +0000 | [diff] [blame] | 596 | b = "blx"; |
| 597 | c = ""; |
| 598 | } else { |
| 599 | if ((instr & B24) != 0) |
| 600 | b = "bl"; |
| 601 | else |
| 602 | b = "b"; |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 603 | |
ager@chromium.org | 18ad94b | 2009-09-02 08:22:29 +0000 | [diff] [blame] | 604 | switch (cond) { |
| 605 | case eq: c = "eq"; break; |
| 606 | case ne: c = "ne"; break; |
| 607 | case hs: c = "hs"; break; |
| 608 | case lo: c = "lo"; break; |
| 609 | case mi: c = "mi"; break; |
| 610 | case pl: c = "pl"; break; |
| 611 | case vs: c = "vs"; break; |
| 612 | case vc: c = "vc"; break; |
| 613 | case hi: c = "hi"; break; |
| 614 | case ls: c = "ls"; break; |
| 615 | case ge: c = "ge"; break; |
| 616 | case lt: c = "lt"; break; |
| 617 | case gt: c = "gt"; break; |
| 618 | case le: c = "le"; break; |
| 619 | case al: c = ""; break; |
| 620 | default: |
| 621 | c = ""; |
| 622 | UNREACHABLE(); |
| 623 | } |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 624 | } |
ager@chromium.org | 18ad94b | 2009-09-02 08:22:29 +0000 | [diff] [blame] | 625 | PrintF("%s%s\n", b, c); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 626 | } |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 627 | next(&l); |
| 628 | } |
| 629 | } else { |
| 630 | PrintF("label in inconsistent state (pos = %d)\n", L->pos_); |
| 631 | } |
| 632 | } |
| 633 | |
| 634 | |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 635 | void Assembler::bind_to(Label* L, int pos) { |
| 636 | ASSERT(0 <= pos && pos <= pc_offset()); // must have a valid binding position |
| 637 | while (L->is_linked()) { |
| 638 | int fixup_pos = L->pos(); |
| 639 | next(L); // call next before overwriting link with target at fixup_pos |
| 640 | target_at_put(fixup_pos, pos); |
| 641 | } |
| 642 | L->bind_to(pos); |
| 643 | |
kasperl@chromium.org | 41044eb | 2008-10-06 08:24:46 +0000 | [diff] [blame] | 644 | // Keep track of the last bound label so we don't eliminate any instructions |
| 645 | // before a bound label. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 646 | if (pos > last_bound_pos_) |
| 647 | last_bound_pos_ = pos; |
| 648 | } |
| 649 | |
| 650 | |
| 651 | void Assembler::link_to(Label* L, Label* appendix) { |
| 652 | if (appendix->is_linked()) { |
| 653 | if (L->is_linked()) { |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 654 | // Append appendix to L's list. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 655 | int fixup_pos; |
| 656 | int link = L->pos(); |
| 657 | do { |
| 658 | fixup_pos = link; |
| 659 | link = target_at(fixup_pos); |
| 660 | } while (link > 0); |
| 661 | ASSERT(link == kEndOfChain); |
| 662 | target_at_put(fixup_pos, appendix->pos()); |
| 663 | } else { |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 664 | // L is empty, simply use appendix. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 665 | *L = *appendix; |
| 666 | } |
| 667 | } |
| 668 | appendix->Unuse(); // appendix should not be used anymore |
| 669 | } |
| 670 | |
| 671 | |
| 672 | void Assembler::bind(Label* L) { |
| 673 | ASSERT(!L->is_bound()); // label can only be bound once |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 674 | bind_to(L, pc_offset()); |
| 675 | } |
| 676 | |
| 677 | |
| 678 | void Assembler::next(Label* L) { |
| 679 | ASSERT(L->is_linked()); |
| 680 | int link = target_at(L->pos()); |
| 681 | if (link > 0) { |
| 682 | L->link_to(link); |
| 683 | } else { |
| 684 | ASSERT(link == kEndOfChain); |
| 685 | L->Unuse(); |
| 686 | } |
| 687 | } |
| 688 | |
| 689 | |
ricow@chromium.org | 5ad5ace | 2010-06-23 09:06:43 +0000 | [diff] [blame] | 690 | static Instr EncodeMovwImmediate(uint32_t immediate) { |
| 691 | ASSERT(immediate < 0x10000); |
| 692 | return ((immediate & 0xf000) << 4) | (immediate & 0xfff); |
| 693 | } |
| 694 | |
| 695 | |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 696 | // Low-level code emission routines depending on the addressing mode. |
whesse@chromium.org | 2c186ca | 2010-06-16 11:32:39 +0000 | [diff] [blame] | 697 | // If this returns true then you have to use the rotate_imm and immed_8 |
| 698 | // that it returns, because it may have already changed the instruction |
| 699 | // to match them! |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 700 | static bool fits_shifter(uint32_t imm32, |
| 701 | uint32_t* rotate_imm, |
| 702 | uint32_t* immed_8, |
| 703 | Instr* instr) { |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 704 | // imm32 must be unsigned. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 705 | for (int rot = 0; rot < 16; rot++) { |
| 706 | uint32_t imm8 = (imm32 << 2*rot) | (imm32 >> (32 - 2*rot)); |
| 707 | if ((imm8 <= 0xff)) { |
| 708 | *rotate_imm = rot; |
| 709 | *immed_8 = imm8; |
| 710 | return true; |
| 711 | } |
| 712 | } |
whesse@chromium.org | 2c186ca | 2010-06-16 11:32:39 +0000 | [diff] [blame] | 713 | // If the opcode is one with a complementary version and the complementary |
| 714 | // immediate fits, change the opcode. |
| 715 | if (instr != NULL) { |
| 716 | if ((*instr & kMovMvnMask) == kMovMvnPattern) { |
| 717 | if (fits_shifter(~imm32, rotate_imm, immed_8, NULL)) { |
| 718 | *instr ^= kMovMvnFlip; |
| 719 | return true; |
ricow@chromium.org | 5ad5ace | 2010-06-23 09:06:43 +0000 | [diff] [blame] | 720 | } else if ((*instr & kMovLeaveCCMask) == kMovLeaveCCPattern) { |
kmillikin@chromium.org | c36ce6e | 2011-04-04 08:25:31 +0000 | [diff] [blame] | 721 | if (CpuFeatures::IsSupported(ARMv7)) { |
ricow@chromium.org | 5ad5ace | 2010-06-23 09:06:43 +0000 | [diff] [blame] | 722 | if (imm32 < 0x10000) { |
| 723 | *instr ^= kMovwLeaveCCFlip; |
| 724 | *instr |= EncodeMovwImmediate(imm32); |
| 725 | *rotate_imm = *immed_8 = 0; // Not used for movw. |
| 726 | return true; |
| 727 | } |
| 728 | } |
whesse@chromium.org | 2c186ca | 2010-06-16 11:32:39 +0000 | [diff] [blame] | 729 | } |
| 730 | } else if ((*instr & kCmpCmnMask) == kCmpCmnPattern) { |
| 731 | if (fits_shifter(-imm32, rotate_imm, immed_8, NULL)) { |
| 732 | *instr ^= kCmpCmnFlip; |
| 733 | return true; |
| 734 | } |
| 735 | } else { |
| 736 | Instr alu_insn = (*instr & kALUMask); |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 737 | if (alu_insn == ADD || |
| 738 | alu_insn == SUB) { |
whesse@chromium.org | 2c186ca | 2010-06-16 11:32:39 +0000 | [diff] [blame] | 739 | if (fits_shifter(-imm32, rotate_imm, immed_8, NULL)) { |
| 740 | *instr ^= kAddSubFlip; |
| 741 | return true; |
| 742 | } |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 743 | } else if (alu_insn == AND || |
| 744 | alu_insn == BIC) { |
whesse@chromium.org | 2c186ca | 2010-06-16 11:32:39 +0000 | [diff] [blame] | 745 | if (fits_shifter(~imm32, rotate_imm, immed_8, NULL)) { |
| 746 | *instr ^= kAndBicFlip; |
| 747 | return true; |
| 748 | } |
| 749 | } |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 750 | } |
| 751 | } |
| 752 | return false; |
| 753 | } |
| 754 | |
| 755 | |
kasperl@chromium.org | 2abc450 | 2009-07-02 07:00:29 +0000 | [diff] [blame] | 756 | // We have to use the temporary register for things that can be relocated even |
| 757 | // if they can be encoded in the ARM's 12 bits of immediate-offset instruction |
| 758 | // space. There is no guarantee that the relocated location can be similarly |
| 759 | // encoded. |
whesse@chromium.org | f0ac72d | 2010-11-08 12:47:26 +0000 | [diff] [blame] | 760 | bool Operand::must_use_constant_pool() const { |
| 761 | if (rmode_ == RelocInfo::EXTERNAL_REFERENCE) { |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 762 | #ifdef DEBUG |
| 763 | if (!Serializer::enabled()) { |
| 764 | Serializer::TooLateToEnableNow(); |
| 765 | } |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 766 | #endif // def DEBUG |
kasperl@chromium.org | 2abc450 | 2009-07-02 07:00:29 +0000 | [diff] [blame] | 767 | return Serializer::enabled(); |
whesse@chromium.org | f0ac72d | 2010-11-08 12:47:26 +0000 | [diff] [blame] | 768 | } else if (rmode_ == RelocInfo::NONE) { |
kasperl@chromium.org | 2abc450 | 2009-07-02 07:00:29 +0000 | [diff] [blame] | 769 | return false; |
| 770 | } |
| 771 | return true; |
| 772 | } |
| 773 | |
| 774 | |
whesse@chromium.org | b08986c | 2011-03-14 16:13:42 +0000 | [diff] [blame] | 775 | bool Operand::is_single_instruction(Instr instr) const { |
whesse@chromium.org | 2c186ca | 2010-06-16 11:32:39 +0000 | [diff] [blame] | 776 | if (rm_.is_valid()) return true; |
whesse@chromium.org | 2c186ca | 2010-06-16 11:32:39 +0000 | [diff] [blame] | 777 | uint32_t dummy1, dummy2; |
whesse@chromium.org | b08986c | 2011-03-14 16:13:42 +0000 | [diff] [blame] | 778 | if (must_use_constant_pool() || |
| 779 | !fits_shifter(imm32_, &dummy1, &dummy2, &instr)) { |
| 780 | // The immediate operand cannot be encoded as a shifter operand, or use of |
| 781 | // constant pool is required. For a mov instruction not setting the |
| 782 | // condition code additional instruction conventions can be used. |
| 783 | if ((instr & ~kCondMask) == 13*B21) { // mov, S not set |
sgjesse@chromium.org | ea88ce9 | 2011-03-23 11:19:56 +0000 | [diff] [blame] | 784 | if (must_use_constant_pool() || |
kmillikin@chromium.org | c36ce6e | 2011-04-04 08:25:31 +0000 | [diff] [blame] | 785 | !CpuFeatures::IsSupported(ARMv7)) { |
whesse@chromium.org | b08986c | 2011-03-14 16:13:42 +0000 | [diff] [blame] | 786 | // mov instruction will be an ldr from constant pool (one instruction). |
| 787 | return true; |
| 788 | } else { |
| 789 | // mov instruction will be a mov or movw followed by movt (two |
| 790 | // instructions). |
| 791 | return false; |
| 792 | } |
| 793 | } else { |
| 794 | // If this is not a mov or mvn instruction there will always an additional |
| 795 | // instructions - either mov or ldr. The mov might actually be two |
| 796 | // instructions mov or movw followed by movt so including the actual |
| 797 | // instruction two or three instructions will be generated. |
| 798 | return false; |
| 799 | } |
| 800 | } else { |
| 801 | // No use of constant pool and the immediate operand can be encoded as a |
| 802 | // shifter operand. |
| 803 | return true; |
| 804 | } |
whesse@chromium.org | 2c186ca | 2010-06-16 11:32:39 +0000 | [diff] [blame] | 805 | } |
| 806 | |
| 807 | |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 808 | void Assembler::addrmod1(Instr instr, |
| 809 | Register rn, |
| 810 | Register rd, |
| 811 | const Operand& x) { |
| 812 | CheckBuffer(); |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 813 | ASSERT((instr & ~(kCondMask | kOpCodeMask | S)) == 0); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 814 | if (!x.rm_.is_valid()) { |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 815 | // Immediate. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 816 | uint32_t rotate_imm; |
| 817 | uint32_t immed_8; |
whesse@chromium.org | f0ac72d | 2010-11-08 12:47:26 +0000 | [diff] [blame] | 818 | if (x.must_use_constant_pool() || |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 819 | !fits_shifter(x.imm32_, &rotate_imm, &immed_8, &instr)) { |
| 820 | // The immediate operand cannot be encoded as a shifter operand, so load |
| 821 | // it first to register ip and change the original instruction to use ip. |
| 822 | // However, if the original instruction is a 'mov rd, x' (not setting the |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 823 | // condition code), then replace it with a 'ldr rd, [pc]'. |
ager@chromium.org | a74f0da | 2008-12-03 16:05:52 +0000 | [diff] [blame] | 824 | CHECK(!rn.is(ip)); // rn should never be ip, or will be trashed |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 825 | Condition cond = Instruction::ConditionField(instr); |
| 826 | if ((instr & ~kCondMask) == 13*B21) { // mov, S not set |
sgjesse@chromium.org | ea88ce9 | 2011-03-23 11:19:56 +0000 | [diff] [blame] | 827 | if (x.must_use_constant_pool() || |
kmillikin@chromium.org | c36ce6e | 2011-04-04 08:25:31 +0000 | [diff] [blame] | 828 | !CpuFeatures::IsSupported(ARMv7)) { |
ricow@chromium.org | 5ad5ace | 2010-06-23 09:06:43 +0000 | [diff] [blame] | 829 | RecordRelocInfo(x.rmode_, x.imm32_); |
| 830 | ldr(rd, MemOperand(pc, 0), cond); |
| 831 | } else { |
| 832 | // Will probably use movw, will certainly not use constant pool. |
| 833 | mov(rd, Operand(x.imm32_ & 0xffff), LeaveCC, cond); |
| 834 | movt(rd, static_cast<uint32_t>(x.imm32_) >> 16, cond); |
| 835 | } |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 836 | } else { |
ricow@chromium.org | 5ad5ace | 2010-06-23 09:06:43 +0000 | [diff] [blame] | 837 | // If this is not a mov or mvn instruction we may still be able to avoid |
| 838 | // a constant pool entry by using mvn or movw. |
whesse@chromium.org | f0ac72d | 2010-11-08 12:47:26 +0000 | [diff] [blame] | 839 | if (!x.must_use_constant_pool() && |
ricow@chromium.org | 5ad5ace | 2010-06-23 09:06:43 +0000 | [diff] [blame] | 840 | (instr & kMovMvnMask) != kMovMvnPattern) { |
| 841 | mov(ip, x, LeaveCC, cond); |
| 842 | } else { |
| 843 | RecordRelocInfo(x.rmode_, x.imm32_); |
| 844 | ldr(ip, MemOperand(pc, 0), cond); |
| 845 | } |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 846 | addrmod1(instr, rn, rd, Operand(ip)); |
| 847 | } |
| 848 | return; |
| 849 | } |
| 850 | instr |= I | rotate_imm*B8 | immed_8; |
| 851 | } else if (!x.rs_.is_valid()) { |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 852 | // Immediate shift. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 853 | instr |= x.shift_imm_*B7 | x.shift_op_ | x.rm_.code(); |
| 854 | } else { |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 855 | // Register shift. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 856 | ASSERT(!rn.is(pc) && !rd.is(pc) && !x.rm_.is(pc) && !x.rs_.is(pc)); |
| 857 | instr |= x.rs_.code()*B8 | x.shift_op_ | B4 | x.rm_.code(); |
| 858 | } |
| 859 | emit(instr | rn.code()*B16 | rd.code()*B12); |
whesse@chromium.org | ba5a61b | 2010-07-26 11:44:40 +0000 | [diff] [blame] | 860 | if (rn.is(pc) || x.rm_.is(pc)) { |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 861 | // Block constant pool emission for one instruction after reading pc. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 862 | BlockConstPoolBefore(pc_offset() + kInstrSize); |
whesse@chromium.org | ba5a61b | 2010-07-26 11:44:40 +0000 | [diff] [blame] | 863 | } |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 864 | } |
| 865 | |
| 866 | |
| 867 | void Assembler::addrmod2(Instr instr, Register rd, const MemOperand& x) { |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 868 | ASSERT((instr & ~(kCondMask | B | L)) == B26); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 869 | int am = x.am_; |
| 870 | if (!x.rm_.is_valid()) { |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 871 | // Immediate offset. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 872 | int offset_12 = x.offset_; |
| 873 | if (offset_12 < 0) { |
| 874 | offset_12 = -offset_12; |
| 875 | am ^= U; |
| 876 | } |
| 877 | if (!is_uint12(offset_12)) { |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 878 | // Immediate offset cannot be encoded, load it first to register ip |
| 879 | // rn (and rd in a load) should never be ip, or will be trashed. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 880 | ASSERT(!x.rn_.is(ip) && ((instr & L) == L || !rd.is(ip))); |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 881 | mov(ip, Operand(x.offset_), LeaveCC, Instruction::ConditionField(instr)); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 882 | addrmod2(instr, rd, MemOperand(x.rn_, ip, x.am_)); |
| 883 | return; |
| 884 | } |
| 885 | ASSERT(offset_12 >= 0); // no masking needed |
| 886 | instr |= offset_12; |
| 887 | } else { |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 888 | // Register offset (shift_imm_ and shift_op_ are 0) or scaled |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 889 | // register offset the constructors make sure than both shift_imm_ |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 890 | // and shift_op_ are initialized. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 891 | ASSERT(!x.rm_.is(pc)); |
| 892 | instr |= B25 | x.shift_imm_*B7 | x.shift_op_ | x.rm_.code(); |
| 893 | } |
| 894 | ASSERT((am & (P|W)) == P || !x.rn_.is(pc)); // no pc base with writeback |
| 895 | emit(instr | am | x.rn_.code()*B16 | rd.code()*B12); |
| 896 | } |
| 897 | |
| 898 | |
| 899 | void Assembler::addrmod3(Instr instr, Register rd, const MemOperand& x) { |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 900 | ASSERT((instr & ~(kCondMask | L | S6 | H)) == (B4 | B7)); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 901 | ASSERT(x.rn_.is_valid()); |
| 902 | int am = x.am_; |
| 903 | if (!x.rm_.is_valid()) { |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 904 | // Immediate offset. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 905 | int offset_8 = x.offset_; |
| 906 | if (offset_8 < 0) { |
| 907 | offset_8 = -offset_8; |
| 908 | am ^= U; |
| 909 | } |
| 910 | if (!is_uint8(offset_8)) { |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 911 | // Immediate offset cannot be encoded, load it first to register ip |
| 912 | // rn (and rd in a load) should never be ip, or will be trashed. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 913 | ASSERT(!x.rn_.is(ip) && ((instr & L) == L || !rd.is(ip))); |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 914 | mov(ip, Operand(x.offset_), LeaveCC, Instruction::ConditionField(instr)); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 915 | addrmod3(instr, rd, MemOperand(x.rn_, ip, x.am_)); |
| 916 | return; |
| 917 | } |
| 918 | ASSERT(offset_8 >= 0); // no masking needed |
| 919 | instr |= B | (offset_8 >> 4)*B8 | (offset_8 & 0xf); |
| 920 | } else if (x.shift_imm_ != 0) { |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 921 | // Scaled register offset not supported, load index first |
| 922 | // rn (and rd in a load) should never be ip, or will be trashed. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 923 | ASSERT(!x.rn_.is(ip) && ((instr & L) == L || !rd.is(ip))); |
| 924 | mov(ip, Operand(x.rm_, x.shift_op_, x.shift_imm_), LeaveCC, |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 925 | Instruction::ConditionField(instr)); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 926 | addrmod3(instr, rd, MemOperand(x.rn_, ip, x.am_)); |
| 927 | return; |
| 928 | } else { |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 929 | // Register offset. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 930 | ASSERT((am & (P|W)) == P || !x.rm_.is(pc)); // no pc index with writeback |
| 931 | instr |= x.rm_.code(); |
| 932 | } |
| 933 | ASSERT((am & (P|W)) == P || !x.rn_.is(pc)); // no pc base with writeback |
| 934 | emit(instr | am | x.rn_.code()*B16 | rd.code()*B12); |
| 935 | } |
| 936 | |
| 937 | |
| 938 | void Assembler::addrmod4(Instr instr, Register rn, RegList rl) { |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 939 | ASSERT((instr & ~(kCondMask | P | U | W | L)) == B27); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 940 | ASSERT(rl != 0); |
| 941 | ASSERT(!rn.is(pc)); |
| 942 | emit(instr | rn.code()*B16 | rl); |
| 943 | } |
| 944 | |
| 945 | |
| 946 | void Assembler::addrmod5(Instr instr, CRegister crd, const MemOperand& x) { |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 947 | // Unindexed addressing is not encoded by this function. |
kasperl@chromium.org | b3284ad | 2009-05-18 06:12:45 +0000 | [diff] [blame] | 948 | ASSERT_EQ((B27 | B26), |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 949 | (instr & ~(kCondMask | kCoprocessorMask | P | U | N | W | L))); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 950 | ASSERT(x.rn_.is_valid() && !x.rm_.is_valid()); |
| 951 | int am = x.am_; |
| 952 | int offset_8 = x.offset_; |
| 953 | ASSERT((offset_8 & 3) == 0); // offset must be an aligned word offset |
| 954 | offset_8 >>= 2; |
| 955 | if (offset_8 < 0) { |
| 956 | offset_8 = -offset_8; |
| 957 | am ^= U; |
| 958 | } |
| 959 | ASSERT(is_uint8(offset_8)); // unsigned word offset must fit in a byte |
| 960 | ASSERT((am & (P|W)) == P || !x.rn_.is(pc)); // no pc base with writeback |
| 961 | |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 962 | // Post-indexed addressing requires W == 1; different than in addrmod2/3. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 963 | if ((am & P) == 0) |
| 964 | am |= W; |
| 965 | |
| 966 | ASSERT(offset_8 >= 0); // no masking needed |
| 967 | emit(instr | am | x.rn_.code()*B16 | crd.code()*B12 | offset_8); |
| 968 | } |
| 969 | |
| 970 | |
mads.s.ager@gmail.com | 769cc96 | 2008-08-06 10:02:49 +0000 | [diff] [blame] | 971 | int Assembler::branch_offset(Label* L, bool jump_elimination_allowed) { |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 972 | int target_pos; |
| 973 | if (L->is_bound()) { |
| 974 | target_pos = L->pos(); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 975 | } else { |
kasperl@chromium.org | 41044eb | 2008-10-06 08:24:46 +0000 | [diff] [blame] | 976 | if (L->is_linked()) { |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 977 | target_pos = L->pos(); // L's link |
kasperl@chromium.org | 41044eb | 2008-10-06 08:24:46 +0000 | [diff] [blame] | 978 | } else { |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 979 | target_pos = kEndOfChain; |
kasperl@chromium.org | 41044eb | 2008-10-06 08:24:46 +0000 | [diff] [blame] | 980 | } |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 981 | L->link_to(pc_offset()); |
| 982 | } |
| 983 | |
| 984 | // Block the emission of the constant pool, since the branch instruction must |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 985 | // be emitted at the pc offset recorded by the label. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 986 | BlockConstPoolBefore(pc_offset() + kInstrSize); |
ager@chromium.org | 18ad94b | 2009-09-02 08:22:29 +0000 | [diff] [blame] | 987 | return target_pos - (pc_offset() + kPcLoadDelta); |
| 988 | } |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 989 | |
ager@chromium.org | 18ad94b | 2009-09-02 08:22:29 +0000 | [diff] [blame] | 990 | |
| 991 | void Assembler::label_at_put(Label* L, int at_offset) { |
| 992 | int target_pos; |
| 993 | if (L->is_bound()) { |
| 994 | target_pos = L->pos(); |
| 995 | } else { |
| 996 | if (L->is_linked()) { |
| 997 | target_pos = L->pos(); // L's link |
| 998 | } else { |
| 999 | target_pos = kEndOfChain; |
| 1000 | } |
| 1001 | L->link_to(at_offset); |
| 1002 | instr_at_put(at_offset, target_pos + (Code::kHeaderSize - kHeapObjectTag)); |
| 1003 | } |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1004 | } |
| 1005 | |
| 1006 | |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 1007 | // Branch instructions. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1008 | void Assembler::b(int branch_offset, Condition cond) { |
| 1009 | ASSERT((branch_offset & 3) == 0); |
| 1010 | int imm24 = branch_offset >> 2; |
| 1011 | ASSERT(is_int24(imm24)); |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1012 | emit(cond | B27 | B25 | (imm24 & kImm24Mask)); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1013 | |
lrn@chromium.org | c34f580 | 2010-04-28 12:53:43 +0000 | [diff] [blame] | 1014 | if (cond == al) { |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 1015 | // Dead code is a good location to emit the constant pool. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1016 | CheckConstPool(false, false); |
lrn@chromium.org | c34f580 | 2010-04-28 12:53:43 +0000 | [diff] [blame] | 1017 | } |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1018 | } |
| 1019 | |
| 1020 | |
| 1021 | void Assembler::bl(int branch_offset, Condition cond) { |
kasperl@chromium.org | a555126 | 2010-12-07 12:49:48 +0000 | [diff] [blame] | 1022 | positions_recorder()->WriteRecordedPositions(); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1023 | ASSERT((branch_offset & 3) == 0); |
| 1024 | int imm24 = branch_offset >> 2; |
| 1025 | ASSERT(is_int24(imm24)); |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1026 | emit(cond | B27 | B25 | B24 | (imm24 & kImm24Mask)); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1027 | } |
| 1028 | |
| 1029 | |
| 1030 | void Assembler::blx(int branch_offset) { // v5 and above |
whesse@chromium.org | f0ac72d | 2010-11-08 12:47:26 +0000 | [diff] [blame] | 1031 | positions_recorder()->WriteRecordedPositions(); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1032 | ASSERT((branch_offset & 1) == 0); |
| 1033 | int h = ((branch_offset & 2) >> 1)*B24; |
| 1034 | int imm24 = branch_offset >> 2; |
| 1035 | ASSERT(is_int24(imm24)); |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1036 | emit(kSpecialCondition | B27 | B25 | h | (imm24 & kImm24Mask)); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1037 | } |
| 1038 | |
| 1039 | |
| 1040 | void Assembler::blx(Register target, Condition cond) { // v5 and above |
whesse@chromium.org | f0ac72d | 2010-11-08 12:47:26 +0000 | [diff] [blame] | 1041 | positions_recorder()->WriteRecordedPositions(); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1042 | ASSERT(!target.is(pc)); |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1043 | emit(cond | B24 | B21 | 15*B16 | 15*B12 | 15*B8 | BLX | target.code()); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1044 | } |
| 1045 | |
| 1046 | |
| 1047 | void Assembler::bx(Register target, Condition cond) { // v5 and above, plus v4t |
whesse@chromium.org | f0ac72d | 2010-11-08 12:47:26 +0000 | [diff] [blame] | 1048 | positions_recorder()->WriteRecordedPositions(); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1049 | ASSERT(!target.is(pc)); // use of pc is actually allowed, but discouraged |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1050 | emit(cond | B24 | B21 | 15*B16 | 15*B12 | 15*B8 | BX | target.code()); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1051 | } |
| 1052 | |
| 1053 | |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 1054 | // Data-processing instructions. |
| 1055 | |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1056 | void Assembler::and_(Register dst, Register src1, const Operand& src2, |
| 1057 | SBit s, Condition cond) { |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1058 | addrmod1(cond | AND | s, src1, dst, src2); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1059 | } |
| 1060 | |
| 1061 | |
| 1062 | void Assembler::eor(Register dst, Register src1, const Operand& src2, |
| 1063 | SBit s, Condition cond) { |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1064 | addrmod1(cond | EOR | s, src1, dst, src2); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1065 | } |
| 1066 | |
| 1067 | |
| 1068 | void Assembler::sub(Register dst, Register src1, const Operand& src2, |
| 1069 | SBit s, Condition cond) { |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1070 | addrmod1(cond | SUB | s, src1, dst, src2); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1071 | } |
| 1072 | |
| 1073 | |
| 1074 | void Assembler::rsb(Register dst, Register src1, const Operand& src2, |
| 1075 | SBit s, Condition cond) { |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1076 | addrmod1(cond | RSB | s, src1, dst, src2); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1077 | } |
| 1078 | |
| 1079 | |
| 1080 | void Assembler::add(Register dst, Register src1, const Operand& src2, |
| 1081 | SBit s, Condition cond) { |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1082 | addrmod1(cond | ADD | s, src1, dst, src2); |
mads.s.ager | 31e7138 | 2008-08-13 09:32:07 +0000 | [diff] [blame] | 1083 | |
| 1084 | // Eliminate pattern: push(r), pop() |
| 1085 | // str(src, MemOperand(sp, 4, NegPreIndex), al); |
| 1086 | // add(sp, sp, Operand(kPointerSize)); |
| 1087 | // Both instructions can be eliminated. |
erik.corry@gmail.com | 9dfbea4 | 2010-05-21 12:58:28 +0000 | [diff] [blame] | 1088 | if (can_peephole_optimize(2) && |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 1089 | // Pattern. |
mads.s.ager | 31e7138 | 2008-08-13 09:32:07 +0000 | [diff] [blame] | 1090 | instr_at(pc_ - 1 * kInstrSize) == kPopInstruction && |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1091 | (instr_at(pc_ - 2 * kInstrSize) & ~kRdMask) == kPushRegPattern) { |
mads.s.ager | 31e7138 | 2008-08-13 09:32:07 +0000 | [diff] [blame] | 1092 | pc_ -= 2 * kInstrSize; |
erik.corry@gmail.com | 9dfbea4 | 2010-05-21 12:58:28 +0000 | [diff] [blame] | 1093 | if (FLAG_print_peephole_optimization) { |
mads.s.ager | 31e7138 | 2008-08-13 09:32:07 +0000 | [diff] [blame] | 1094 | PrintF("%x push(reg)/pop() eliminated\n", pc_offset()); |
| 1095 | } |
| 1096 | } |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1097 | } |
| 1098 | |
| 1099 | |
| 1100 | void Assembler::adc(Register dst, Register src1, const Operand& src2, |
| 1101 | SBit s, Condition cond) { |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1102 | addrmod1(cond | ADC | s, src1, dst, src2); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1103 | } |
| 1104 | |
| 1105 | |
| 1106 | void Assembler::sbc(Register dst, Register src1, const Operand& src2, |
| 1107 | SBit s, Condition cond) { |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1108 | addrmod1(cond | SBC | s, src1, dst, src2); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1109 | } |
| 1110 | |
| 1111 | |
| 1112 | void Assembler::rsc(Register dst, Register src1, const Operand& src2, |
| 1113 | SBit s, Condition cond) { |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1114 | addrmod1(cond | RSC | s, src1, dst, src2); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1115 | } |
| 1116 | |
| 1117 | |
| 1118 | void Assembler::tst(Register src1, const Operand& src2, Condition cond) { |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1119 | addrmod1(cond | TST | S, src1, r0, src2); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1120 | } |
| 1121 | |
| 1122 | |
| 1123 | void Assembler::teq(Register src1, const Operand& src2, Condition cond) { |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1124 | addrmod1(cond | TEQ | S, src1, r0, src2); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1125 | } |
| 1126 | |
| 1127 | |
| 1128 | void Assembler::cmp(Register src1, const Operand& src2, Condition cond) { |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1129 | addrmod1(cond | CMP | S, src1, r0, src2); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1130 | } |
| 1131 | |
| 1132 | |
sgjesse@chromium.org | 496c03a | 2011-02-14 12:05:43 +0000 | [diff] [blame] | 1133 | void Assembler::cmp_raw_immediate( |
| 1134 | Register src, int raw_immediate, Condition cond) { |
| 1135 | ASSERT(is_uint12(raw_immediate)); |
| 1136 | emit(cond | I | CMP | S | src.code() << 16 | raw_immediate); |
| 1137 | } |
| 1138 | |
| 1139 | |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1140 | void Assembler::cmn(Register src1, const Operand& src2, Condition cond) { |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1141 | addrmod1(cond | CMN | S, src1, r0, src2); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1142 | } |
| 1143 | |
| 1144 | |
| 1145 | void Assembler::orr(Register dst, Register src1, const Operand& src2, |
| 1146 | SBit s, Condition cond) { |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1147 | addrmod1(cond | ORR | s, src1, dst, src2); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1148 | } |
| 1149 | |
| 1150 | |
| 1151 | void Assembler::mov(Register dst, const Operand& src, SBit s, Condition cond) { |
kasperl@chromium.org | defbd10 | 2009-07-13 14:04:26 +0000 | [diff] [blame] | 1152 | if (dst.is(pc)) { |
whesse@chromium.org | f0ac72d | 2010-11-08 12:47:26 +0000 | [diff] [blame] | 1153 | positions_recorder()->WriteRecordedPositions(); |
kasperl@chromium.org | defbd10 | 2009-07-13 14:04:26 +0000 | [diff] [blame] | 1154 | } |
fschneider@chromium.org | 013f3e1 | 2010-04-26 13:27:52 +0000 | [diff] [blame] | 1155 | // Don't allow nop instructions in the form mov rn, rn to be generated using |
ager@chromium.org | beb2571 | 2010-11-29 08:02:25 +0000 | [diff] [blame] | 1156 | // the mov instruction. They must be generated using nop(int/NopMarkerTypes) |
| 1157 | // or MarkCode(int/NopMarkerTypes) pseudo instructions. |
fschneider@chromium.org | 013f3e1 | 2010-04-26 13:27:52 +0000 | [diff] [blame] | 1158 | ASSERT(!(src.is_reg() && src.rm().is(dst) && s == LeaveCC && cond == al)); |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1159 | addrmod1(cond | MOV | s, r0, dst, src); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1160 | } |
| 1161 | |
| 1162 | |
ricow@chromium.org | 5ad5ace | 2010-06-23 09:06:43 +0000 | [diff] [blame] | 1163 | void Assembler::movw(Register reg, uint32_t immediate, Condition cond) { |
| 1164 | ASSERT(immediate < 0x10000); |
| 1165 | mov(reg, Operand(immediate), LeaveCC, cond); |
| 1166 | } |
| 1167 | |
| 1168 | |
| 1169 | void Assembler::movt(Register reg, uint32_t immediate, Condition cond) { |
| 1170 | emit(cond | 0x34*B20 | reg.code()*B12 | EncodeMovwImmediate(immediate)); |
| 1171 | } |
| 1172 | |
| 1173 | |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1174 | void Assembler::bic(Register dst, Register src1, const Operand& src2, |
| 1175 | SBit s, Condition cond) { |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1176 | addrmod1(cond | BIC | s, src1, dst, src2); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1177 | } |
| 1178 | |
| 1179 | |
| 1180 | void Assembler::mvn(Register dst, const Operand& src, SBit s, Condition cond) { |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1181 | addrmod1(cond | MVN | s, r0, dst, src); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1182 | } |
| 1183 | |
| 1184 | |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 1185 | // Multiply instructions. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1186 | void Assembler::mla(Register dst, Register src1, Register src2, Register srcA, |
| 1187 | SBit s, Condition cond) { |
| 1188 | ASSERT(!dst.is(pc) && !src1.is(pc) && !src2.is(pc) && !srcA.is(pc)); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1189 | emit(cond | A | s | dst.code()*B16 | srcA.code()*B12 | |
| 1190 | src2.code()*B8 | B7 | B4 | src1.code()); |
| 1191 | } |
| 1192 | |
| 1193 | |
| 1194 | void Assembler::mul(Register dst, Register src1, Register src2, |
| 1195 | SBit s, Condition cond) { |
| 1196 | ASSERT(!dst.is(pc) && !src1.is(pc) && !src2.is(pc)); |
kasperl@chromium.org | 86f77b7 | 2009-07-06 08:21:57 +0000 | [diff] [blame] | 1197 | // dst goes in bits 16-19 for this instruction! |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1198 | emit(cond | s | dst.code()*B16 | src2.code()*B8 | B7 | B4 | src1.code()); |
| 1199 | } |
| 1200 | |
| 1201 | |
| 1202 | void Assembler::smlal(Register dstL, |
| 1203 | Register dstH, |
| 1204 | Register src1, |
| 1205 | Register src2, |
| 1206 | SBit s, |
| 1207 | Condition cond) { |
| 1208 | ASSERT(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc)); |
kasperl@chromium.org | 2abc450 | 2009-07-02 07:00:29 +0000 | [diff] [blame] | 1209 | ASSERT(!dstL.is(dstH)); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1210 | emit(cond | B23 | B22 | A | s | dstH.code()*B16 | dstL.code()*B12 | |
| 1211 | src2.code()*B8 | B7 | B4 | src1.code()); |
| 1212 | } |
| 1213 | |
| 1214 | |
| 1215 | void Assembler::smull(Register dstL, |
| 1216 | Register dstH, |
| 1217 | Register src1, |
| 1218 | Register src2, |
| 1219 | SBit s, |
| 1220 | Condition cond) { |
| 1221 | ASSERT(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc)); |
kasperl@chromium.org | 2abc450 | 2009-07-02 07:00:29 +0000 | [diff] [blame] | 1222 | ASSERT(!dstL.is(dstH)); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1223 | emit(cond | B23 | B22 | s | dstH.code()*B16 | dstL.code()*B12 | |
| 1224 | src2.code()*B8 | B7 | B4 | src1.code()); |
| 1225 | } |
| 1226 | |
| 1227 | |
| 1228 | void Assembler::umlal(Register dstL, |
| 1229 | Register dstH, |
| 1230 | Register src1, |
| 1231 | Register src2, |
| 1232 | SBit s, |
| 1233 | Condition cond) { |
| 1234 | ASSERT(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc)); |
kasperl@chromium.org | 2abc450 | 2009-07-02 07:00:29 +0000 | [diff] [blame] | 1235 | ASSERT(!dstL.is(dstH)); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1236 | emit(cond | B23 | A | s | dstH.code()*B16 | dstL.code()*B12 | |
| 1237 | src2.code()*B8 | B7 | B4 | src1.code()); |
| 1238 | } |
| 1239 | |
| 1240 | |
| 1241 | void Assembler::umull(Register dstL, |
| 1242 | Register dstH, |
| 1243 | Register src1, |
| 1244 | Register src2, |
| 1245 | SBit s, |
| 1246 | Condition cond) { |
| 1247 | ASSERT(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc)); |
kasperl@chromium.org | 2abc450 | 2009-07-02 07:00:29 +0000 | [diff] [blame] | 1248 | ASSERT(!dstL.is(dstH)); |
kasperl@chromium.org | 86f77b7 | 2009-07-06 08:21:57 +0000 | [diff] [blame] | 1249 | emit(cond | B23 | s | dstH.code()*B16 | dstL.code()*B12 | |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1250 | src2.code()*B8 | B7 | B4 | src1.code()); |
| 1251 | } |
| 1252 | |
| 1253 | |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 1254 | // Miscellaneous arithmetic instructions. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1255 | void Assembler::clz(Register dst, Register src, Condition cond) { |
| 1256 | // v5 and above. |
| 1257 | ASSERT(!dst.is(pc) && !src.is(pc)); |
| 1258 | emit(cond | B24 | B22 | B21 | 15*B16 | dst.code()*B12 | |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1259 | 15*B8 | CLZ | src.code()); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1260 | } |
| 1261 | |
| 1262 | |
fschneider@chromium.org | ed78ffd | 2010-07-21 11:05:19 +0000 | [diff] [blame] | 1263 | // Saturating instructions. |
| 1264 | |
| 1265 | // Unsigned saturate. |
| 1266 | void Assembler::usat(Register dst, |
| 1267 | int satpos, |
| 1268 | const Operand& src, |
| 1269 | Condition cond) { |
| 1270 | // v6 and above. |
kmillikin@chromium.org | c36ce6e | 2011-04-04 08:25:31 +0000 | [diff] [blame] | 1271 | ASSERT(CpuFeatures::IsSupported(ARMv7)); |
fschneider@chromium.org | ed78ffd | 2010-07-21 11:05:19 +0000 | [diff] [blame] | 1272 | ASSERT(!dst.is(pc) && !src.rm_.is(pc)); |
| 1273 | ASSERT((satpos >= 0) && (satpos <= 31)); |
| 1274 | ASSERT((src.shift_op_ == ASR) || (src.shift_op_ == LSL)); |
| 1275 | ASSERT(src.rs_.is(no_reg)); |
| 1276 | |
| 1277 | int sh = 0; |
| 1278 | if (src.shift_op_ == ASR) { |
| 1279 | sh = 1; |
| 1280 | } |
| 1281 | |
| 1282 | emit(cond | 0x6*B24 | 0xe*B20 | satpos*B16 | dst.code()*B12 | |
| 1283 | src.shift_imm_*B7 | sh*B6 | 0x1*B4 | src.rm_.code()); |
| 1284 | } |
| 1285 | |
| 1286 | |
ricow@chromium.org | 30ce411 | 2010-05-31 10:38:25 +0000 | [diff] [blame] | 1287 | // Bitfield manipulation instructions. |
| 1288 | |
| 1289 | // Unsigned bit field extract. |
| 1290 | // Extracts #width adjacent bits from position #lsb in a register, and |
| 1291 | // writes them to the low bits of a destination register. |
| 1292 | // ubfx dst, src, #lsb, #width |
| 1293 | void Assembler::ubfx(Register dst, |
| 1294 | Register src, |
| 1295 | int lsb, |
| 1296 | int width, |
| 1297 | Condition cond) { |
| 1298 | // v7 and above. |
kmillikin@chromium.org | c36ce6e | 2011-04-04 08:25:31 +0000 | [diff] [blame] | 1299 | ASSERT(CpuFeatures::IsSupported(ARMv7)); |
ricow@chromium.org | 30ce411 | 2010-05-31 10:38:25 +0000 | [diff] [blame] | 1300 | ASSERT(!dst.is(pc) && !src.is(pc)); |
| 1301 | ASSERT((lsb >= 0) && (lsb <= 31)); |
| 1302 | ASSERT((width >= 1) && (width <= (32 - lsb))); |
| 1303 | emit(cond | 0xf*B23 | B22 | B21 | (width - 1)*B16 | dst.code()*B12 | |
| 1304 | lsb*B7 | B6 | B4 | src.code()); |
| 1305 | } |
| 1306 | |
| 1307 | |
| 1308 | // Signed bit field extract. |
| 1309 | // Extracts #width adjacent bits from position #lsb in a register, and |
| 1310 | // writes them to the low bits of a destination register. The extracted |
| 1311 | // value is sign extended to fill the destination register. |
| 1312 | // sbfx dst, src, #lsb, #width |
| 1313 | void Assembler::sbfx(Register dst, |
| 1314 | Register src, |
| 1315 | int lsb, |
| 1316 | int width, |
| 1317 | Condition cond) { |
| 1318 | // v7 and above. |
kmillikin@chromium.org | c36ce6e | 2011-04-04 08:25:31 +0000 | [diff] [blame] | 1319 | ASSERT(CpuFeatures::IsSupported(ARMv7)); |
ricow@chromium.org | 30ce411 | 2010-05-31 10:38:25 +0000 | [diff] [blame] | 1320 | ASSERT(!dst.is(pc) && !src.is(pc)); |
| 1321 | ASSERT((lsb >= 0) && (lsb <= 31)); |
| 1322 | ASSERT((width >= 1) && (width <= (32 - lsb))); |
| 1323 | emit(cond | 0xf*B23 | B21 | (width - 1)*B16 | dst.code()*B12 | |
| 1324 | lsb*B7 | B6 | B4 | src.code()); |
| 1325 | } |
| 1326 | |
| 1327 | |
| 1328 | // Bit field clear. |
| 1329 | // Sets #width adjacent bits at position #lsb in the destination register |
| 1330 | // to zero, preserving the value of the other bits. |
| 1331 | // bfc dst, #lsb, #width |
| 1332 | void Assembler::bfc(Register dst, int lsb, int width, Condition cond) { |
| 1333 | // v7 and above. |
kmillikin@chromium.org | c36ce6e | 2011-04-04 08:25:31 +0000 | [diff] [blame] | 1334 | ASSERT(CpuFeatures::IsSupported(ARMv7)); |
ricow@chromium.org | 30ce411 | 2010-05-31 10:38:25 +0000 | [diff] [blame] | 1335 | ASSERT(!dst.is(pc)); |
| 1336 | ASSERT((lsb >= 0) && (lsb <= 31)); |
| 1337 | ASSERT((width >= 1) && (width <= (32 - lsb))); |
| 1338 | int msb = lsb + width - 1; |
| 1339 | emit(cond | 0x1f*B22 | msb*B16 | dst.code()*B12 | lsb*B7 | B4 | 0xf); |
| 1340 | } |
| 1341 | |
| 1342 | |
| 1343 | // Bit field insert. |
| 1344 | // Inserts #width adjacent bits from the low bits of the source register |
| 1345 | // into position #lsb of the destination register. |
| 1346 | // bfi dst, src, #lsb, #width |
| 1347 | void Assembler::bfi(Register dst, |
| 1348 | Register src, |
| 1349 | int lsb, |
| 1350 | int width, |
| 1351 | Condition cond) { |
| 1352 | // v7 and above. |
kmillikin@chromium.org | c36ce6e | 2011-04-04 08:25:31 +0000 | [diff] [blame] | 1353 | ASSERT(CpuFeatures::IsSupported(ARMv7)); |
ricow@chromium.org | 30ce411 | 2010-05-31 10:38:25 +0000 | [diff] [blame] | 1354 | ASSERT(!dst.is(pc) && !src.is(pc)); |
| 1355 | ASSERT((lsb >= 0) && (lsb <= 31)); |
| 1356 | ASSERT((width >= 1) && (width <= (32 - lsb))); |
| 1357 | int msb = lsb + width - 1; |
| 1358 | emit(cond | 0x1f*B22 | msb*B16 | dst.code()*B12 | lsb*B7 | B4 | |
| 1359 | src.code()); |
| 1360 | } |
| 1361 | |
| 1362 | |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 1363 | // Status register access instructions. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1364 | void Assembler::mrs(Register dst, SRegister s, Condition cond) { |
| 1365 | ASSERT(!dst.is(pc)); |
| 1366 | emit(cond | B24 | s | 15*B16 | dst.code()*B12); |
| 1367 | } |
| 1368 | |
| 1369 | |
| 1370 | void Assembler::msr(SRegisterFieldMask fields, const Operand& src, |
| 1371 | Condition cond) { |
| 1372 | ASSERT(fields >= B16 && fields < B20); // at least one field set |
| 1373 | Instr instr; |
| 1374 | if (!src.rm_.is_valid()) { |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 1375 | // Immediate. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1376 | uint32_t rotate_imm; |
| 1377 | uint32_t immed_8; |
whesse@chromium.org | f0ac72d | 2010-11-08 12:47:26 +0000 | [diff] [blame] | 1378 | if (src.must_use_constant_pool() || |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1379 | !fits_shifter(src.imm32_, &rotate_imm, &immed_8, NULL)) { |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 1380 | // Immediate operand cannot be encoded, load it first to register ip. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1381 | RecordRelocInfo(src.rmode_, src.imm32_); |
| 1382 | ldr(ip, MemOperand(pc, 0), cond); |
| 1383 | msr(fields, Operand(ip), cond); |
| 1384 | return; |
| 1385 | } |
| 1386 | instr = I | rotate_imm*B8 | immed_8; |
| 1387 | } else { |
| 1388 | ASSERT(!src.rs_.is_valid() && src.shift_imm_ == 0); // only rm allowed |
| 1389 | instr = src.rm_.code(); |
| 1390 | } |
| 1391 | emit(cond | instr | B24 | B21 | fields | 15*B12); |
| 1392 | } |
| 1393 | |
| 1394 | |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 1395 | // Load/Store instructions. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1396 | void Assembler::ldr(Register dst, const MemOperand& src, Condition cond) { |
kasperl@chromium.org | defbd10 | 2009-07-13 14:04:26 +0000 | [diff] [blame] | 1397 | if (dst.is(pc)) { |
whesse@chromium.org | f0ac72d | 2010-11-08 12:47:26 +0000 | [diff] [blame] | 1398 | positions_recorder()->WriteRecordedPositions(); |
kasperl@chromium.org | defbd10 | 2009-07-13 14:04:26 +0000 | [diff] [blame] | 1399 | } |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1400 | addrmod2(cond | B26 | L, dst, src); |
mads.s.ager | 31e7138 | 2008-08-13 09:32:07 +0000 | [diff] [blame] | 1401 | |
erik.corry@gmail.com | 9dfbea4 | 2010-05-21 12:58:28 +0000 | [diff] [blame] | 1402 | // Eliminate pattern: push(ry), pop(rx) |
| 1403 | // str(ry, MemOperand(sp, 4, NegPreIndex), al) |
| 1404 | // ldr(rx, MemOperand(sp, 4, PostIndex), al) |
| 1405 | // Both instructions can be eliminated if ry = rx. |
| 1406 | // If ry != rx, a register copy from ry to rx is inserted |
| 1407 | // after eliminating the push and the pop instructions. |
sgjesse@chromium.org | 82dbbab | 2010-06-02 08:57:44 +0000 | [diff] [blame] | 1408 | if (can_peephole_optimize(2)) { |
| 1409 | Instr push_instr = instr_at(pc_ - 2 * kInstrSize); |
| 1410 | Instr pop_instr = instr_at(pc_ - 1 * kInstrSize); |
erik.corry@gmail.com | 9dfbea4 | 2010-05-21 12:58:28 +0000 | [diff] [blame] | 1411 | |
sgjesse@chromium.org | 82dbbab | 2010-06-02 08:57:44 +0000 | [diff] [blame] | 1412 | if (IsPush(push_instr) && IsPop(pop_instr)) { |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1413 | if (Instruction::RdValue(pop_instr) != Instruction::RdValue(push_instr)) { |
sgjesse@chromium.org | 82dbbab | 2010-06-02 08:57:44 +0000 | [diff] [blame] | 1414 | // For consecutive push and pop on different registers, |
| 1415 | // we delete both the push & pop and insert a register move. |
| 1416 | // push ry, pop rx --> mov rx, ry |
| 1417 | Register reg_pushed, reg_popped; |
| 1418 | reg_pushed = GetRd(push_instr); |
| 1419 | reg_popped = GetRd(pop_instr); |
| 1420 | pc_ -= 2 * kInstrSize; |
| 1421 | // Insert a mov instruction, which is better than a pair of push & pop |
| 1422 | mov(reg_popped, reg_pushed); |
| 1423 | if (FLAG_print_peephole_optimization) { |
| 1424 | PrintF("%x push/pop (diff reg) replaced by a reg move\n", |
| 1425 | pc_offset()); |
| 1426 | } |
| 1427 | } else { |
| 1428 | // For consecutive push and pop on the same register, |
| 1429 | // both the push and the pop can be deleted. |
| 1430 | pc_ -= 2 * kInstrSize; |
| 1431 | if (FLAG_print_peephole_optimization) { |
| 1432 | PrintF("%x push/pop (same reg) eliminated\n", pc_offset()); |
| 1433 | } |
erik.corry@gmail.com | 9dfbea4 | 2010-05-21 12:58:28 +0000 | [diff] [blame] | 1434 | } |
| 1435 | } |
| 1436 | } |
| 1437 | |
| 1438 | if (can_peephole_optimize(2)) { |
| 1439 | Instr str_instr = instr_at(pc_ - 2 * kInstrSize); |
| 1440 | Instr ldr_instr = instr_at(pc_ - 1 * kInstrSize); |
| 1441 | |
| 1442 | if ((IsStrRegFpOffset(str_instr) && |
| 1443 | IsLdrRegFpOffset(ldr_instr)) || |
| 1444 | (IsStrRegFpNegOffset(str_instr) && |
| 1445 | IsLdrRegFpNegOffset(ldr_instr))) { |
| 1446 | if ((ldr_instr & kLdrStrInstrArgumentMask) == |
| 1447 | (str_instr & kLdrStrInstrArgumentMask)) { |
| 1448 | // Pattern: Ldr/str same fp+offset, same register. |
| 1449 | // |
| 1450 | // The following: |
| 1451 | // str rx, [fp, #-12] |
| 1452 | // ldr rx, [fp, #-12] |
| 1453 | // |
| 1454 | // Becomes: |
| 1455 | // str rx, [fp, #-12] |
| 1456 | |
| 1457 | pc_ -= 1 * kInstrSize; |
| 1458 | if (FLAG_print_peephole_optimization) { |
| 1459 | PrintF("%x str/ldr (fp + same offset), same reg\n", pc_offset()); |
| 1460 | } |
| 1461 | } else if ((ldr_instr & kLdrStrOffsetMask) == |
| 1462 | (str_instr & kLdrStrOffsetMask)) { |
| 1463 | // Pattern: Ldr/str same fp+offset, different register. |
| 1464 | // |
| 1465 | // The following: |
| 1466 | // str rx, [fp, #-12] |
| 1467 | // ldr ry, [fp, #-12] |
| 1468 | // |
| 1469 | // Becomes: |
| 1470 | // str rx, [fp, #-12] |
| 1471 | // mov ry, rx |
| 1472 | |
| 1473 | Register reg_stored, reg_loaded; |
| 1474 | reg_stored = GetRd(str_instr); |
| 1475 | reg_loaded = GetRd(ldr_instr); |
| 1476 | pc_ -= 1 * kInstrSize; |
| 1477 | // Insert a mov instruction, which is better than ldr. |
| 1478 | mov(reg_loaded, reg_stored); |
| 1479 | if (FLAG_print_peephole_optimization) { |
| 1480 | PrintF("%x str/ldr (fp + same offset), diff reg \n", pc_offset()); |
| 1481 | } |
| 1482 | } |
| 1483 | } |
| 1484 | } |
| 1485 | |
| 1486 | if (can_peephole_optimize(3)) { |
| 1487 | Instr mem_write_instr = instr_at(pc_ - 3 * kInstrSize); |
| 1488 | Instr ldr_instr = instr_at(pc_ - 2 * kInstrSize); |
| 1489 | Instr mem_read_instr = instr_at(pc_ - 1 * kInstrSize); |
| 1490 | if (IsPush(mem_write_instr) && |
| 1491 | IsPop(mem_read_instr)) { |
| 1492 | if ((IsLdrRegFpOffset(ldr_instr) || |
| 1493 | IsLdrRegFpNegOffset(ldr_instr))) { |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1494 | if (Instruction::RdValue(mem_write_instr) == |
| 1495 | Instruction::RdValue(mem_read_instr)) { |
erik.corry@gmail.com | 9dfbea4 | 2010-05-21 12:58:28 +0000 | [diff] [blame] | 1496 | // Pattern: push & pop from/to same register, |
| 1497 | // with a fp+offset ldr in between |
| 1498 | // |
| 1499 | // The following: |
| 1500 | // str rx, [sp, #-4]! |
| 1501 | // ldr rz, [fp, #-24] |
| 1502 | // ldr rx, [sp], #+4 |
| 1503 | // |
| 1504 | // Becomes: |
| 1505 | // if(rx == rz) |
| 1506 | // delete all |
| 1507 | // else |
| 1508 | // ldr rz, [fp, #-24] |
| 1509 | |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1510 | if (Instruction::RdValue(mem_write_instr) == |
| 1511 | Instruction::RdValue(ldr_instr)) { |
erik.corry@gmail.com | 9dfbea4 | 2010-05-21 12:58:28 +0000 | [diff] [blame] | 1512 | pc_ -= 3 * kInstrSize; |
| 1513 | } else { |
| 1514 | pc_ -= 3 * kInstrSize; |
| 1515 | // Reinsert back the ldr rz. |
| 1516 | emit(ldr_instr); |
| 1517 | } |
| 1518 | if (FLAG_print_peephole_optimization) { |
| 1519 | PrintF("%x push/pop -dead ldr fp+offset in middle\n", pc_offset()); |
| 1520 | } |
| 1521 | } else { |
| 1522 | // Pattern: push & pop from/to different registers |
| 1523 | // with a fp+offset ldr in between |
| 1524 | // |
| 1525 | // The following: |
| 1526 | // str rx, [sp, #-4]! |
| 1527 | // ldr rz, [fp, #-24] |
| 1528 | // ldr ry, [sp], #+4 |
| 1529 | // |
| 1530 | // Becomes: |
| 1531 | // if(ry == rz) |
| 1532 | // mov ry, rx; |
| 1533 | // else if(rx != rz) |
| 1534 | // ldr rz, [fp, #-24] |
| 1535 | // mov ry, rx |
| 1536 | // else if((ry != rz) || (rx == rz)) becomes: |
| 1537 | // mov ry, rx |
| 1538 | // ldr rz, [fp, #-24] |
| 1539 | |
| 1540 | Register reg_pushed, reg_popped; |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1541 | if (Instruction::RdValue(mem_read_instr) == |
| 1542 | Instruction::RdValue(ldr_instr)) { |
erik.corry@gmail.com | 9dfbea4 | 2010-05-21 12:58:28 +0000 | [diff] [blame] | 1543 | reg_pushed = GetRd(mem_write_instr); |
| 1544 | reg_popped = GetRd(mem_read_instr); |
| 1545 | pc_ -= 3 * kInstrSize; |
| 1546 | mov(reg_popped, reg_pushed); |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1547 | } else if (Instruction::RdValue(mem_write_instr) != |
| 1548 | Instruction::RdValue(ldr_instr)) { |
erik.corry@gmail.com | 9dfbea4 | 2010-05-21 12:58:28 +0000 | [diff] [blame] | 1549 | reg_pushed = GetRd(mem_write_instr); |
| 1550 | reg_popped = GetRd(mem_read_instr); |
| 1551 | pc_ -= 3 * kInstrSize; |
| 1552 | emit(ldr_instr); |
| 1553 | mov(reg_popped, reg_pushed); |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1554 | } else if ((Instruction::RdValue(mem_read_instr) != |
| 1555 | Instruction::RdValue(ldr_instr)) || |
| 1556 | (Instruction::RdValue(mem_write_instr) == |
| 1557 | Instruction::RdValue(ldr_instr))) { |
erik.corry@gmail.com | 9dfbea4 | 2010-05-21 12:58:28 +0000 | [diff] [blame] | 1558 | reg_pushed = GetRd(mem_write_instr); |
| 1559 | reg_popped = GetRd(mem_read_instr); |
| 1560 | pc_ -= 3 * kInstrSize; |
| 1561 | mov(reg_popped, reg_pushed); |
| 1562 | emit(ldr_instr); |
| 1563 | } |
| 1564 | if (FLAG_print_peephole_optimization) { |
| 1565 | PrintF("%x push/pop (ldr fp+off in middle)\n", pc_offset()); |
| 1566 | } |
| 1567 | } |
| 1568 | } |
mads.s.ager | 31e7138 | 2008-08-13 09:32:07 +0000 | [diff] [blame] | 1569 | } |
| 1570 | } |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1571 | } |
| 1572 | |
| 1573 | |
| 1574 | void Assembler::str(Register src, const MemOperand& dst, Condition cond) { |
| 1575 | addrmod2(cond | B26, src, dst); |
mads.s.ager | 31e7138 | 2008-08-13 09:32:07 +0000 | [diff] [blame] | 1576 | |
| 1577 | // Eliminate pattern: pop(), push(r) |
| 1578 | // add sp, sp, #4 LeaveCC, al; str r, [sp, #-4], al |
| 1579 | // -> str r, [sp, 0], al |
erik.corry@gmail.com | 9dfbea4 | 2010-05-21 12:58:28 +0000 | [diff] [blame] | 1580 | if (can_peephole_optimize(2) && |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 1581 | // Pattern. |
mads.s.ager | 31e7138 | 2008-08-13 09:32:07 +0000 | [diff] [blame] | 1582 | instr_at(pc_ - 1 * kInstrSize) == (kPushRegPattern | src.code() * B12) && |
| 1583 | instr_at(pc_ - 2 * kInstrSize) == kPopInstruction) { |
| 1584 | pc_ -= 2 * kInstrSize; |
| 1585 | emit(al | B26 | 0 | Offset | sp.code() * B16 | src.code() * B12); |
erik.corry@gmail.com | 9dfbea4 | 2010-05-21 12:58:28 +0000 | [diff] [blame] | 1586 | if (FLAG_print_peephole_optimization) { |
mads.s.ager | 31e7138 | 2008-08-13 09:32:07 +0000 | [diff] [blame] | 1587 | PrintF("%x pop()/push(reg) eliminated\n", pc_offset()); |
| 1588 | } |
| 1589 | } |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1590 | } |
| 1591 | |
| 1592 | |
| 1593 | void Assembler::ldrb(Register dst, const MemOperand& src, Condition cond) { |
| 1594 | addrmod2(cond | B26 | B | L, dst, src); |
| 1595 | } |
| 1596 | |
| 1597 | |
| 1598 | void Assembler::strb(Register src, const MemOperand& dst, Condition cond) { |
| 1599 | addrmod2(cond | B26 | B, src, dst); |
| 1600 | } |
| 1601 | |
| 1602 | |
| 1603 | void Assembler::ldrh(Register dst, const MemOperand& src, Condition cond) { |
| 1604 | addrmod3(cond | L | B7 | H | B4, dst, src); |
| 1605 | } |
| 1606 | |
| 1607 | |
| 1608 | void Assembler::strh(Register src, const MemOperand& dst, Condition cond) { |
| 1609 | addrmod3(cond | B7 | H | B4, src, dst); |
| 1610 | } |
| 1611 | |
| 1612 | |
| 1613 | void Assembler::ldrsb(Register dst, const MemOperand& src, Condition cond) { |
| 1614 | addrmod3(cond | L | B7 | S6 | B4, dst, src); |
| 1615 | } |
| 1616 | |
| 1617 | |
| 1618 | void Assembler::ldrsh(Register dst, const MemOperand& src, Condition cond) { |
| 1619 | addrmod3(cond | L | B7 | S6 | H | B4, dst, src); |
| 1620 | } |
| 1621 | |
| 1622 | |
kmillikin@chromium.org | 9155e25 | 2010-05-26 13:27:57 +0000 | [diff] [blame] | 1623 | void Assembler::ldrd(Register dst1, Register dst2, |
| 1624 | const MemOperand& src, Condition cond) { |
kmillikin@chromium.org | c36ce6e | 2011-04-04 08:25:31 +0000 | [diff] [blame] | 1625 | ASSERT(CpuFeatures::IsEnabled(ARMv7)); |
sgjesse@chromium.org | 720dc0b | 2010-05-10 09:25:39 +0000 | [diff] [blame] | 1626 | ASSERT(src.rm().is(no_reg)); |
kmillikin@chromium.org | 9155e25 | 2010-05-26 13:27:57 +0000 | [diff] [blame] | 1627 | ASSERT(!dst1.is(lr)); // r14. |
| 1628 | ASSERT_EQ(0, dst1.code() % 2); |
| 1629 | ASSERT_EQ(dst1.code() + 1, dst2.code()); |
| 1630 | addrmod3(cond | B7 | B6 | B4, dst1, src); |
sgjesse@chromium.org | 720dc0b | 2010-05-10 09:25:39 +0000 | [diff] [blame] | 1631 | } |
| 1632 | |
| 1633 | |
kmillikin@chromium.org | 9155e25 | 2010-05-26 13:27:57 +0000 | [diff] [blame] | 1634 | void Assembler::strd(Register src1, Register src2, |
| 1635 | const MemOperand& dst, Condition cond) { |
sgjesse@chromium.org | 720dc0b | 2010-05-10 09:25:39 +0000 | [diff] [blame] | 1636 | ASSERT(dst.rm().is(no_reg)); |
kmillikin@chromium.org | 9155e25 | 2010-05-26 13:27:57 +0000 | [diff] [blame] | 1637 | ASSERT(!src1.is(lr)); // r14. |
| 1638 | ASSERT_EQ(0, src1.code() % 2); |
| 1639 | ASSERT_EQ(src1.code() + 1, src2.code()); |
kmillikin@chromium.org | c36ce6e | 2011-04-04 08:25:31 +0000 | [diff] [blame] | 1640 | ASSERT(CpuFeatures::IsEnabled(ARMv7)); |
kmillikin@chromium.org | 9155e25 | 2010-05-26 13:27:57 +0000 | [diff] [blame] | 1641 | addrmod3(cond | B7 | B6 | B5 | B4, src1, dst); |
sgjesse@chromium.org | 720dc0b | 2010-05-10 09:25:39 +0000 | [diff] [blame] | 1642 | } |
| 1643 | |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 1644 | // Load/Store multiple instructions. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1645 | void Assembler::ldm(BlockAddrMode am, |
| 1646 | Register base, |
| 1647 | RegList dst, |
| 1648 | Condition cond) { |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 1649 | // ABI stack constraint: ldmxx base, {..sp..} base != sp is not restartable. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1650 | ASSERT(base.is(sp) || (dst & sp.bit()) == 0); |
| 1651 | |
| 1652 | addrmod4(cond | B27 | am | L, base, dst); |
| 1653 | |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 1654 | // Emit the constant pool after a function return implemented by ldm ..{..pc}. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1655 | if (cond == al && (dst & pc.bit()) != 0) { |
| 1656 | // There is a slight chance that the ldm instruction was actually a call, |
| 1657 | // in which case it would be wrong to return into the constant pool; we |
| 1658 | // recognize this case by checking if the emission of the pool was blocked |
| 1659 | // at the pc of the ldm instruction by a mov lr, pc instruction; if this is |
| 1660 | // the case, we emit a jump over the pool. |
| 1661 | CheckConstPool(true, no_const_pool_before_ == pc_offset() - kInstrSize); |
| 1662 | } |
| 1663 | } |
| 1664 | |
| 1665 | |
| 1666 | void Assembler::stm(BlockAddrMode am, |
| 1667 | Register base, |
| 1668 | RegList src, |
| 1669 | Condition cond) { |
| 1670 | addrmod4(cond | B27 | am, base, src); |
| 1671 | } |
| 1672 | |
| 1673 | |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 1674 | // Exception-generating instructions and debugging support. |
fschneider@chromium.org | e03fb64 | 2010-11-01 12:34:09 +0000 | [diff] [blame] | 1675 | // Stops with a non-negative code less than kNumOfWatchedStops support |
| 1676 | // enabling/disabling and a counter feature. See simulator-arm.h . |
| 1677 | void Assembler::stop(const char* msg, Condition cond, int32_t code) { |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 1678 | #ifndef __arm__ |
fschneider@chromium.org | e03fb64 | 2010-11-01 12:34:09 +0000 | [diff] [blame] | 1679 | ASSERT(code >= kDefaultStopCode); |
fschneider@chromium.org | e03fb64 | 2010-11-01 12:34:09 +0000 | [diff] [blame] | 1680 | // The Simulator will handle the stop instruction and get the message address. |
| 1681 | // It expects to find the address just after the svc instruction. |
| 1682 | BlockConstPoolFor(2); |
| 1683 | if (code >= 0) { |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1684 | svc(kStopCode + code, cond); |
fschneider@chromium.org | e03fb64 | 2010-11-01 12:34:09 +0000 | [diff] [blame] | 1685 | } else { |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1686 | svc(kStopCode + kMaxStopCode, cond); |
fschneider@chromium.org | e03fb64 | 2010-11-01 12:34:09 +0000 | [diff] [blame] | 1687 | } |
| 1688 | emit(reinterpret_cast<Instr>(msg)); |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 1689 | #else // def __arm__ |
| 1690 | #ifdef CAN_USE_ARMV5_INSTRUCTIONS |
vegorov@chromium.org | 0a4e901 | 2011-01-24 12:33:13 +0000 | [diff] [blame] | 1691 | if (cond != al) { |
| 1692 | Label skip; |
| 1693 | b(&skip, NegateCondition(cond)); |
| 1694 | bkpt(0); |
| 1695 | bind(&skip); |
| 1696 | } else { |
| 1697 | bkpt(0); |
| 1698 | } |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 1699 | #else // ndef CAN_USE_ARMV5_INSTRUCTIONS |
kasperl@chromium.org | a555126 | 2010-12-07 12:49:48 +0000 | [diff] [blame] | 1700 | svc(0x9f0001, cond); |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 1701 | #endif // ndef CAN_USE_ARMV5_INSTRUCTIONS |
| 1702 | #endif // def __arm__ |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1703 | } |
| 1704 | |
| 1705 | |
| 1706 | void Assembler::bkpt(uint32_t imm16) { // v5 and above |
| 1707 | ASSERT(is_uint16(imm16)); |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1708 | emit(al | B24 | B21 | (imm16 >> 4)*B8 | BKPT | (imm16 & 0xf)); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1709 | } |
| 1710 | |
| 1711 | |
fschneider@chromium.org | e03fb64 | 2010-11-01 12:34:09 +0000 | [diff] [blame] | 1712 | void Assembler::svc(uint32_t imm24, Condition cond) { |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1713 | ASSERT(is_uint24(imm24)); |
| 1714 | emit(cond | 15*B24 | imm24); |
| 1715 | } |
| 1716 | |
| 1717 | |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 1718 | // Coprocessor instructions. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1719 | void Assembler::cdp(Coprocessor coproc, |
| 1720 | int opcode_1, |
| 1721 | CRegister crd, |
| 1722 | CRegister crn, |
| 1723 | CRegister crm, |
| 1724 | int opcode_2, |
| 1725 | Condition cond) { |
| 1726 | ASSERT(is_uint4(opcode_1) && is_uint3(opcode_2)); |
| 1727 | emit(cond | B27 | B26 | B25 | (opcode_1 & 15)*B20 | crn.code()*B16 | |
| 1728 | crd.code()*B12 | coproc*B8 | (opcode_2 & 7)*B5 | crm.code()); |
| 1729 | } |
| 1730 | |
| 1731 | |
| 1732 | void Assembler::cdp2(Coprocessor coproc, |
| 1733 | int opcode_1, |
| 1734 | CRegister crd, |
| 1735 | CRegister crn, |
| 1736 | CRegister crm, |
| 1737 | int opcode_2) { // v5 and above |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1738 | cdp(coproc, opcode_1, crd, crn, crm, opcode_2, kSpecialCondition); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1739 | } |
| 1740 | |
| 1741 | |
| 1742 | void Assembler::mcr(Coprocessor coproc, |
| 1743 | int opcode_1, |
| 1744 | Register rd, |
| 1745 | CRegister crn, |
| 1746 | CRegister crm, |
| 1747 | int opcode_2, |
| 1748 | Condition cond) { |
| 1749 | ASSERT(is_uint3(opcode_1) && is_uint3(opcode_2)); |
| 1750 | emit(cond | B27 | B26 | B25 | (opcode_1 & 7)*B21 | crn.code()*B16 | |
| 1751 | rd.code()*B12 | coproc*B8 | (opcode_2 & 7)*B5 | B4 | crm.code()); |
| 1752 | } |
| 1753 | |
| 1754 | |
| 1755 | void Assembler::mcr2(Coprocessor coproc, |
| 1756 | int opcode_1, |
| 1757 | Register rd, |
| 1758 | CRegister crn, |
| 1759 | CRegister crm, |
| 1760 | int opcode_2) { // v5 and above |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1761 | mcr(coproc, opcode_1, rd, crn, crm, opcode_2, kSpecialCondition); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1762 | } |
| 1763 | |
| 1764 | |
| 1765 | void Assembler::mrc(Coprocessor coproc, |
| 1766 | int opcode_1, |
| 1767 | Register rd, |
| 1768 | CRegister crn, |
| 1769 | CRegister crm, |
| 1770 | int opcode_2, |
| 1771 | Condition cond) { |
| 1772 | ASSERT(is_uint3(opcode_1) && is_uint3(opcode_2)); |
| 1773 | emit(cond | B27 | B26 | B25 | (opcode_1 & 7)*B21 | L | crn.code()*B16 | |
| 1774 | rd.code()*B12 | coproc*B8 | (opcode_2 & 7)*B5 | B4 | crm.code()); |
| 1775 | } |
| 1776 | |
| 1777 | |
| 1778 | void Assembler::mrc2(Coprocessor coproc, |
| 1779 | int opcode_1, |
| 1780 | Register rd, |
| 1781 | CRegister crn, |
| 1782 | CRegister crm, |
| 1783 | int opcode_2) { // v5 and above |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1784 | mrc(coproc, opcode_1, rd, crn, crm, opcode_2, kSpecialCondition); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1785 | } |
| 1786 | |
| 1787 | |
| 1788 | void Assembler::ldc(Coprocessor coproc, |
| 1789 | CRegister crd, |
| 1790 | const MemOperand& src, |
| 1791 | LFlag l, |
| 1792 | Condition cond) { |
| 1793 | addrmod5(cond | B27 | B26 | l | L | coproc*B8, crd, src); |
| 1794 | } |
| 1795 | |
| 1796 | |
| 1797 | void Assembler::ldc(Coprocessor coproc, |
| 1798 | CRegister crd, |
| 1799 | Register rn, |
| 1800 | int option, |
| 1801 | LFlag l, |
| 1802 | Condition cond) { |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 1803 | // Unindexed addressing. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1804 | ASSERT(is_uint8(option)); |
| 1805 | emit(cond | B27 | B26 | U | l | L | rn.code()*B16 | crd.code()*B12 | |
| 1806 | coproc*B8 | (option & 255)); |
| 1807 | } |
| 1808 | |
| 1809 | |
| 1810 | void Assembler::ldc2(Coprocessor coproc, |
| 1811 | CRegister crd, |
| 1812 | const MemOperand& src, |
| 1813 | LFlag l) { // v5 and above |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1814 | ldc(coproc, crd, src, l, kSpecialCondition); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1815 | } |
| 1816 | |
| 1817 | |
| 1818 | void Assembler::ldc2(Coprocessor coproc, |
| 1819 | CRegister crd, |
| 1820 | Register rn, |
| 1821 | int option, |
| 1822 | LFlag l) { // v5 and above |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1823 | ldc(coproc, crd, rn, option, l, kSpecialCondition); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1824 | } |
| 1825 | |
| 1826 | |
| 1827 | void Assembler::stc(Coprocessor coproc, |
| 1828 | CRegister crd, |
| 1829 | const MemOperand& dst, |
| 1830 | LFlag l, |
| 1831 | Condition cond) { |
| 1832 | addrmod5(cond | B27 | B26 | l | coproc*B8, crd, dst); |
| 1833 | } |
| 1834 | |
| 1835 | |
| 1836 | void Assembler::stc(Coprocessor coproc, |
| 1837 | CRegister crd, |
| 1838 | Register rn, |
| 1839 | int option, |
| 1840 | LFlag l, |
| 1841 | Condition cond) { |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 1842 | // Unindexed addressing. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1843 | ASSERT(is_uint8(option)); |
| 1844 | emit(cond | B27 | B26 | U | l | rn.code()*B16 | crd.code()*B12 | |
| 1845 | coproc*B8 | (option & 255)); |
| 1846 | } |
| 1847 | |
| 1848 | |
| 1849 | void Assembler::stc2(Coprocessor |
| 1850 | coproc, CRegister crd, |
| 1851 | const MemOperand& dst, |
| 1852 | LFlag l) { // v5 and above |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1853 | stc(coproc, crd, dst, l, kSpecialCondition); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1854 | } |
| 1855 | |
| 1856 | |
| 1857 | void Assembler::stc2(Coprocessor coproc, |
| 1858 | CRegister crd, |
| 1859 | Register rn, |
| 1860 | int option, |
| 1861 | LFlag l) { // v5 and above |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 1862 | stc(coproc, crd, rn, option, l, kSpecialCondition); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 1863 | } |
| 1864 | |
| 1865 | |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 1866 | // Support for VFP. |
ricow@chromium.org | d236f4d | 2010-09-01 06:52:08 +0000 | [diff] [blame] | 1867 | |
sgjesse@chromium.org | b302e56 | 2010-02-03 11:26:59 +0000 | [diff] [blame] | 1868 | void Assembler::vldr(const DwVfpRegister dst, |
| 1869 | const Register base, |
| 1870 | int offset, |
| 1871 | const Condition cond) { |
| 1872 | // Ddst = MEM(Rbase + offset). |
| 1873 | // Instruction details available in ARM DDI 0406A, A8-628. |
kasperl@chromium.org | a555126 | 2010-12-07 12:49:48 +0000 | [diff] [blame] | 1874 | // cond(31-28) | 1101(27-24)| U001(23-20) | Rbase(19-16) | |
sgjesse@chromium.org | b302e56 | 2010-02-03 11:26:59 +0000 | [diff] [blame] | 1875 | // Vdst(15-12) | 1011(11-8) | offset |
kmillikin@chromium.org | c36ce6e | 2011-04-04 08:25:31 +0000 | [diff] [blame] | 1876 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
kasperl@chromium.org | a555126 | 2010-12-07 12:49:48 +0000 | [diff] [blame] | 1877 | int u = 1; |
| 1878 | if (offset < 0) { |
| 1879 | offset = -offset; |
| 1880 | u = 0; |
| 1881 | } |
fschneider@chromium.org | 3a5fd78 | 2011-02-24 10:10:44 +0000 | [diff] [blame] | 1882 | |
ricow@chromium.org | 0b9f850 | 2010-08-18 07:45:01 +0000 | [diff] [blame] | 1883 | ASSERT(offset >= 0); |
fschneider@chromium.org | 3a5fd78 | 2011-02-24 10:10:44 +0000 | [diff] [blame] | 1884 | if ((offset % 4) == 0 && (offset / 4) < 256) { |
| 1885 | emit(cond | u*B23 | 0xD1*B20 | base.code()*B16 | dst.code()*B12 | |
| 1886 | 0xB*B8 | ((offset / 4) & 255)); |
| 1887 | } else { |
| 1888 | // Larger offsets must be handled by computing the correct address |
| 1889 | // in the ip register. |
| 1890 | ASSERT(!base.is(ip)); |
| 1891 | if (u == 1) { |
| 1892 | add(ip, base, Operand(offset)); |
| 1893 | } else { |
| 1894 | sub(ip, base, Operand(offset)); |
| 1895 | } |
| 1896 | emit(cond | 0xD1*B20 | ip.code()*B16 | dst.code()*B12 | 0xB*B8); |
| 1897 | } |
| 1898 | } |
| 1899 | |
| 1900 | |
| 1901 | void Assembler::vldr(const DwVfpRegister dst, |
| 1902 | const MemOperand& operand, |
| 1903 | const Condition cond) { |
| 1904 | ASSERT(!operand.rm().is_valid()); |
| 1905 | ASSERT(operand.am_ == Offset); |
| 1906 | vldr(dst, operand.rn(), operand.offset(), cond); |
sgjesse@chromium.org | b302e56 | 2010-02-03 11:26:59 +0000 | [diff] [blame] | 1907 | } |
| 1908 | |
| 1909 | |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 1910 | void Assembler::vldr(const SwVfpRegister dst, |
| 1911 | const Register base, |
| 1912 | int offset, |
| 1913 | const Condition cond) { |
| 1914 | // Sdst = MEM(Rbase + offset). |
| 1915 | // Instruction details available in ARM DDI 0406A, A8-628. |
kasperl@chromium.org | a555126 | 2010-12-07 12:49:48 +0000 | [diff] [blame] | 1916 | // cond(31-28) | 1101(27-24)| U001(23-20) | Rbase(19-16) | |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 1917 | // Vdst(15-12) | 1010(11-8) | offset |
kmillikin@chromium.org | c36ce6e | 2011-04-04 08:25:31 +0000 | [diff] [blame] | 1918 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
kasperl@chromium.org | a555126 | 2010-12-07 12:49:48 +0000 | [diff] [blame] | 1919 | int u = 1; |
| 1920 | if (offset < 0) { |
| 1921 | offset = -offset; |
| 1922 | u = 0; |
| 1923 | } |
ricow@chromium.org | d236f4d | 2010-09-01 06:52:08 +0000 | [diff] [blame] | 1924 | int sd, d; |
| 1925 | dst.split_code(&sd, &d); |
fschneider@chromium.org | 3a5fd78 | 2011-02-24 10:10:44 +0000 | [diff] [blame] | 1926 | ASSERT(offset >= 0); |
| 1927 | |
| 1928 | if ((offset % 4) == 0 && (offset / 4) < 256) { |
kasperl@chromium.org | a555126 | 2010-12-07 12:49:48 +0000 | [diff] [blame] | 1929 | emit(cond | u*B23 | d*B22 | 0xD1*B20 | base.code()*B16 | sd*B12 | |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 1930 | 0xA*B8 | ((offset / 4) & 255)); |
fschneider@chromium.org | 3a5fd78 | 2011-02-24 10:10:44 +0000 | [diff] [blame] | 1931 | } else { |
| 1932 | // Larger offsets must be handled by computing the correct address |
| 1933 | // in the ip register. |
| 1934 | ASSERT(!base.is(ip)); |
| 1935 | if (u == 1) { |
| 1936 | add(ip, base, Operand(offset)); |
| 1937 | } else { |
| 1938 | sub(ip, base, Operand(offset)); |
| 1939 | } |
| 1940 | emit(cond | d*B22 | 0xD1*B20 | ip.code()*B16 | sd*B12 | 0xA*B8); |
| 1941 | } |
| 1942 | } |
| 1943 | |
| 1944 | |
| 1945 | void Assembler::vldr(const SwVfpRegister dst, |
| 1946 | const MemOperand& operand, |
| 1947 | const Condition cond) { |
| 1948 | ASSERT(!operand.rm().is_valid()); |
| 1949 | ASSERT(operand.am_ == Offset); |
| 1950 | vldr(dst, operand.rn(), operand.offset(), cond); |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 1951 | } |
| 1952 | |
| 1953 | |
sgjesse@chromium.org | b302e56 | 2010-02-03 11:26:59 +0000 | [diff] [blame] | 1954 | void Assembler::vstr(const DwVfpRegister src, |
| 1955 | const Register base, |
| 1956 | int offset, |
| 1957 | const Condition cond) { |
| 1958 | // MEM(Rbase + offset) = Dsrc. |
| 1959 | // Instruction details available in ARM DDI 0406A, A8-786. |
kasperl@chromium.org | a555126 | 2010-12-07 12:49:48 +0000 | [diff] [blame] | 1960 | // cond(31-28) | 1101(27-24)| U000(23-20) | | Rbase(19-16) | |
sgjesse@chromium.org | b302e56 | 2010-02-03 11:26:59 +0000 | [diff] [blame] | 1961 | // Vsrc(15-12) | 1011(11-8) | (offset/4) |
kmillikin@chromium.org | c36ce6e | 2011-04-04 08:25:31 +0000 | [diff] [blame] | 1962 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
kasperl@chromium.org | a555126 | 2010-12-07 12:49:48 +0000 | [diff] [blame] | 1963 | int u = 1; |
| 1964 | if (offset < 0) { |
| 1965 | offset = -offset; |
| 1966 | u = 0; |
| 1967 | } |
ricow@chromium.org | 0b9f850 | 2010-08-18 07:45:01 +0000 | [diff] [blame] | 1968 | ASSERT(offset >= 0); |
fschneider@chromium.org | 3a5fd78 | 2011-02-24 10:10:44 +0000 | [diff] [blame] | 1969 | if ((offset % 4) == 0 && (offset / 4) < 256) { |
| 1970 | emit(cond | u*B23 | 0xD0*B20 | base.code()*B16 | src.code()*B12 | |
| 1971 | 0xB*B8 | ((offset / 4) & 255)); |
| 1972 | } else { |
| 1973 | // Larger offsets must be handled by computing the correct address |
| 1974 | // in the ip register. |
| 1975 | ASSERT(!base.is(ip)); |
| 1976 | if (u == 1) { |
| 1977 | add(ip, base, Operand(offset)); |
| 1978 | } else { |
| 1979 | sub(ip, base, Operand(offset)); |
| 1980 | } |
| 1981 | emit(cond | 0xD0*B20 | ip.code()*B16 | src.code()*B12 | 0xB*B8); |
| 1982 | } |
| 1983 | } |
| 1984 | |
| 1985 | |
| 1986 | void Assembler::vstr(const DwVfpRegister src, |
| 1987 | const MemOperand& operand, |
| 1988 | const Condition cond) { |
| 1989 | ASSERT(!operand.rm().is_valid()); |
| 1990 | ASSERT(operand.am_ == Offset); |
| 1991 | vstr(src, operand.rn(), operand.offset(), cond); |
sgjesse@chromium.org | b302e56 | 2010-02-03 11:26:59 +0000 | [diff] [blame] | 1992 | } |
| 1993 | |
| 1994 | |
ricow@chromium.org | 0b9f850 | 2010-08-18 07:45:01 +0000 | [diff] [blame] | 1995 | void Assembler::vstr(const SwVfpRegister src, |
| 1996 | const Register base, |
| 1997 | int offset, |
| 1998 | const Condition cond) { |
| 1999 | // MEM(Rbase + offset) = SSrc. |
| 2000 | // Instruction details available in ARM DDI 0406A, A8-786. |
kasperl@chromium.org | a555126 | 2010-12-07 12:49:48 +0000 | [diff] [blame] | 2001 | // cond(31-28) | 1101(27-24)| U000(23-20) | Rbase(19-16) | |
ricow@chromium.org | 0b9f850 | 2010-08-18 07:45:01 +0000 | [diff] [blame] | 2002 | // Vdst(15-12) | 1010(11-8) | (offset/4) |
kmillikin@chromium.org | c36ce6e | 2011-04-04 08:25:31 +0000 | [diff] [blame] | 2003 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
kasperl@chromium.org | a555126 | 2010-12-07 12:49:48 +0000 | [diff] [blame] | 2004 | int u = 1; |
| 2005 | if (offset < 0) { |
| 2006 | offset = -offset; |
| 2007 | u = 0; |
| 2008 | } |
ricow@chromium.org | d236f4d | 2010-09-01 06:52:08 +0000 | [diff] [blame] | 2009 | int sd, d; |
| 2010 | src.split_code(&sd, &d); |
fschneider@chromium.org | 3a5fd78 | 2011-02-24 10:10:44 +0000 | [diff] [blame] | 2011 | ASSERT(offset >= 0); |
| 2012 | if ((offset % 4) == 0 && (offset / 4) < 256) { |
| 2013 | emit(cond | u*B23 | d*B22 | 0xD0*B20 | base.code()*B16 | sd*B12 | |
| 2014 | 0xA*B8 | ((offset / 4) & 255)); |
| 2015 | } else { |
| 2016 | // Larger offsets must be handled by computing the correct address |
| 2017 | // in the ip register. |
| 2018 | ASSERT(!base.is(ip)); |
| 2019 | if (u == 1) { |
| 2020 | add(ip, base, Operand(offset)); |
| 2021 | } else { |
| 2022 | sub(ip, base, Operand(offset)); |
| 2023 | } |
| 2024 | emit(cond | d*B22 | 0xD0*B20 | ip.code()*B16 | sd*B12 | 0xA*B8); |
| 2025 | } |
| 2026 | } |
| 2027 | |
| 2028 | |
| 2029 | void Assembler::vstr(const SwVfpRegister src, |
| 2030 | const MemOperand& operand, |
| 2031 | const Condition cond) { |
| 2032 | ASSERT(!operand.rm().is_valid()); |
| 2033 | ASSERT(operand.am_ == Offset); |
| 2034 | vldr(src, operand.rn(), operand.offset(), cond); |
ricow@chromium.org | 0b9f850 | 2010-08-18 07:45:01 +0000 | [diff] [blame] | 2035 | } |
| 2036 | |
| 2037 | |
vegorov@chromium.org | 74f333b | 2011-04-06 11:17:46 +0000 | [diff] [blame^] | 2038 | void Assembler::vldm(BlockAddrMode am, |
| 2039 | Register base, |
| 2040 | DwVfpRegister first, |
| 2041 | DwVfpRegister last, |
| 2042 | Condition cond) { |
| 2043 | // Instruction details available in ARM DDI 0406A, A8-626. |
| 2044 | // cond(31-28) | 110(27-25)| PUDW1(24-20) | Rbase(19-16) | |
| 2045 | // first(15-12) | 1010(11-8) | (count * 2) |
| 2046 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
| 2047 | ASSERT_LE(first.code(), last.code()); |
| 2048 | ASSERT(am == ia || am == ia_w || am == db_w); |
| 2049 | ASSERT(!base.is(pc)); |
| 2050 | |
| 2051 | int sd, d; |
| 2052 | first.split_code(&sd, &d); |
| 2053 | int count = last.code() - first.code() + 1; |
| 2054 | emit(cond | B27 | B26 | am | d*B22 | B20 | base.code()*B16 | sd*B12 | |
| 2055 | 0xB*B8 | count*2); |
| 2056 | } |
| 2057 | |
| 2058 | |
| 2059 | void Assembler::vstm(BlockAddrMode am, |
| 2060 | Register base, |
| 2061 | DwVfpRegister first, |
| 2062 | DwVfpRegister last, |
| 2063 | Condition cond) { |
| 2064 | // Instruction details available in ARM DDI 0406A, A8-784. |
| 2065 | // cond(31-28) | 110(27-25)| PUDW0(24-20) | Rbase(19-16) | |
| 2066 | // first(15-12) | 1011(11-8) | (count * 2) |
| 2067 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
| 2068 | ASSERT_LE(first.code(), last.code()); |
| 2069 | ASSERT(am == ia || am == ia_w || am == db_w); |
| 2070 | ASSERT(!base.is(pc)); |
| 2071 | |
| 2072 | int sd, d; |
| 2073 | first.split_code(&sd, &d); |
| 2074 | int count = last.code() - first.code() + 1; |
| 2075 | emit(cond | B27 | B26 | am | d*B22 | base.code()*B16 | sd*B12 | |
| 2076 | 0xB*B8 | count*2); |
| 2077 | } |
| 2078 | |
| 2079 | void Assembler::vldm(BlockAddrMode am, |
| 2080 | Register base, |
| 2081 | SwVfpRegister first, |
| 2082 | SwVfpRegister last, |
| 2083 | Condition cond) { |
| 2084 | // Instruction details available in ARM DDI 0406A, A8-626. |
| 2085 | // cond(31-28) | 110(27-25)| PUDW1(24-20) | Rbase(19-16) | |
| 2086 | // first(15-12) | 1010(11-8) | (count/2) |
| 2087 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
| 2088 | ASSERT_LE(first.code(), last.code()); |
| 2089 | ASSERT(am == ia || am == ia_w || am == db_w); |
| 2090 | ASSERT(!base.is(pc)); |
| 2091 | |
| 2092 | int sd, d; |
| 2093 | first.split_code(&sd, &d); |
| 2094 | int count = last.code() - first.code() + 1; |
| 2095 | emit(cond | B27 | B26 | am | d*B22 | B20 | base.code()*B16 | sd*B12 | |
| 2096 | 0xA*B8 | count); |
| 2097 | } |
| 2098 | |
| 2099 | |
| 2100 | void Assembler::vstm(BlockAddrMode am, |
| 2101 | Register base, |
| 2102 | SwVfpRegister first, |
| 2103 | SwVfpRegister last, |
| 2104 | Condition cond) { |
| 2105 | // Instruction details available in ARM DDI 0406A, A8-784. |
| 2106 | // cond(31-28) | 110(27-25)| PUDW0(24-20) | Rbase(19-16) | |
| 2107 | // first(15-12) | 1011(11-8) | (count/2) |
| 2108 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
| 2109 | ASSERT_LE(first.code(), last.code()); |
| 2110 | ASSERT(am == ia || am == ia_w || am == db_w); |
| 2111 | ASSERT(!base.is(pc)); |
| 2112 | |
| 2113 | int sd, d; |
| 2114 | first.split_code(&sd, &d); |
| 2115 | int count = last.code() - first.code() + 1; |
| 2116 | emit(cond | B27 | B26 | am | d*B22 | base.code()*B16 | sd*B12 | |
| 2117 | 0xA*B8 | count); |
| 2118 | } |
| 2119 | |
ager@chromium.org | 6a2b0aa | 2010-07-13 20:58:03 +0000 | [diff] [blame] | 2120 | static void DoubleAsTwoUInt32(double d, uint32_t* lo, uint32_t* hi) { |
| 2121 | uint64_t i; |
| 2122 | memcpy(&i, &d, 8); |
| 2123 | |
| 2124 | *lo = i & 0xffffffff; |
| 2125 | *hi = i >> 32; |
| 2126 | } |
| 2127 | |
| 2128 | // Only works for little endian floating point formats. |
| 2129 | // We don't support VFP on the mixed endian floating point platform. |
| 2130 | static bool FitsVMOVDoubleImmediate(double d, uint32_t *encoding) { |
kmillikin@chromium.org | c36ce6e | 2011-04-04 08:25:31 +0000 | [diff] [blame] | 2131 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
ager@chromium.org | 6a2b0aa | 2010-07-13 20:58:03 +0000 | [diff] [blame] | 2132 | |
| 2133 | // VMOV can accept an immediate of the form: |
| 2134 | // |
| 2135 | // +/- m * 2^(-n) where 16 <= m <= 31 and 0 <= n <= 7 |
| 2136 | // |
| 2137 | // The immediate is encoded using an 8-bit quantity, comprised of two |
| 2138 | // 4-bit fields. For an 8-bit immediate of the form: |
| 2139 | // |
| 2140 | // [abcdefgh] |
| 2141 | // |
| 2142 | // where a is the MSB and h is the LSB, an immediate 64-bit double can be |
| 2143 | // created of the form: |
| 2144 | // |
| 2145 | // [aBbbbbbb,bbcdefgh,00000000,00000000, |
| 2146 | // 00000000,00000000,00000000,00000000] |
| 2147 | // |
| 2148 | // where B = ~b. |
| 2149 | // |
| 2150 | |
| 2151 | uint32_t lo, hi; |
| 2152 | DoubleAsTwoUInt32(d, &lo, &hi); |
| 2153 | |
| 2154 | // The most obvious constraint is the long block of zeroes. |
| 2155 | if ((lo != 0) || ((hi & 0xffff) != 0)) { |
| 2156 | return false; |
| 2157 | } |
| 2158 | |
| 2159 | // Bits 62:55 must be all clear or all set. |
| 2160 | if (((hi & 0x3fc00000) != 0) && ((hi & 0x3fc00000) != 0x3fc00000)) { |
| 2161 | return false; |
| 2162 | } |
| 2163 | |
| 2164 | // Bit 63 must be NOT bit 62. |
| 2165 | if (((hi ^ (hi << 1)) & (0x40000000)) == 0) { |
| 2166 | return false; |
| 2167 | } |
| 2168 | |
| 2169 | // Create the encoded immediate in the form: |
| 2170 | // [00000000,0000abcd,00000000,0000efgh] |
| 2171 | *encoding = (hi >> 16) & 0xf; // Low nybble. |
| 2172 | *encoding |= (hi >> 4) & 0x70000; // Low three bits of the high nybble. |
| 2173 | *encoding |= (hi >> 12) & 0x80000; // Top bit of the high nybble. |
| 2174 | |
| 2175 | return true; |
| 2176 | } |
| 2177 | |
| 2178 | |
| 2179 | void Assembler::vmov(const DwVfpRegister dst, |
| 2180 | double imm, |
| 2181 | const Condition cond) { |
| 2182 | // Dd = immediate |
| 2183 | // Instruction details available in ARM DDI 0406B, A8-640. |
kmillikin@chromium.org | c36ce6e | 2011-04-04 08:25:31 +0000 | [diff] [blame] | 2184 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
ager@chromium.org | 6a2b0aa | 2010-07-13 20:58:03 +0000 | [diff] [blame] | 2185 | |
| 2186 | uint32_t enc; |
| 2187 | if (FitsVMOVDoubleImmediate(imm, &enc)) { |
| 2188 | // The double can be encoded in the instruction. |
| 2189 | emit(cond | 0xE*B24 | 0xB*B20 | dst.code()*B12 | 0xB*B8 | enc); |
| 2190 | } else { |
| 2191 | // Synthesise the double from ARM immediates. This could be implemented |
| 2192 | // using vldr from a constant pool. |
| 2193 | uint32_t lo, hi; |
| 2194 | DoubleAsTwoUInt32(imm, &lo, &hi); |
| 2195 | |
| 2196 | if (lo == hi) { |
| 2197 | // If the lo and hi parts of the double are equal, the literal is easier |
| 2198 | // to create. This is the case with 0.0. |
| 2199 | mov(ip, Operand(lo)); |
| 2200 | vmov(dst, ip, ip); |
| 2201 | } else { |
| 2202 | // Move the low part of the double into the lower of the corresponsing S |
| 2203 | // registers of D register dst. |
| 2204 | mov(ip, Operand(lo)); |
| 2205 | vmov(dst.low(), ip, cond); |
| 2206 | |
| 2207 | // Move the high part of the double into the higher of the corresponsing S |
| 2208 | // registers of D register dst. |
| 2209 | mov(ip, Operand(hi)); |
| 2210 | vmov(dst.high(), ip, cond); |
| 2211 | } |
| 2212 | } |
| 2213 | } |
| 2214 | |
| 2215 | |
| 2216 | void Assembler::vmov(const SwVfpRegister dst, |
| 2217 | const SwVfpRegister src, |
| 2218 | const Condition cond) { |
| 2219 | // Sd = Sm |
| 2220 | // Instruction details available in ARM DDI 0406B, A8-642. |
kmillikin@chromium.org | c36ce6e | 2011-04-04 08:25:31 +0000 | [diff] [blame] | 2221 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
ricow@chromium.org | d236f4d | 2010-09-01 06:52:08 +0000 | [diff] [blame] | 2222 | int sd, d, sm, m; |
| 2223 | dst.split_code(&sd, &d); |
| 2224 | src.split_code(&sm, &m); |
| 2225 | emit(cond | 0xE*B24 | d*B22 | 0xB*B20 | sd*B12 | 0xA*B8 | B6 | m*B5 | sm); |
ager@chromium.org | 6a2b0aa | 2010-07-13 20:58:03 +0000 | [diff] [blame] | 2226 | } |
| 2227 | |
| 2228 | |
kmillikin@chromium.org | 13bd294 | 2009-12-16 15:36:05 +0000 | [diff] [blame] | 2229 | void Assembler::vmov(const DwVfpRegister dst, |
kmillikin@chromium.org | 69ea396 | 2010-07-05 11:01:40 +0000 | [diff] [blame] | 2230 | const DwVfpRegister src, |
| 2231 | const Condition cond) { |
| 2232 | // Dd = Dm |
| 2233 | // Instruction details available in ARM DDI 0406B, A8-642. |
kmillikin@chromium.org | c36ce6e | 2011-04-04 08:25:31 +0000 | [diff] [blame] | 2234 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
kmillikin@chromium.org | 69ea396 | 2010-07-05 11:01:40 +0000 | [diff] [blame] | 2235 | emit(cond | 0xE*B24 | 0xB*B20 | |
| 2236 | dst.code()*B12 | 0x5*B9 | B8 | B6 | src.code()); |
| 2237 | } |
| 2238 | |
| 2239 | |
| 2240 | void Assembler::vmov(const DwVfpRegister dst, |
kmillikin@chromium.org | 13bd294 | 2009-12-16 15:36:05 +0000 | [diff] [blame] | 2241 | const Register src1, |
| 2242 | const Register src2, |
| 2243 | const Condition cond) { |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2244 | // Dm = <Rt,Rt2>. |
| 2245 | // Instruction details available in ARM DDI 0406A, A8-646. |
| 2246 | // cond(31-28) | 1100(27-24)| 010(23-21) | op=0(20) | Rt2(19-16) | |
| 2247 | // Rt(15-12) | 1011(11-8) | 00(7-6) | M(5) | 1(4) | Vm |
kmillikin@chromium.org | c36ce6e | 2011-04-04 08:25:31 +0000 | [diff] [blame] | 2248 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2249 | ASSERT(!src1.is(pc) && !src2.is(pc)); |
| 2250 | emit(cond | 0xC*B24 | B22 | src2.code()*B16 | |
| 2251 | src1.code()*B12 | 0xB*B8 | B4 | dst.code()); |
| 2252 | } |
| 2253 | |
| 2254 | |
kmillikin@chromium.org | 13bd294 | 2009-12-16 15:36:05 +0000 | [diff] [blame] | 2255 | void Assembler::vmov(const Register dst1, |
| 2256 | const Register dst2, |
| 2257 | const DwVfpRegister src, |
| 2258 | const Condition cond) { |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2259 | // <Rt,Rt2> = Dm. |
| 2260 | // Instruction details available in ARM DDI 0406A, A8-646. |
| 2261 | // cond(31-28) | 1100(27-24)| 010(23-21) | op=1(20) | Rt2(19-16) | |
| 2262 | // Rt(15-12) | 1011(11-8) | 00(7-6) | M(5) | 1(4) | Vm |
kmillikin@chromium.org | c36ce6e | 2011-04-04 08:25:31 +0000 | [diff] [blame] | 2263 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2264 | ASSERT(!dst1.is(pc) && !dst2.is(pc)); |
| 2265 | emit(cond | 0xC*B24 | B22 | B20 | dst2.code()*B16 | |
| 2266 | dst1.code()*B12 | 0xB*B8 | B4 | src.code()); |
| 2267 | } |
| 2268 | |
| 2269 | |
kmillikin@chromium.org | 13bd294 | 2009-12-16 15:36:05 +0000 | [diff] [blame] | 2270 | void Assembler::vmov(const SwVfpRegister dst, |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2271 | const Register src, |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2272 | const Condition cond) { |
| 2273 | // Sn = Rt. |
| 2274 | // Instruction details available in ARM DDI 0406A, A8-642. |
| 2275 | // cond(31-28) | 1110(27-24)| 000(23-21) | op=0(20) | Vn(19-16) | |
| 2276 | // Rt(15-12) | 1010(11-8) | N(7)=0 | 00(6-5) | 1(4) | 0000(3-0) |
kmillikin@chromium.org | c36ce6e | 2011-04-04 08:25:31 +0000 | [diff] [blame] | 2277 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2278 | ASSERT(!src.is(pc)); |
ricow@chromium.org | d236f4d | 2010-09-01 06:52:08 +0000 | [diff] [blame] | 2279 | int sn, n; |
| 2280 | dst.split_code(&sn, &n); |
| 2281 | emit(cond | 0xE*B24 | sn*B16 | src.code()*B12 | 0xA*B8 | n*B7 | B4); |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2282 | } |
| 2283 | |
| 2284 | |
kmillikin@chromium.org | 13bd294 | 2009-12-16 15:36:05 +0000 | [diff] [blame] | 2285 | void Assembler::vmov(const Register dst, |
| 2286 | const SwVfpRegister src, |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2287 | const Condition cond) { |
| 2288 | // Rt = Sn. |
| 2289 | // Instruction details available in ARM DDI 0406A, A8-642. |
| 2290 | // cond(31-28) | 1110(27-24)| 000(23-21) | op=1(20) | Vn(19-16) | |
| 2291 | // Rt(15-12) | 1010(11-8) | N(7)=0 | 00(6-5) | 1(4) | 0000(3-0) |
kmillikin@chromium.org | c36ce6e | 2011-04-04 08:25:31 +0000 | [diff] [blame] | 2292 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2293 | ASSERT(!dst.is(pc)); |
ricow@chromium.org | d236f4d | 2010-09-01 06:52:08 +0000 | [diff] [blame] | 2294 | int sn, n; |
| 2295 | src.split_code(&sn, &n); |
| 2296 | emit(cond | 0xE*B24 | B20 | sn*B16 | dst.code()*B12 | 0xA*B8 | n*B7 | B4); |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2297 | } |
| 2298 | |
| 2299 | |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 2300 | // Type of data to read from or write to VFP register. |
| 2301 | // Used as specifier in generic vcvt instruction. |
| 2302 | enum VFPType { S32, U32, F32, F64 }; |
| 2303 | |
| 2304 | |
| 2305 | static bool IsSignedVFPType(VFPType type) { |
| 2306 | switch (type) { |
| 2307 | case S32: |
| 2308 | return true; |
| 2309 | case U32: |
| 2310 | return false; |
| 2311 | default: |
| 2312 | UNREACHABLE(); |
| 2313 | return false; |
| 2314 | } |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2315 | } |
| 2316 | |
| 2317 | |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 2318 | static bool IsIntegerVFPType(VFPType type) { |
| 2319 | switch (type) { |
| 2320 | case S32: |
| 2321 | case U32: |
| 2322 | return true; |
| 2323 | case F32: |
| 2324 | case F64: |
| 2325 | return false; |
| 2326 | default: |
| 2327 | UNREACHABLE(); |
| 2328 | return false; |
| 2329 | } |
| 2330 | } |
| 2331 | |
| 2332 | |
| 2333 | static bool IsDoubleVFPType(VFPType type) { |
| 2334 | switch (type) { |
| 2335 | case F32: |
| 2336 | return false; |
| 2337 | case F64: |
| 2338 | return true; |
| 2339 | default: |
| 2340 | UNREACHABLE(); |
| 2341 | return false; |
| 2342 | } |
| 2343 | } |
| 2344 | |
| 2345 | |
ricow@chromium.org | d236f4d | 2010-09-01 06:52:08 +0000 | [diff] [blame] | 2346 | // Split five bit reg_code based on size of reg_type. |
| 2347 | // 32-bit register codes are Vm:M |
| 2348 | // 64-bit register codes are M:Vm |
| 2349 | // where Vm is four bits, and M is a single bit. |
| 2350 | static void SplitRegCode(VFPType reg_type, |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 2351 | int reg_code, |
| 2352 | int* vm, |
| 2353 | int* m) { |
ricow@chromium.org | d236f4d | 2010-09-01 06:52:08 +0000 | [diff] [blame] | 2354 | ASSERT((reg_code >= 0) && (reg_code <= 31)); |
| 2355 | if (IsIntegerVFPType(reg_type) || !IsDoubleVFPType(reg_type)) { |
| 2356 | // 32 bit type. |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 2357 | *m = reg_code & 0x1; |
| 2358 | *vm = reg_code >> 1; |
| 2359 | } else { |
ricow@chromium.org | d236f4d | 2010-09-01 06:52:08 +0000 | [diff] [blame] | 2360 | // 64 bit type. |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 2361 | *m = (reg_code & 0x10) >> 4; |
| 2362 | *vm = reg_code & 0x0F; |
| 2363 | } |
| 2364 | } |
| 2365 | |
| 2366 | |
| 2367 | // Encode vcvt.src_type.dst_type instruction. |
| 2368 | static Instr EncodeVCVT(const VFPType dst_type, |
| 2369 | const int dst_code, |
| 2370 | const VFPType src_type, |
| 2371 | const int src_code, |
ricow@chromium.org | 83aa549 | 2011-02-07 12:42:56 +0000 | [diff] [blame] | 2372 | VFPConversionMode mode, |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 2373 | const Condition cond) { |
ricow@chromium.org | d236f4d | 2010-09-01 06:52:08 +0000 | [diff] [blame] | 2374 | ASSERT(src_type != dst_type); |
| 2375 | int D, Vd, M, Vm; |
| 2376 | SplitRegCode(src_type, src_code, &Vm, &M); |
| 2377 | SplitRegCode(dst_type, dst_code, &Vd, &D); |
| 2378 | |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 2379 | if (IsIntegerVFPType(dst_type) || IsIntegerVFPType(src_type)) { |
| 2380 | // Conversion between IEEE floating point and 32-bit integer. |
| 2381 | // Instruction details available in ARM DDI 0406B, A8.6.295. |
| 2382 | // cond(31-28) | 11101(27-23)| D(22) | 11(21-20) | 1(19) | opc2(18-16) | |
| 2383 | // Vd(15-12) | 101(11-9) | sz(8) | op(7) | 1(6) | M(5) | 0(4) | Vm(3-0) |
| 2384 | ASSERT(!IsIntegerVFPType(dst_type) || !IsIntegerVFPType(src_type)); |
| 2385 | |
ricow@chromium.org | d236f4d | 2010-09-01 06:52:08 +0000 | [diff] [blame] | 2386 | int sz, opc2, op; |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 2387 | |
| 2388 | if (IsIntegerVFPType(dst_type)) { |
| 2389 | opc2 = IsSignedVFPType(dst_type) ? 0x5 : 0x4; |
| 2390 | sz = IsDoubleVFPType(src_type) ? 0x1 : 0x0; |
ager@chromium.org | 01fe7df | 2010-11-10 11:59:11 +0000 | [diff] [blame] | 2391 | op = mode; |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 2392 | } else { |
| 2393 | ASSERT(IsIntegerVFPType(src_type)); |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 2394 | opc2 = 0x0; |
| 2395 | sz = IsDoubleVFPType(dst_type) ? 0x1 : 0x0; |
| 2396 | op = IsSignedVFPType(src_type) ? 0x1 : 0x0; |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 2397 | } |
| 2398 | |
| 2399 | return (cond | 0xE*B24 | B23 | D*B22 | 0x3*B20 | B19 | opc2*B16 | |
| 2400 | Vd*B12 | 0x5*B9 | sz*B8 | op*B7 | B6 | M*B5 | Vm); |
| 2401 | } else { |
| 2402 | // Conversion between IEEE double and single precision. |
| 2403 | // Instruction details available in ARM DDI 0406B, A8.6.298. |
| 2404 | // cond(31-28) | 11101(27-23)| D(22) | 11(21-20) | 0111(19-16) | |
| 2405 | // Vd(15-12) | 101(11-9) | sz(8) | 1(7) | 1(6) | M(5) | 0(4) | Vm(3-0) |
ricow@chromium.org | d236f4d | 2010-09-01 06:52:08 +0000 | [diff] [blame] | 2406 | int sz = IsDoubleVFPType(src_type) ? 0x1 : 0x0; |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 2407 | return (cond | 0xE*B24 | B23 | D*B22 | 0x3*B20 | 0x7*B16 | |
| 2408 | Vd*B12 | 0x5*B9 | sz*B8 | B7 | B6 | M*B5 | Vm); |
| 2409 | } |
| 2410 | } |
| 2411 | |
| 2412 | |
| 2413 | void Assembler::vcvt_f64_s32(const DwVfpRegister dst, |
| 2414 | const SwVfpRegister src, |
ricow@chromium.org | 83aa549 | 2011-02-07 12:42:56 +0000 | [diff] [blame] | 2415 | VFPConversionMode mode, |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 2416 | const Condition cond) { |
kmillikin@chromium.org | c36ce6e | 2011-04-04 08:25:31 +0000 | [diff] [blame] | 2417 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
ager@chromium.org | 01fe7df | 2010-11-10 11:59:11 +0000 | [diff] [blame] | 2418 | emit(EncodeVCVT(F64, dst.code(), S32, src.code(), mode, cond)); |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 2419 | } |
| 2420 | |
| 2421 | |
| 2422 | void Assembler::vcvt_f32_s32(const SwVfpRegister dst, |
| 2423 | const SwVfpRegister src, |
ricow@chromium.org | 83aa549 | 2011-02-07 12:42:56 +0000 | [diff] [blame] | 2424 | VFPConversionMode mode, |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 2425 | const Condition cond) { |
kmillikin@chromium.org | c36ce6e | 2011-04-04 08:25:31 +0000 | [diff] [blame] | 2426 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
ager@chromium.org | 01fe7df | 2010-11-10 11:59:11 +0000 | [diff] [blame] | 2427 | emit(EncodeVCVT(F32, dst.code(), S32, src.code(), mode, cond)); |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 2428 | } |
| 2429 | |
| 2430 | |
| 2431 | void Assembler::vcvt_f64_u32(const DwVfpRegister dst, |
| 2432 | const SwVfpRegister src, |
ricow@chromium.org | 83aa549 | 2011-02-07 12:42:56 +0000 | [diff] [blame] | 2433 | VFPConversionMode mode, |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 2434 | const Condition cond) { |
kmillikin@chromium.org | c36ce6e | 2011-04-04 08:25:31 +0000 | [diff] [blame] | 2435 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
ager@chromium.org | 01fe7df | 2010-11-10 11:59:11 +0000 | [diff] [blame] | 2436 | emit(EncodeVCVT(F64, dst.code(), U32, src.code(), mode, cond)); |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 2437 | } |
| 2438 | |
| 2439 | |
| 2440 | void Assembler::vcvt_s32_f64(const SwVfpRegister dst, |
| 2441 | const DwVfpRegister src, |
ricow@chromium.org | 83aa549 | 2011-02-07 12:42:56 +0000 | [diff] [blame] | 2442 | VFPConversionMode mode, |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 2443 | const Condition cond) { |
kmillikin@chromium.org | c36ce6e | 2011-04-04 08:25:31 +0000 | [diff] [blame] | 2444 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
ager@chromium.org | 01fe7df | 2010-11-10 11:59:11 +0000 | [diff] [blame] | 2445 | emit(EncodeVCVT(S32, dst.code(), F64, src.code(), mode, cond)); |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 2446 | } |
| 2447 | |
| 2448 | |
| 2449 | void Assembler::vcvt_u32_f64(const SwVfpRegister dst, |
| 2450 | const DwVfpRegister src, |
ricow@chromium.org | 83aa549 | 2011-02-07 12:42:56 +0000 | [diff] [blame] | 2451 | VFPConversionMode mode, |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 2452 | const Condition cond) { |
kmillikin@chromium.org | c36ce6e | 2011-04-04 08:25:31 +0000 | [diff] [blame] | 2453 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
ager@chromium.org | 01fe7df | 2010-11-10 11:59:11 +0000 | [diff] [blame] | 2454 | emit(EncodeVCVT(U32, dst.code(), F64, src.code(), mode, cond)); |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 2455 | } |
| 2456 | |
| 2457 | |
| 2458 | void Assembler::vcvt_f64_f32(const DwVfpRegister dst, |
| 2459 | const SwVfpRegister src, |
ricow@chromium.org | 83aa549 | 2011-02-07 12:42:56 +0000 | [diff] [blame] | 2460 | VFPConversionMode mode, |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 2461 | const Condition cond) { |
kmillikin@chromium.org | c36ce6e | 2011-04-04 08:25:31 +0000 | [diff] [blame] | 2462 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
ager@chromium.org | 01fe7df | 2010-11-10 11:59:11 +0000 | [diff] [blame] | 2463 | emit(EncodeVCVT(F64, dst.code(), F32, src.code(), mode, cond)); |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 2464 | } |
| 2465 | |
| 2466 | |
| 2467 | void Assembler::vcvt_f32_f64(const SwVfpRegister dst, |
| 2468 | const DwVfpRegister src, |
ricow@chromium.org | 83aa549 | 2011-02-07 12:42:56 +0000 | [diff] [blame] | 2469 | VFPConversionMode mode, |
kmillikin@chromium.org | 5d8f0e6 | 2010-03-24 08:21:20 +0000 | [diff] [blame] | 2470 | const Condition cond) { |
kmillikin@chromium.org | c36ce6e | 2011-04-04 08:25:31 +0000 | [diff] [blame] | 2471 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
ager@chromium.org | 01fe7df | 2010-11-10 11:59:11 +0000 | [diff] [blame] | 2472 | emit(EncodeVCVT(F32, dst.code(), F64, src.code(), mode, cond)); |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2473 | } |
| 2474 | |
| 2475 | |
ricow@chromium.org | badaffc | 2011-03-17 12:15:27 +0000 | [diff] [blame] | 2476 | void Assembler::vneg(const DwVfpRegister dst, |
| 2477 | const DwVfpRegister src, |
| 2478 | const Condition cond) { |
| 2479 | emit(cond | 0xE*B24 | 0xB*B20 | B16 | dst.code()*B12 | |
| 2480 | 0x5*B9 | B8 | B6 | src.code()); |
| 2481 | } |
| 2482 | |
| 2483 | |
whesse@chromium.org | 7a392b3 | 2011-01-31 11:30:36 +0000 | [diff] [blame] | 2484 | void Assembler::vabs(const DwVfpRegister dst, |
| 2485 | const DwVfpRegister src, |
| 2486 | const Condition cond) { |
| 2487 | emit(cond | 0xE*B24 | 0xB*B20 | dst.code()*B12 | |
| 2488 | 0x5*B9 | B8 | 0x3*B6 | src.code()); |
| 2489 | } |
| 2490 | |
| 2491 | |
kmillikin@chromium.org | 13bd294 | 2009-12-16 15:36:05 +0000 | [diff] [blame] | 2492 | void Assembler::vadd(const DwVfpRegister dst, |
| 2493 | const DwVfpRegister src1, |
| 2494 | const DwVfpRegister src2, |
| 2495 | const Condition cond) { |
| 2496 | // Dd = vadd(Dn, Dm) double precision floating point addition. |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2497 | // Dd = D:Vd; Dm=M:Vm; Dn=N:Vm. |
| 2498 | // Instruction details available in ARM DDI 0406A, A8-536. |
| 2499 | // cond(31-28) | 11100(27-23)| D=?(22) | 11(21-20) | Vn(19-16) | |
| 2500 | // Vd(15-12) | 101(11-9) | sz(8)=1 | N(7)=0 | 0(6) | M=?(5) | 0(4) | Vm(3-0) |
kmillikin@chromium.org | c36ce6e | 2011-04-04 08:25:31 +0000 | [diff] [blame] | 2501 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2502 | emit(cond | 0xE*B24 | 0x3*B20 | src1.code()*B16 | |
| 2503 | dst.code()*B12 | 0x5*B9 | B8 | src2.code()); |
| 2504 | } |
| 2505 | |
| 2506 | |
kmillikin@chromium.org | 13bd294 | 2009-12-16 15:36:05 +0000 | [diff] [blame] | 2507 | void Assembler::vsub(const DwVfpRegister dst, |
| 2508 | const DwVfpRegister src1, |
| 2509 | const DwVfpRegister src2, |
| 2510 | const Condition cond) { |
| 2511 | // Dd = vsub(Dn, Dm) double precision floating point subtraction. |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2512 | // Dd = D:Vd; Dm=M:Vm; Dn=N:Vm. |
| 2513 | // Instruction details available in ARM DDI 0406A, A8-784. |
| 2514 | // cond(31-28) | 11100(27-23)| D=?(22) | 11(21-20) | Vn(19-16) | |
| 2515 | // Vd(15-12) | 101(11-9) | sz(8)=1 | N(7)=0 | 1(6) | M=?(5) | 0(4) | Vm(3-0) |
kmillikin@chromium.org | c36ce6e | 2011-04-04 08:25:31 +0000 | [diff] [blame] | 2516 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2517 | emit(cond | 0xE*B24 | 0x3*B20 | src1.code()*B16 | |
| 2518 | dst.code()*B12 | 0x5*B9 | B8 | B6 | src2.code()); |
| 2519 | } |
| 2520 | |
| 2521 | |
kmillikin@chromium.org | 13bd294 | 2009-12-16 15:36:05 +0000 | [diff] [blame] | 2522 | void Assembler::vmul(const DwVfpRegister dst, |
| 2523 | const DwVfpRegister src1, |
| 2524 | const DwVfpRegister src2, |
| 2525 | const Condition cond) { |
| 2526 | // Dd = vmul(Dn, Dm) double precision floating point multiplication. |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2527 | // Dd = D:Vd; Dm=M:Vm; Dn=N:Vm. |
| 2528 | // Instruction details available in ARM DDI 0406A, A8-784. |
| 2529 | // cond(31-28) | 11100(27-23)| D=?(22) | 10(21-20) | Vn(19-16) | |
| 2530 | // Vd(15-12) | 101(11-9) | sz(8)=1 | N(7)=0 | 0(6) | M=?(5) | 0(4) | Vm(3-0) |
kmillikin@chromium.org | c36ce6e | 2011-04-04 08:25:31 +0000 | [diff] [blame] | 2531 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2532 | emit(cond | 0xE*B24 | 0x2*B20 | src1.code()*B16 | |
| 2533 | dst.code()*B12 | 0x5*B9 | B8 | src2.code()); |
| 2534 | } |
| 2535 | |
| 2536 | |
kmillikin@chromium.org | 13bd294 | 2009-12-16 15:36:05 +0000 | [diff] [blame] | 2537 | void Assembler::vdiv(const DwVfpRegister dst, |
| 2538 | const DwVfpRegister src1, |
| 2539 | const DwVfpRegister src2, |
| 2540 | const Condition cond) { |
| 2541 | // Dd = vdiv(Dn, Dm) double precision floating point division. |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2542 | // Dd = D:Vd; Dm=M:Vm; Dn=N:Vm. |
| 2543 | // Instruction details available in ARM DDI 0406A, A8-584. |
| 2544 | // cond(31-28) | 11101(27-23)| D=?(22) | 00(21-20) | Vn(19-16) | |
| 2545 | // Vd(15-12) | 101(11-9) | sz(8)=1 | N(7)=? | 0(6) | M=?(5) | 0(4) | Vm(3-0) |
kmillikin@chromium.org | c36ce6e | 2011-04-04 08:25:31 +0000 | [diff] [blame] | 2546 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2547 | emit(cond | 0xE*B24 | B23 | src1.code()*B16 | |
| 2548 | dst.code()*B12 | 0x5*B9 | B8 | src2.code()); |
| 2549 | } |
| 2550 | |
| 2551 | |
kmillikin@chromium.org | 13bd294 | 2009-12-16 15:36:05 +0000 | [diff] [blame] | 2552 | void Assembler::vcmp(const DwVfpRegister src1, |
| 2553 | const DwVfpRegister src2, |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2554 | const Condition cond) { |
| 2555 | // vcmp(Dd, Dm) double precision floating point comparison. |
| 2556 | // Instruction details available in ARM DDI 0406A, A8-570. |
| 2557 | // cond(31-28) | 11101 (27-23)| D=?(22) | 11 (21-20) | 0100 (19-16) | |
sgjesse@chromium.org | c6c5718 | 2011-01-17 12:24:25 +0000 | [diff] [blame] | 2558 | // Vd(15-12) | 101(11-9) | sz(8)=1 | E(7)=0 | 1(6) | M(5)=? | 0(4) | Vm(3-0) |
kmillikin@chromium.org | c36ce6e | 2011-04-04 08:25:31 +0000 | [diff] [blame] | 2559 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2560 | emit(cond | 0xE*B24 |B23 | 0x3*B20 | B18 | |
sgjesse@chromium.org | c6c5718 | 2011-01-17 12:24:25 +0000 | [diff] [blame] | 2561 | src1.code()*B12 | 0x5*B9 | B8 | B6 | src2.code()); |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2562 | } |
| 2563 | |
| 2564 | |
ager@chromium.org | ea4f62e | 2010-08-16 16:28:43 +0000 | [diff] [blame] | 2565 | void Assembler::vcmp(const DwVfpRegister src1, |
| 2566 | const double src2, |
ager@chromium.org | ea4f62e | 2010-08-16 16:28:43 +0000 | [diff] [blame] | 2567 | const Condition cond) { |
| 2568 | // vcmp(Dd, Dm) double precision floating point comparison. |
| 2569 | // Instruction details available in ARM DDI 0406A, A8-570. |
| 2570 | // cond(31-28) | 11101 (27-23)| D=?(22) | 11 (21-20) | 0101 (19-16) | |
sgjesse@chromium.org | c6c5718 | 2011-01-17 12:24:25 +0000 | [diff] [blame] | 2571 | // Vd(15-12) | 101(11-9) | sz(8)=1 | E(7)=0 | 1(6) | M(5)=? | 0(4) | 0000(3-0) |
kmillikin@chromium.org | c36ce6e | 2011-04-04 08:25:31 +0000 | [diff] [blame] | 2572 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
ager@chromium.org | ea4f62e | 2010-08-16 16:28:43 +0000 | [diff] [blame] | 2573 | ASSERT(src2 == 0.0); |
| 2574 | emit(cond | 0xE*B24 |B23 | 0x3*B20 | B18 | B16 | |
sgjesse@chromium.org | c6c5718 | 2011-01-17 12:24:25 +0000 | [diff] [blame] | 2575 | src1.code()*B12 | 0x5*B9 | B8 | B6); |
ager@chromium.org | ea4f62e | 2010-08-16 16:28:43 +0000 | [diff] [blame] | 2576 | } |
| 2577 | |
| 2578 | |
ager@chromium.org | 01fe7df | 2010-11-10 11:59:11 +0000 | [diff] [blame] | 2579 | void Assembler::vmsr(Register dst, Condition cond) { |
| 2580 | // Instruction details available in ARM DDI 0406A, A8-652. |
| 2581 | // cond(31-28) | 1110 (27-24) | 1110(23-20)| 0001 (19-16) | |
| 2582 | // Rt(15-12) | 1010 (11-8) | 0(7) | 00 (6-5) | 1(4) | 0000(3-0) |
kmillikin@chromium.org | c36ce6e | 2011-04-04 08:25:31 +0000 | [diff] [blame] | 2583 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
ager@chromium.org | 01fe7df | 2010-11-10 11:59:11 +0000 | [diff] [blame] | 2584 | emit(cond | 0xE*B24 | 0xE*B20 | B16 | |
| 2585 | dst.code()*B12 | 0xA*B8 | B4); |
| 2586 | } |
| 2587 | |
| 2588 | |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2589 | void Assembler::vmrs(Register dst, Condition cond) { |
| 2590 | // Instruction details available in ARM DDI 0406A, A8-652. |
| 2591 | // cond(31-28) | 1110 (27-24) | 1111(23-20)| 0001 (19-16) | |
| 2592 | // Rt(15-12) | 1010 (11-8) | 0(7) | 00 (6-5) | 1(4) | 0000(3-0) |
kmillikin@chromium.org | c36ce6e | 2011-04-04 08:25:31 +0000 | [diff] [blame] | 2593 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2594 | emit(cond | 0xE*B24 | 0xF*B20 | B16 | |
| 2595 | dst.code()*B12 | 0xA*B8 | B4); |
| 2596 | } |
| 2597 | |
| 2598 | |
lrn@chromium.org | 32d961d | 2010-06-30 09:09:34 +0000 | [diff] [blame] | 2599 | void Assembler::vsqrt(const DwVfpRegister dst, |
| 2600 | const DwVfpRegister src, |
| 2601 | const Condition cond) { |
| 2602 | // cond(31-28) | 11101 (27-23)| D=?(22) | 11 (21-20) | 0001 (19-16) | |
| 2603 | // Vd(15-12) | 101(11-9) | sz(8)=1 | 11 (7-6) | M(5)=? | 0(4) | Vm(3-0) |
kmillikin@chromium.org | c36ce6e | 2011-04-04 08:25:31 +0000 | [diff] [blame] | 2604 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
lrn@chromium.org | 32d961d | 2010-06-30 09:09:34 +0000 | [diff] [blame] | 2605 | emit(cond | 0xE*B24 | B23 | 0x3*B20 | B16 | |
| 2606 | dst.code()*B12 | 0x5*B9 | B8 | 3*B6 | src.code()); |
| 2607 | } |
| 2608 | |
| 2609 | |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 2610 | // Pseudo instructions. |
fschneider@chromium.org | 013f3e1 | 2010-04-26 13:27:52 +0000 | [diff] [blame] | 2611 | void Assembler::nop(int type) { |
| 2612 | // This is mov rx, rx. |
| 2613 | ASSERT(0 <= type && type <= 14); // mov pc, pc is not a nop. |
| 2614 | emit(al | 13*B21 | type*B12 | type); |
| 2615 | } |
| 2616 | |
| 2617 | |
ager@chromium.org | beb2571 | 2010-11-29 08:02:25 +0000 | [diff] [blame] | 2618 | bool Assembler::IsNop(Instr instr, int type) { |
sgjesse@chromium.org | 496c03a | 2011-02-14 12:05:43 +0000 | [diff] [blame] | 2619 | // Check for mov rx, rx where x = type. |
ager@chromium.org | beb2571 | 2010-11-29 08:02:25 +0000 | [diff] [blame] | 2620 | ASSERT(0 <= type && type <= 14); // mov pc, pc is not a nop. |
| 2621 | return instr == (al | 13*B21 | type*B12 | type); |
| 2622 | } |
| 2623 | |
| 2624 | |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2625 | bool Assembler::ImmediateFitsAddrMode1Instruction(int32_t imm32) { |
| 2626 | uint32_t dummy1; |
| 2627 | uint32_t dummy2; |
| 2628 | return fits_shifter(imm32, &dummy1, &dummy2, NULL); |
| 2629 | } |
| 2630 | |
| 2631 | |
lrn@chromium.org | c34f580 | 2010-04-28 12:53:43 +0000 | [diff] [blame] | 2632 | void Assembler::BlockConstPoolFor(int instructions) { |
| 2633 | BlockConstPoolBefore(pc_offset() + instructions * kInstrSize); |
| 2634 | } |
| 2635 | |
| 2636 | |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 2637 | // Debugging. |
ager@chromium.org | 4af710e | 2009-09-15 12:20:11 +0000 | [diff] [blame] | 2638 | void Assembler::RecordJSReturn() { |
whesse@chromium.org | f0ac72d | 2010-11-08 12:47:26 +0000 | [diff] [blame] | 2639 | positions_recorder()->WriteRecordedPositions(); |
ager@chromium.org | 4af710e | 2009-09-15 12:20:11 +0000 | [diff] [blame] | 2640 | CheckBuffer(); |
| 2641 | RecordRelocInfo(RelocInfo::JS_RETURN); |
| 2642 | } |
| 2643 | |
| 2644 | |
vegorov@chromium.org | 2356e6f | 2010-06-09 09:38:56 +0000 | [diff] [blame] | 2645 | void Assembler::RecordDebugBreakSlot() { |
whesse@chromium.org | f0ac72d | 2010-11-08 12:47:26 +0000 | [diff] [blame] | 2646 | positions_recorder()->WriteRecordedPositions(); |
vegorov@chromium.org | 2356e6f | 2010-06-09 09:38:56 +0000 | [diff] [blame] | 2647 | CheckBuffer(); |
| 2648 | RecordRelocInfo(RelocInfo::DEBUG_BREAK_SLOT); |
| 2649 | } |
| 2650 | |
| 2651 | |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 2652 | void Assembler::RecordComment(const char* msg) { |
kasperl@chromium.org | a555126 | 2010-12-07 12:49:48 +0000 | [diff] [blame] | 2653 | if (FLAG_code_comments) { |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 2654 | CheckBuffer(); |
ager@chromium.org | 236ad96 | 2008-09-25 09:45:57 +0000 | [diff] [blame] | 2655 | RecordRelocInfo(RelocInfo::COMMENT, reinterpret_cast<intptr_t>(msg)); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 2656 | } |
| 2657 | } |
| 2658 | |
| 2659 | |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 2660 | void Assembler::GrowBuffer() { |
| 2661 | if (!own_buffer_) FATAL("external code buffer is too small"); |
| 2662 | |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 2663 | // Compute new buffer size. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 2664 | CodeDesc desc; // the new buffer |
| 2665 | if (buffer_size_ < 4*KB) { |
| 2666 | desc.buffer_size = 4*KB; |
| 2667 | } else if (buffer_size_ < 1*MB) { |
| 2668 | desc.buffer_size = 2*buffer_size_; |
| 2669 | } else { |
| 2670 | desc.buffer_size = buffer_size_ + 1*MB; |
| 2671 | } |
| 2672 | CHECK_GT(desc.buffer_size, 0); // no overflow |
| 2673 | |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 2674 | // Setup new buffer. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 2675 | desc.buffer = NewArray<byte>(desc.buffer_size); |
| 2676 | |
| 2677 | desc.instr_size = pc_offset(); |
| 2678 | desc.reloc_size = (buffer_ + buffer_size_) - reloc_info_writer.pos(); |
| 2679 | |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 2680 | // Copy the data. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 2681 | int pc_delta = desc.buffer - buffer_; |
| 2682 | int rc_delta = (desc.buffer + desc.buffer_size) - (buffer_ + buffer_size_); |
| 2683 | memmove(desc.buffer, buffer_, desc.instr_size); |
| 2684 | memmove(reloc_info_writer.pos() + rc_delta, |
| 2685 | reloc_info_writer.pos(), desc.reloc_size); |
| 2686 | |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 2687 | // Switch buffers. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 2688 | DeleteArray(buffer_); |
| 2689 | buffer_ = desc.buffer; |
| 2690 | buffer_size_ = desc.buffer_size; |
| 2691 | pc_ += pc_delta; |
| 2692 | reloc_info_writer.Reposition(reloc_info_writer.pos() + rc_delta, |
| 2693 | reloc_info_writer.last_pc() + pc_delta); |
| 2694 | |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 2695 | // None of our relocation types are pc relative pointing outside the code |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 2696 | // buffer nor pc absolute pointing inside the code buffer, so there is no need |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 2697 | // to relocate any emitted relocation entries. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 2698 | |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 2699 | // Relocate pending relocation entries. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 2700 | for (int i = 0; i < num_prinfo_; i++) { |
| 2701 | RelocInfo& rinfo = prinfo_[i]; |
ager@chromium.org | 236ad96 | 2008-09-25 09:45:57 +0000 | [diff] [blame] | 2702 | ASSERT(rinfo.rmode() != RelocInfo::COMMENT && |
| 2703 | rinfo.rmode() != RelocInfo::POSITION); |
ager@chromium.org | 4af710e | 2009-09-15 12:20:11 +0000 | [diff] [blame] | 2704 | if (rinfo.rmode() != RelocInfo::JS_RETURN) { |
| 2705 | rinfo.set_pc(rinfo.pc() + pc_delta); |
| 2706 | } |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 2707 | } |
| 2708 | } |
| 2709 | |
| 2710 | |
kasperl@chromium.org | a555126 | 2010-12-07 12:49:48 +0000 | [diff] [blame] | 2711 | void Assembler::db(uint8_t data) { |
erik.corry@gmail.com | 0511e24 | 2011-01-19 11:11:08 +0000 | [diff] [blame] | 2712 | // No relocation info should be pending while using db. db is used |
| 2713 | // to write pure data with no pointers and the constant pool should |
| 2714 | // be emitted before using db. |
| 2715 | ASSERT(num_prinfo_ == 0); |
kasperl@chromium.org | a555126 | 2010-12-07 12:49:48 +0000 | [diff] [blame] | 2716 | CheckBuffer(); |
| 2717 | *reinterpret_cast<uint8_t*>(pc_) = data; |
| 2718 | pc_ += sizeof(uint8_t); |
| 2719 | } |
| 2720 | |
| 2721 | |
| 2722 | void Assembler::dd(uint32_t data) { |
erik.corry@gmail.com | 0511e24 | 2011-01-19 11:11:08 +0000 | [diff] [blame] | 2723 | // No relocation info should be pending while using dd. dd is used |
| 2724 | // to write pure data with no pointers and the constant pool should |
| 2725 | // be emitted before using dd. |
| 2726 | ASSERT(num_prinfo_ == 0); |
kasperl@chromium.org | a555126 | 2010-12-07 12:49:48 +0000 | [diff] [blame] | 2727 | CheckBuffer(); |
| 2728 | *reinterpret_cast<uint32_t*>(pc_) = data; |
| 2729 | pc_ += sizeof(uint32_t); |
| 2730 | } |
| 2731 | |
| 2732 | |
ager@chromium.org | 236ad96 | 2008-09-25 09:45:57 +0000 | [diff] [blame] | 2733 | void Assembler::RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data) { |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 2734 | RelocInfo rinfo(pc_, rmode, data); // we do not try to reuse pool constants |
vegorov@chromium.org | 2356e6f | 2010-06-09 09:38:56 +0000 | [diff] [blame] | 2735 | if (rmode >= RelocInfo::JS_RETURN && rmode <= RelocInfo::DEBUG_BREAK_SLOT) { |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 2736 | // Adjust code for new modes. |
vegorov@chromium.org | 2356e6f | 2010-06-09 09:38:56 +0000 | [diff] [blame] | 2737 | ASSERT(RelocInfo::IsDebugBreakSlot(rmode) |
| 2738 | || RelocInfo::IsJSReturn(rmode) |
ager@chromium.org | 4af710e | 2009-09-15 12:20:11 +0000 | [diff] [blame] | 2739 | || RelocInfo::IsComment(rmode) |
| 2740 | || RelocInfo::IsPosition(rmode)); |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 2741 | // These modes do not need an entry in the constant pool. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 2742 | } else { |
| 2743 | ASSERT(num_prinfo_ < kMaxNumPRInfo); |
| 2744 | prinfo_[num_prinfo_++] = rinfo; |
| 2745 | // Make sure the constant pool is not emitted in place of the next |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 2746 | // instruction for which we just recorded relocation info. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 2747 | BlockConstPoolBefore(pc_offset() + kInstrSize); |
| 2748 | } |
ager@chromium.org | 236ad96 | 2008-09-25 09:45:57 +0000 | [diff] [blame] | 2749 | if (rinfo.rmode() != RelocInfo::NONE) { |
mads.s.ager@gmail.com | 9a4089a | 2008-09-01 08:55:01 +0000 | [diff] [blame] | 2750 | // Don't record external references unless the heap will be serialized. |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2751 | if (rmode == RelocInfo::EXTERNAL_REFERENCE) { |
| 2752 | #ifdef DEBUG |
| 2753 | if (!Serializer::enabled()) { |
| 2754 | Serializer::TooLateToEnableNow(); |
| 2755 | } |
| 2756 | #endif |
ricow@chromium.org | badaffc | 2011-03-17 12:15:27 +0000 | [diff] [blame] | 2757 | if (!Serializer::enabled() && !emit_debug_code()) { |
ager@chromium.org | c4c9272 | 2009-11-18 14:12:51 +0000 | [diff] [blame] | 2758 | return; |
| 2759 | } |
mads.s.ager@gmail.com | 9a4089a | 2008-09-01 08:55:01 +0000 | [diff] [blame] | 2760 | } |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 2761 | ASSERT(buffer_space() >= kMaxRelocSize); // too late to grow buffer here |
| 2762 | reloc_info_writer.Write(&rinfo); |
| 2763 | } |
| 2764 | } |
| 2765 | |
| 2766 | |
| 2767 | void Assembler::CheckConstPool(bool force_emit, bool require_jump) { |
| 2768 | // Calculate the offset of the next check. It will be overwritten |
| 2769 | // when a const pool is generated or when const pools are being |
| 2770 | // blocked for a specific range. |
| 2771 | next_buffer_check_ = pc_offset() + kCheckConstInterval; |
| 2772 | |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 2773 | // There is nothing to do if there are no pending relocation info entries. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 2774 | if (num_prinfo_ == 0) return; |
| 2775 | |
| 2776 | // We emit a constant pool at regular intervals of about kDistBetweenPools |
| 2777 | // or when requested by parameter force_emit (e.g. after each function). |
| 2778 | // We prefer not to emit a jump unless the max distance is reached or if we |
| 2779 | // are running low on slots, which can happen if a lot of constants are being |
| 2780 | // emitted (e.g. --debug-code and many static references). |
| 2781 | int dist = pc_offset() - last_const_pool_end_; |
| 2782 | if (!force_emit && dist < kMaxDistBetweenPools && |
| 2783 | (require_jump || dist < kDistBetweenPools) && |
| 2784 | // TODO(1236125): Cleanup the "magic" number below. We know that |
| 2785 | // the code generation will test every kCheckConstIntervalInst. |
| 2786 | // Thus we are safe as long as we generate less than 7 constant |
| 2787 | // entries per instruction. |
| 2788 | (num_prinfo_ < (kMaxNumPRInfo - (7 * kCheckConstIntervalInst)))) { |
| 2789 | return; |
| 2790 | } |
| 2791 | |
| 2792 | // If we did not return by now, we need to emit the constant pool soon. |
| 2793 | |
| 2794 | // However, some small sequences of instructions must not be broken up by the |
| 2795 | // insertion of a constant pool; such sequences are protected by setting |
fschneider@chromium.org | 013f3e1 | 2010-04-26 13:27:52 +0000 | [diff] [blame] | 2796 | // either const_pool_blocked_nesting_ or no_const_pool_before_, which are |
| 2797 | // both checked here. Also, recursive calls to CheckConstPool are blocked by |
| 2798 | // no_const_pool_before_. |
| 2799 | if (const_pool_blocked_nesting_ > 0 || pc_offset() < no_const_pool_before_) { |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 2800 | // Emission is currently blocked; make sure we try again as soon as |
| 2801 | // possible. |
fschneider@chromium.org | 013f3e1 | 2010-04-26 13:27:52 +0000 | [diff] [blame] | 2802 | if (const_pool_blocked_nesting_ > 0) { |
| 2803 | next_buffer_check_ = pc_offset() + kInstrSize; |
| 2804 | } else { |
| 2805 | next_buffer_check_ = no_const_pool_before_; |
| 2806 | } |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 2807 | |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 2808 | // Something is wrong if emission is forced and blocked at the same time. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 2809 | ASSERT(!force_emit); |
| 2810 | return; |
| 2811 | } |
| 2812 | |
| 2813 | int jump_instr = require_jump ? kInstrSize : 0; |
| 2814 | |
| 2815 | // Check that the code buffer is large enough before emitting the constant |
| 2816 | // pool and relocation information (include the jump over the pool and the |
| 2817 | // constant pool marker). |
| 2818 | int max_needed_space = |
| 2819 | jump_instr + kInstrSize + num_prinfo_*(kInstrSize + kMaxRelocSize); |
| 2820 | while (buffer_space() <= (max_needed_space + kGap)) GrowBuffer(); |
| 2821 | |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 2822 | // Block recursive calls to CheckConstPool. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 2823 | BlockConstPoolBefore(pc_offset() + jump_instr + kInstrSize + |
| 2824 | num_prinfo_*kInstrSize); |
| 2825 | // Don't bother to check for the emit calls below. |
| 2826 | next_buffer_check_ = no_const_pool_before_; |
| 2827 | |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 2828 | // Emit jump over constant pool if necessary. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 2829 | Label after_pool; |
| 2830 | if (require_jump) b(&after_pool); |
| 2831 | |
| 2832 | RecordComment("[ Constant Pool"); |
| 2833 | |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 2834 | // Put down constant pool marker "Undefined instruction" as specified by |
sgjesse@chromium.org | ea88ce9 | 2011-03-23 11:19:56 +0000 | [diff] [blame] | 2835 | // A5.6 (ARMv7) Instruction set encoding. |
| 2836 | emit(kConstantPoolMarker | num_prinfo_); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 2837 | |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 2838 | // Emit constant pool entries. |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 2839 | for (int i = 0; i < num_prinfo_; i++) { |
| 2840 | RelocInfo& rinfo = prinfo_[i]; |
ager@chromium.org | 236ad96 | 2008-09-25 09:45:57 +0000 | [diff] [blame] | 2841 | ASSERT(rinfo.rmode() != RelocInfo::COMMENT && |
| 2842 | rinfo.rmode() != RelocInfo::POSITION && |
| 2843 | rinfo.rmode() != RelocInfo::STATEMENT_POSITION); |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 2844 | Instr instr = instr_at(rinfo.pc()); |
ager@chromium.org | 4af710e | 2009-09-15 12:20:11 +0000 | [diff] [blame] | 2845 | |
ager@chromium.org | 5c83825 | 2010-02-19 08:53:10 +0000 | [diff] [blame] | 2846 | // Instruction to patch must be a ldr/str [pc, #offset]. |
| 2847 | // P and U set, B and W clear, Rn == pc, offset12 still 0. |
ager@chromium.org | 378b34e | 2011-01-28 08:04:38 +0000 | [diff] [blame] | 2848 | ASSERT((instr & (7*B25 | P | U | B | W | 15*B16 | kOff12Mask)) == |
christian.plesner.hansen | 43d26ec | 2008-07-03 15:10:15 +0000 | [diff] [blame] | 2849 | (2*B25 | P | U | pc.code()*B16)); |
| 2850 | int delta = pc_ - rinfo.pc() - 8; |
| 2851 | ASSERT(delta >= -4); // instr could be ldr pc, [pc, #-4] followed by targ32 |
| 2852 | if (delta < 0) { |
| 2853 | instr &= ~U; |
| 2854 | delta = -delta; |
| 2855 | } |
| 2856 | ASSERT(is_uint12(delta)); |
| 2857 | instr_at_put(rinfo.pc(), instr + delta); |
| 2858 | emit(rinfo.data()); |
| 2859 | } |
| 2860 | num_prinfo_ = 0; |
| 2861 | last_const_pool_end_ = pc_offset(); |
| 2862 | |
| 2863 | RecordComment("]"); |
| 2864 | |
| 2865 | if (after_pool.is_linked()) { |
| 2866 | bind(&after_pool); |
| 2867 | } |
| 2868 | |
| 2869 | // Since a constant pool was just emitted, move the check offset forward by |
| 2870 | // the standard interval. |
| 2871 | next_buffer_check_ = pc_offset() + kCheckConstInterval; |
| 2872 | } |
| 2873 | |
| 2874 | |
| 2875 | } } // namespace v8::internal |
erik.corry@gmail.com | 9dfbea4 | 2010-05-21 12:58:28 +0000 | [diff] [blame] | 2876 | |
| 2877 | #endif // V8_TARGET_ARCH_ARM |