Revert some Hexagon builtin commits to match reverts done to LLVM in
r155047. See the LLVM log for the primary motivation:
http://llvm.org/viewvc/llvm-project?rev=155047&view=rev
Primary commit r154828:
- Several issues were raised in review, and fixed in subsequent
commits.
- Follow-up commits also reverted, and which should be folded into the
original before reposting:
- r154837: Re-add the 'undef BUILTIN' thing to fix the build.
- r154928: Fix build warnings, re-add (and correct) header and
license
- r154937: Typo fix.
Please resubmit this patch with the relevant LLVM resubmission.
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@155048 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Basic/Targets.cpp b/lib/Basic/Targets.cpp
index 482cf8f..1eceaaa 100644
--- a/lib/Basic/Targets.cpp
+++ b/lib/Basic/Targets.cpp
@@ -3015,8 +3015,8 @@
HexagonTargetInfo(const std::string& triple) : TargetInfo(triple) {
BigEndian = false;
DescriptionString = ("e-p:32:32:32-"
- "i64:64:64-i32:32:32-i16:16:16-i1:32:32"
- "f64:64:64-f32:32:32-a0:0-n32");
+ "i64:64:64-i32:32:32-"
+ "i16:16:16-i1:32:32-a:0:0");
// {} in inline assembly are packet specifiers, not assembly variant
// specifiers.
@@ -3057,7 +3057,6 @@
.Case("hexagonv2", "2")
.Case("hexagonv3", "3")
.Case("hexagonv4", "4")
- .Case("hexagonv5", "5")
.Default(0);
}
@@ -3112,14 +3111,6 @@
Builder.defineMacro("__QDSP6_ARCH__", "4");
}
}
- else if(CPU == "hexagonv5") {
- Builder.defineMacro("__HEXAGON_V5__");
- Builder.defineMacro("__HEXAGON_ARCH__", "5");
- if(Opts.HexagonQdsp6Compat) {
- Builder.defineMacro("__QDSP6_V5__");
- Builder.defineMacro("__QDSP6_ARCH__", "5");
- }
- }
}
const char * const HexagonTargetInfo::GCCRegNames[] = {