ARM: Swap which registers we consider real / aliases to match LLVM and llvm-gcc.
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@110774 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Basic/Targets.cpp b/lib/Basic/Targets.cpp
index 40a0296..3eee5c0 100644
--- a/lib/Basic/Targets.cpp
+++ b/lib/Basic/Targets.cpp
@@ -1788,17 +1788,16 @@
const char * const ARMTargetInfo::GCCRegNames[] = {
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
- "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
+ "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc"
};
void ARMTargetInfo::getGCCRegNames(const char * const *&Names,
- unsigned &NumNames) const {
+ unsigned &NumNames) const {
Names = GCCRegNames;
NumNames = llvm::array_lengthof(GCCRegNames);
}
const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
-
{ { "a1" }, "r0" },
{ { "a2" }, "r1" },
{ { "a3" }, "r2" },
@@ -1812,9 +1811,9 @@
{ { "sl" }, "r10" },
{ { "fp" }, "r11" },
{ { "ip" }, "r12" },
- { { "sp" }, "r13" },
- { { "lr" }, "r14" },
- { { "pc" }, "r15" },
+ { { "r13" }, "sp" },
+ { { "r14" }, "lr" },
+ { { "r15" }, "pc" },
};
void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
diff --git a/test/CodeGen/asm_arm.c b/test/CodeGen/asm_arm.c
index aac47d5..12cf5d7 100644
--- a/test/CodeGen/asm_arm.c
+++ b/test/CodeGen/asm_arm.c
@@ -30,3 +30,11 @@
"vst1.32 {q4}, [%0,:128] \n\t"
:: "r"(a), "r"(b));
}
+
+// {sp, lr, pc} are the canonical names for {r13, r14, r15}.
+//
+// CHECK: @test5
+// CHECK: call void asm sideeffect "", "~{sp},~{lr},~{pc},~{sp},~{lr},~{pc}"()
+void test5() {
+ __asm__("" : : : "r13", "r14", "r15", "sp", "lr", "pc");
+}