commit 5cada6bd7f0a9f1c0f82613924610177d676ced5
author Devang Patel <dpatel@apple.com> Wed May 07 22:28:29 2008 +0000
committer Devang Patel <dpatel@apple.com> Wed May 07 22:28:29 2008 +0000
tree ae2681a9c78ef755f747fac0990706a3a7b22217
parent 5df5b76594f7112c3bf4a07fe9c9d224c1b9c86f

Begin handling union bitfields.
Note, this is just beginning.


git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@50835 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/CodeGenTypes.cpp

diff --git a/lib/CodeGen/CodeGenTypes.cpp b/lib/CodeGen/CodeGenTypes.cpp
index 751cd3a..1544050 100644
--- a/lib/CodeGen/CodeGenTypes.cpp
+++ b/lib/CodeGen/CodeGenTypes.cpp
@@ -593,12 +593,14 @@
   unsigned PrimaryEltNo = 0;
   std::pair<uint64_t, unsigned> PrimaryElt =
     CGT.getContext().getTypeInfo(FieldDecls[0]->getType());
-  CGT.addFieldInfo(FieldDecls[0], 0);
+    if (FieldDecls[0]->isBitField()) 
+      placeBitField(FieldDecls[0]);
+    else
+      CGT.addFieldInfo(FieldDecls[0], 0);
 
   unsigned Size = FieldDecls.size();
   for(unsigned i = 1; i != Size; ++i) {
     const FieldDecl *FD = FieldDecls[i];
-    assert (!FD->isBitField() && "Bit fields are not yet supported");
     std::pair<uint64_t, unsigned> EltInfo = 
       CGT.getContext().getTypeInfo(FD->getType());
 
@@ -611,7 +613,10 @@
     }
 
     // In union, each field gets first slot.
-    CGT.addFieldInfo(FD, 0);
+    if (FD->isBitField()) 
+      placeBitField(FD);
+    else
+      CGT.addFieldInfo(FD, 0);
   }
 
   std::vector<const llvm::Type*> Fields;

test/CodeGen/union.c

diff --git a/test/CodeGen/union.c b/test/CodeGen/union.c
index 4d32abd..b47e697 100644
--- a/test/CodeGen/union.c
+++ b/test/CodeGen/union.c
@@ -26,3 +26,8 @@
 int f3(value v) {
   return *v.j;
 }
+
+enum E9 { one, two };
+union S65 { enum E9 a:62; } ; union S65 s65;
+void fS65() { enum E9 e = s65.a; } 
+