ARM: Recognize single precision float register names.
- We don't recognize double or NEON register names yet -- we don't have the
infrastructure to generate the right clobbers for them.
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@110775 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Basic/Targets.cpp b/lib/Basic/Targets.cpp
index 3eee5c0..1e8ed79 100644
--- a/lib/Basic/Targets.cpp
+++ b/lib/Basic/Targets.cpp
@@ -1787,8 +1787,18 @@
};
const char * const ARMTargetInfo::GCCRegNames[] = {
+ // Integer registers
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
- "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc"
+ "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
+
+ // Float registers
+ "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
+ "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
+ "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
+ "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31"
+
+ // FIXME: Need double and NEON registers, but we need support for aliasing
+ // multiple registers for that.
};
void ARMTargetInfo::getGCCRegNames(const char * const *&Names,
diff --git a/test/CodeGen/asm_arm.c b/test/CodeGen/asm_arm.c
index 12cf5d7..633bf55 100644
--- a/test/CodeGen/asm_arm.c
+++ b/test/CodeGen/asm_arm.c
@@ -38,3 +38,17 @@
void test5() {
__asm__("" : : : "r13", "r14", "r15", "sp", "lr", "pc");
}
+
+// CHECK: @test6
+// CHECK: call void asm sideeffect "", "
+// CHECK: ~{s0},~{s1},~{s2},~{s3},~{s4},~{s5},~{s6},~{s7},
+// CHECK: ~{s8},~{s9},~{s10},~{s11},~{s12},~{s13},~{s14},~{s15},
+// CHECK: ~{s16},~{s17},~{s18},~{s19},~{s20},~{s21},~{s22},~{s23},
+// CHECK: ~{s24},~{s25},~{s26},~{s27},~{s28},~{s29},~{s30},~{s31}"()
+void test6() {
+ __asm__("" : : :
+ "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
+ "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
+ "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
+ "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31");
+}