Jim Grosbach | f794705 | 2012-07-09 18:34:21 +0000 | [diff] [blame] | 1 | // REQUIRES: mips-registered-target |
Simon Atanasyan | fbf7005 | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 2 | // RUN: %clang_cc1 -triple mips-unknown-linux-gnu -emit-llvm -o %t %s |
| 3 | // RUN: not grep __builtin %t |
| 4 | |
| 5 | typedef int q31; |
| 6 | typedef int i32; |
| 7 | typedef unsigned int ui32; |
| 8 | typedef long long a64; |
| 9 | |
| 10 | typedef signed char v4i8 __attribute__ ((vector_size(4))); |
| 11 | typedef short v2q15 __attribute__ ((vector_size(4))); |
| 12 | |
| 13 | void foo() { |
| 14 | v2q15 v2q15_r, v2q15_a, v2q15_b, v2q15_c; |
| 15 | v4i8 v4i8_r, v4i8_a, v4i8_b, v4i8_c; |
| 16 | q31 q31_r, q31_a, q31_b, q31_c; |
| 17 | i32 i32_r, i32_a, i32_b, i32_c; |
| 18 | ui32 ui32_r, ui32_a, ui32_b, ui32_c; |
| 19 | a64 a64_r, a64_a, a64_b; |
| 20 | |
| 21 | // MIPS DSP Rev 1 |
| 22 | |
| 23 | v4i8_a = (v4i8) {1, 2, 3, 0xFF}; |
| 24 | v4i8_b = (v4i8) {2, 4, 6, 8}; |
| 25 | v4i8_r = __builtin_mips_addu_qb(v4i8_a, v4i8_b); |
| 26 | v4i8_r = __builtin_mips_addu_s_qb(v4i8_a, v4i8_b); |
| 27 | v4i8_r = __builtin_mips_subu_qb(v4i8_a, v4i8_b); |
| 28 | v4i8_r = __builtin_mips_subu_s_qb(v4i8_a, v4i8_b); |
| 29 | |
| 30 | v2q15_a = (v2q15) {0x0000, 0x8000}; |
| 31 | v2q15_b = (v2q15) {0x8000, 0x8000}; |
| 32 | v2q15_r = __builtin_mips_addq_ph(v2q15_a, v2q15_b); |
| 33 | v2q15_r = __builtin_mips_addq_s_ph(v2q15_a, v2q15_b); |
| 34 | v2q15_r = __builtin_mips_subq_ph(v2q15_a, v2q15_b); |
| 35 | v2q15_r = __builtin_mips_subq_s_ph(v2q15_a, v2q15_b); |
| 36 | |
| 37 | a64_a = 0x12345678; |
| 38 | i32_b = 0x80000000; |
| 39 | i32_c = 0x11112222; |
| 40 | a64_r = __builtin_mips_madd(a64_a, i32_b, i32_c); |
| 41 | a64_a = 0x12345678; |
| 42 | ui32_b = 0x80000000; |
| 43 | ui32_c = 0x11112222; |
| 44 | a64_r = __builtin_mips_maddu(a64_a, ui32_b, ui32_c); |
| 45 | a64_a = 0x12345678; |
| 46 | i32_b = 0x80000000; |
| 47 | i32_c = 0x11112222; |
| 48 | a64_r = __builtin_mips_msub(a64_a, i32_b, i32_c); |
| 49 | a64_a = 0x12345678; |
| 50 | ui32_b = 0x80000000; |
| 51 | ui32_c = 0x11112222; |
| 52 | a64_r = __builtin_mips_msubu(a64_a, ui32_b, ui32_c); |
| 53 | |
| 54 | q31_a = 0x12345678; |
| 55 | q31_b = 0x7FFFFFFF; |
| 56 | q31_r = __builtin_mips_addq_s_w(q31_a, q31_b); |
| 57 | q31_r = __builtin_mips_subq_s_w(q31_a, q31_b); |
| 58 | |
| 59 | i32_a = 0xFFFFFFFF; |
| 60 | i32_b = 1; |
| 61 | i32_r = __builtin_mips_addsc(i32_a, i32_b); |
| 62 | i32_a = 0; |
| 63 | i32_b = 1; |
| 64 | i32_r = __builtin_mips_addwc(i32_a, i32_b); |
| 65 | |
| 66 | i32_a = 20; |
| 67 | i32_b = 0x1402; |
| 68 | i32_r = __builtin_mips_modsub(i32_a, i32_b); |
| 69 | |
| 70 | v4i8_a = (v4i8) {1, 2, 3, 4}; |
| 71 | i32_r = __builtin_mips_raddu_w_qb(v4i8_a); |
| 72 | |
| 73 | v2q15_a = (v2q15) {0xFFFF, 0x8000}; |
| 74 | v2q15_r = __builtin_mips_absq_s_ph(v2q15_a); |
| 75 | q31_a = 0x80000000; |
| 76 | q31_r = __builtin_mips_absq_s_w(q31_a); |
| 77 | |
| 78 | v2q15_a = (v2q15) {0x1234, 0x5678}; |
| 79 | v2q15_b = (v2q15) {0x1111, 0x2222}; |
| 80 | v4i8_r = __builtin_mips_precrq_qb_ph(v2q15_a, v2q15_b); |
| 81 | |
| 82 | v2q15_a = (v2q15) {0x7F79, 0xFFFF}; |
| 83 | v2q15_b = (v2q15) {0x7F81, 0x2000}; |
| 84 | v4i8_r = __builtin_mips_precrqu_s_qb_ph(v2q15_a, v2q15_b); |
| 85 | q31_a = 0x12345678; |
| 86 | q31_b = 0x11112222; |
| 87 | v2q15_r = __builtin_mips_precrq_ph_w(q31_a, q31_b); |
| 88 | q31_a = 0x7000FFFF; |
| 89 | q31_b = 0x80000000; |
| 90 | v2q15_r = __builtin_mips_precrq_rs_ph_w(q31_a, q31_b); |
| 91 | v2q15_a = (v2q15) {0x1234, 0x5678}; |
| 92 | q31_r = __builtin_mips_preceq_w_phl(v2q15_a); |
| 93 | q31_r = __builtin_mips_preceq_w_phr(v2q15_a); |
| 94 | v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78}; |
| 95 | v2q15_r = __builtin_mips_precequ_ph_qbl(v4i8_a); |
| 96 | v2q15_r = __builtin_mips_precequ_ph_qbr(v4i8_a); |
| 97 | v2q15_r = __builtin_mips_precequ_ph_qbla(v4i8_a); |
| 98 | v2q15_r = __builtin_mips_precequ_ph_qbra(v4i8_a); |
| 99 | v2q15_r = __builtin_mips_preceu_ph_qbl(v4i8_a); |
| 100 | v2q15_r = __builtin_mips_preceu_ph_qbr(v4i8_a); |
| 101 | v2q15_r = __builtin_mips_preceu_ph_qbla(v4i8_a); |
| 102 | v2q15_r = __builtin_mips_preceu_ph_qbra(v4i8_a); |
| 103 | |
| 104 | v4i8_a = (v4i8) {1, 2, 3, 4}; |
| 105 | v4i8_r = __builtin_mips_shll_qb(v4i8_a, 2); |
| 106 | v4i8_a = (v4i8) {128, 64, 32, 16}; |
| 107 | v4i8_r = __builtin_mips_shrl_qb(v4i8_a, 2); |
| 108 | v2q15_a = (v2q15) {0x0001, 0x8000}; |
| 109 | v2q15_r = __builtin_mips_shll_ph(v2q15_a, 2); |
| 110 | v2q15_r = __builtin_mips_shll_s_ph(v2q15_a, 2); |
| 111 | v2q15_a = (v2q15) {0x7FFF, 0x8000}; |
| 112 | v2q15_r = __builtin_mips_shra_ph(v2q15_a, 2); |
| 113 | v2q15_r = __builtin_mips_shra_r_ph(v2q15_a, 2); |
| 114 | q31_a = 0x70000000; |
| 115 | q31_r = __builtin_mips_shll_s_w(q31_a, 2); |
| 116 | q31_a = 0x7FFFFFFF; |
| 117 | q31_r = __builtin_mips_shra_r_w(q31_a, 2); |
| 118 | a64_a = 0x1234567887654321LL; |
| 119 | a64_r = __builtin_mips_shilo(a64_a, -8); |
| 120 | |
| 121 | v4i8_a = (v4i8) {0x1, 0x3, 0x5, 0x7}; |
| 122 | v2q15_b = (v2q15) {0x1234, 0x5678}; |
| 123 | v2q15_r = __builtin_mips_muleu_s_ph_qbl(v4i8_a, v2q15_b); |
| 124 | v2q15_r = __builtin_mips_muleu_s_ph_qbr(v4i8_a, v2q15_b); |
| 125 | v2q15_a = (v2q15) {0x7FFF, 0x8000}; |
| 126 | v2q15_b = (v2q15) {0x7FFF, 0x8000}; |
| 127 | v2q15_r = __builtin_mips_mulq_rs_ph(v2q15_a, v2q15_b); |
| 128 | v2q15_a = (v2q15) {0x1234, 0x8000}; |
| 129 | v2q15_b = (v2q15) {0x5678, 0x8000}; |
| 130 | q31_r = __builtin_mips_muleq_s_w_phl(v2q15_a, v2q15_b); |
| 131 | q31_r = __builtin_mips_muleq_s_w_phr(v2q15_a, v2q15_b); |
| 132 | a64_a = 0; |
| 133 | v2q15_a = (v2q15) {0x0001, 0x8000}; |
| 134 | v2q15_b = (v2q15) {0x0002, 0x8000}; |
| 135 | a64_r = __builtin_mips_mulsaq_s_w_ph(a64_a, v2q15_b, v2q15_c); |
| 136 | a64_a = 0; |
| 137 | v2q15_b = (v2q15) {0x0001, 0x8000}; |
| 138 | v2q15_c = (v2q15) {0x0002, 0x8000}; |
| 139 | a64_r = __builtin_mips_maq_s_w_phl(a64_a, v2q15_b, v2q15_c); |
| 140 | a64_r = __builtin_mips_maq_s_w_phr(a64_a, v2q15_b, v2q15_c); |
| 141 | a64_a = 0x7FFFFFF0; |
| 142 | a64_r = __builtin_mips_maq_sa_w_phl(a64_a, v2q15_b, v2q15_c); |
| 143 | a64_r = __builtin_mips_maq_sa_w_phr(a64_a, v2q15_b, v2q15_c); |
| 144 | i32_a = 0x80000000; |
| 145 | i32_b = 0x11112222; |
| 146 | a64_r = __builtin_mips_mult(i32_a, i32_b); |
| 147 | ui32_a = 0x80000000; |
| 148 | ui32_b = 0x11112222; |
| 149 | a64_r = __builtin_mips_multu(ui32_a, ui32_b); |
| 150 | |
| 151 | a64_a = 0; |
| 152 | v4i8_b = (v4i8) {1, 2, 3, 4}; |
| 153 | v4i8_c = (v4i8) {4, 5, 6, 7}; |
| 154 | a64_r = __builtin_mips_dpau_h_qbl(a64_a, v4i8_b, v4i8_c); |
| 155 | a64_r = __builtin_mips_dpau_h_qbr(a64_a, v4i8_b, v4i8_c); |
| 156 | a64_r = __builtin_mips_dpsu_h_qbl(a64_a, v4i8_b, v4i8_c); |
| 157 | a64_r = __builtin_mips_dpsu_h_qbr(a64_a, v4i8_b, v4i8_c); |
| 158 | a64_a = 0; |
| 159 | v2q15_b = (v2q15) {0x0001, 0x8000}; |
| 160 | v2q15_c = (v2q15) {0x0002, 0x8000}; |
| 161 | a64_r = __builtin_mips_dpaq_s_w_ph(a64_a, v2q15_b, v2q15_c); |
| 162 | a64_r = __builtin_mips_dpsq_s_w_ph(a64_a, v2q15_b, v2q15_c); |
| 163 | a64_a = 0; |
| 164 | q31_b = 0x80000000; |
| 165 | q31_c = 0x80000000; |
| 166 | a64_r = __builtin_mips_dpaq_sa_l_w(a64_a, q31_b, q31_c); |
| 167 | a64_r = __builtin_mips_dpsq_sa_l_w(a64_a, q31_b, q31_c); |
| 168 | |
| 169 | v4i8_a = (v4i8) {1, 4, 10, 8}; |
| 170 | v4i8_b = (v4i8) {1, 2, 100, 8}; |
| 171 | __builtin_mips_cmpu_eq_qb(v4i8_a, v4i8_b); |
| 172 | __builtin_mips_cmpu_lt_qb(v4i8_a, v4i8_b); |
| 173 | __builtin_mips_cmpu_le_qb(v4i8_a, v4i8_b); |
| 174 | i32_r = __builtin_mips_cmpgu_eq_qb(v4i8_a, v4i8_b); |
| 175 | i32_r = __builtin_mips_cmpgu_lt_qb(v4i8_a, v4i8_b); |
| 176 | i32_r = __builtin_mips_cmpgu_le_qb(v4i8_a, v4i8_b); |
| 177 | v2q15_a = (v2q15) {0x1111, 0x1234}; |
| 178 | v2q15_b = (v2q15) {0x4444, 0x1234}; |
| 179 | __builtin_mips_cmp_eq_ph(v2q15_a, v2q15_b); |
| 180 | __builtin_mips_cmp_lt_ph(v2q15_a, v2q15_b); |
| 181 | __builtin_mips_cmp_le_ph(v2q15_a, v2q15_b); |
| 182 | |
| 183 | a64_a = 0xFFFFF81230000000LL; |
| 184 | i32_r = __builtin_mips_extr_s_h(a64_a, 4); |
| 185 | a64_a = 0x8123456712345678LL; |
| 186 | i32_r = __builtin_mips_extr_w(a64_a, 31); |
| 187 | i32_r = __builtin_mips_extr_rs_w(a64_a, 31); |
| 188 | i32_r = __builtin_mips_extr_r_w(a64_a, 31); |
| 189 | a64_a = 0x1234567887654321LL; |
| 190 | i32_r = __builtin_mips_extp(a64_a, 3); |
| 191 | a64_a = 0x123456789ABCDEF0LL; |
| 192 | i32_r = __builtin_mips_extpdp(a64_a, 7); |
| 193 | |
| 194 | __builtin_mips_wrdsp(2052, 3); |
| 195 | i32_r = __builtin_mips_rddsp(3); |
| 196 | i32_a = 0xFFFFFFFF; |
| 197 | i32_b = 0x12345678; |
| 198 | __builtin_mips_wrdsp((16<<7) + 4, 3); |
| 199 | i32_r = __builtin_mips_insv(i32_a, i32_b); |
| 200 | i32_a = 0x1234; |
| 201 | i32_r = __builtin_mips_bitrev(i32_a); |
| 202 | v2q15_a = (v2q15) {0x1111, 0x2222}; |
| 203 | v2q15_b = (v2q15) {0x3333, 0x4444}; |
| 204 | v2q15_r = __builtin_mips_packrl_ph(v2q15_a, v2q15_b); |
| 205 | i32_a = 100; |
| 206 | v4i8_r = __builtin_mips_repl_qb(i32_a); |
| 207 | i32_a = 0x1234; |
| 208 | v2q15_r = __builtin_mips_repl_ph(i32_a); |
| 209 | v4i8_a = (v4i8) {1, 4, 10, 8}; |
| 210 | v4i8_b = (v4i8) {1, 2, 100, 8}; |
| 211 | __builtin_mips_cmpu_eq_qb(v4i8_a, v4i8_b); |
| 212 | v4i8_r = __builtin_mips_pick_qb(v4i8_a, v4i8_b); |
| 213 | v2q15_a = (v2q15) {0x1111, 0x1234}; |
| 214 | v2q15_b = (v2q15) {0x4444, 0x1234}; |
| 215 | __builtin_mips_cmp_eq_ph(v2q15_a, v2q15_b); |
| 216 | v2q15_r = __builtin_mips_pick_ph(v2q15_a, v2q15_b); |
| 217 | a64_a = 0x1234567887654321LL; |
| 218 | i32_b = 0x11112222; |
| 219 | __builtin_mips_wrdsp(0, 1); |
| 220 | a64_r = __builtin_mips_mthlip(a64_a, i32_b); |
| 221 | i32_r = __builtin_mips_bposge32(); |
| 222 | char array_a[100]; |
| 223 | i32_r = __builtin_mips_lbux(array_a, 20); |
| 224 | short array_b[100]; |
| 225 | i32_r = __builtin_mips_lhx(array_b, 20); |
| 226 | int array_c[100]; |
| 227 | i32_r = __builtin_mips_lwx(array_c, 20); |
| 228 | } |