add conversion functions and test cases for ARM
git-svn-id: https://llvm.org/svn/llvm-project/compiler-rt/trunk@81809 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/arm/extendsfdf2vfp.S b/lib/arm/extendsfdf2vfp.S
new file mode 100644
index 0000000..024bbf0
--- /dev/null
+++ b/lib/arm/extendsfdf2vfp.S
@@ -0,0 +1,23 @@
+//===-- extendsfdf2vfp.S - Implement extendsfdf2vfp -----------------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+
+//
+// extern double __extendsfdf2vfp(float a);
+//
+// Converts single precision float to double precision result.
+// Uses Darwin calling convention where a single precision parameter is
+// passed in a GPR and a double precision result is returned in R0/R1 pair.
+//
+ .globl ___extendsfdf2vfp
+___extendsfdf2vfp:
+ fmsr s15, r0 // load float register from R0
+ fcvtds d7, s15 // convert single to double
+ fmrrd r0, r1, d7 // return result in r0/r1 pair
+ bx lr
diff --git a/lib/arm/fixdfsivfp.S b/lib/arm/fixdfsivfp.S
new file mode 100644
index 0000000..75c322d
--- /dev/null
+++ b/lib/arm/fixdfsivfp.S
@@ -0,0 +1,23 @@
+//===-- fixdfsivfp.S - Implement fixdfsivfp -----------------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+
+//
+// extern int __fixdfsivfp(double a);
+//
+// Converts double precision float to a 32-bit int rounding towards zero.
+// Uses Darwin calling convention where a double precision parameter is
+// passed in GPR register pair.
+//
+ .globl ___fixdfsivfp
+___fixdfsivfp:
+ fmdrr d7, r0, r1 // load double register from R0/R1
+ ftosizd s15, d7 // convert double to 32-bit int into s15
+ fmrs r0, s15 // move s15 to result register
+ bx lr
diff --git a/lib/arm/fixsfsivfp.S b/lib/arm/fixsfsivfp.S
new file mode 100644
index 0000000..cd2fbe8
--- /dev/null
+++ b/lib/arm/fixsfsivfp.S
@@ -0,0 +1,23 @@
+//===-- fixsfsivfp.S - Implement fixsfsivfp -----------------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+
+//
+// extern int __fixsfsivfp(float a);
+//
+// Converts single precision float to a 32-bit int rounding towards zero.
+// Uses Darwin calling convention where a single precision parameter is
+// passed in a GPR..
+//
+ .globl ___fixsfsivfp
+___fixsfsivfp:
+ fmsr s15, r0 // load float register from R0
+ ftosizs s15, s15 // convert single to 32-bit int into s15
+ fmrs r0, s15 // move s15 to result register
+ bx lr
diff --git a/lib/arm/fixunsdfsivfp.S b/lib/arm/fixunsdfsivfp.S
new file mode 100644
index 0000000..ab6c4df
--- /dev/null
+++ b/lib/arm/fixunsdfsivfp.S
@@ -0,0 +1,24 @@
+//===-- fixunsdfsivfp.S - Implement fixunsdfsivfp -------------------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+
+//
+// extern unsigned int __fixunsdfsivfp(double a);
+//
+// Converts double precision float to a 32-bit unsigned int rounding towards
+// zero. All negative values become zero.
+// Uses Darwin calling convention where a double precision parameter is
+// passed in GPR register pair.
+//
+ .globl ___fixunsdfsivfp
+___fixunsdfsivfp:
+ fmdrr d7, r0, r1 // load double register from R0/R1
+ ftouizd s15, d7 // convert double to 32-bit int into s15
+ fmrs r0, s15 // move s15 to result register
+ bx lr
diff --git a/lib/arm/fixunssfsivfp.S b/lib/arm/fixunssfsivfp.S
new file mode 100644
index 0000000..c39c698
--- /dev/null
+++ b/lib/arm/fixunssfsivfp.S
@@ -0,0 +1,24 @@
+//===-- fixunssfsivfp.S - Implement fixunssfsivfp -------------------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+
+//
+// extern unsigned int __fixunssfsivfp(float a);
+//
+// Converts single precision float to a 32-bit unsigned int rounding towards
+// zero. All negative values become zero.
+// Uses Darwin calling convention where a single precision parameter is
+// passed in a GPR..
+//
+ .globl ___fixunssfsivfp
+___fixunssfsivfp:
+ fmsr s15, r0 // load float register from R0
+ ftouizs s15, s15 // convert single to 32-bit unsigned into s15
+ fmrs r0, s15 // move s15 to result register
+ bx lr
diff --git a/lib/arm/floatsidfvfp.S b/lib/arm/floatsidfvfp.S
new file mode 100644
index 0000000..d402924
--- /dev/null
+++ b/lib/arm/floatsidfvfp.S
@@ -0,0 +1,23 @@
+//===-- floatsidfvfp.S - Implement floatsidfvfp ---------------------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+
+//
+// extern double __floatsidfvfp(int a);
+//
+// Converts a 32-bit int to a double precision float.
+// Uses Darwin calling convention where a double precision result is
+// return in GPR register pair.
+//
+ .globl ___floatsidfvfp
+___floatsidfvfp:
+ fmsr s15, r0 // move int to float register s15
+ fsitod d7, s15 // convert 32-bit int in s15 to double in d7
+ fmrrd r0, r1, d7 // move d7 to result register pair r0/r1
+ bx lr
diff --git a/lib/arm/floatsisfvfp.S b/lib/arm/floatsisfvfp.S
new file mode 100644
index 0000000..29e7e0d
--- /dev/null
+++ b/lib/arm/floatsisfvfp.S
@@ -0,0 +1,23 @@
+//===-- floatsisfvfp.S - Implement floatsisfvfp ---------------------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+
+//
+// extern float __floatsisfvfp(int a);
+//
+// Converts single precision float to a 32-bit int rounding towards zero.
+// Uses Darwin calling convention where a single precision result is
+// return in a GPR..
+//
+ .globl ___floatsisfvfp
+___floatsisfvfp:
+ fmsr s15, r0 // move int to float register s15
+ fsitos s15, s15 // convert 32-bit int in s15 to float in s15
+ fmrs r0, s15 // move s15 to result register
+ bx lr
diff --git a/lib/arm/floatunssidfvfp.S b/lib/arm/floatunssidfvfp.S
new file mode 100644
index 0000000..148945f
--- /dev/null
+++ b/lib/arm/floatunssidfvfp.S
@@ -0,0 +1,23 @@
+//===-- floatunssidfvfp.S - Implement floatunssidfvfp ---------------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+
+//
+// extern double __floatunssidfvfp(unsigned int a);
+//
+// Converts a 32-bit int to a double precision float.
+// Uses Darwin calling convention where a double precision result is
+// return in GPR register pair.
+//
+ .globl ___floatunssidfvfp
+___floatunssidfvfp:
+ fmsr s15, r0 // move int to float register s15
+ fuitod d7, s15 // convert 32-bit int in s15 to double in d7
+ fmrrd r0, r1, d7 // move d7 to result register pair r0/r1
+ bx lr
diff --git a/lib/arm/floatunssisfvfp.S b/lib/arm/floatunssisfvfp.S
new file mode 100644
index 0000000..c832278
--- /dev/null
+++ b/lib/arm/floatunssisfvfp.S
@@ -0,0 +1,23 @@
+//===-- floatunssisfvfp.S - Implement floatunssisfvfp ---------------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+
+//
+// extern float __floatunssisfvfp(unsigned int a);
+//
+// Converts single precision float to a 32-bit int rounding towards zero.
+// Uses Darwin calling convention where a single precision result is
+// return in a GPR..
+//
+ .globl ___floatunssisfvfp
+___floatunssisfvfp:
+ fmsr s15, r0 // move int to float register s15
+ fuitos s15, s15 // convert 32-bit int in s15 to float in s15
+ fmrs r0, s15 // move s15 to result register
+ bx lr
diff --git a/lib/arm/truncdfsf2vfp.S b/lib/arm/truncdfsf2vfp.S
new file mode 100644
index 0000000..2e26fdc
--- /dev/null
+++ b/lib/arm/truncdfsf2vfp.S
@@ -0,0 +1,23 @@
+//===-- truncdfsf2vfp.S - Implement truncdfsf2vfp -------------------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+
+//
+// extern float __truncdfsf2vfp(double a);
+//
+// Converts double precision float to signle precision result.
+// Uses Darwin calling convention where a double precision parameter is
+// passed in a R0/R1 pair and a signle precision result is returned in R0.
+//
+ .globl ___truncdfsf2vfp
+___truncdfsf2vfp:
+ fmdrr d7, r0, r1 // load double from r0/r1 pair
+ fcvtsd s15, d7 // convert double to single (trucate precision)
+ fmrs r0, s15 // return result in r0
+ bx lr