commit bab2a0caa65d114ab1dfc9314636c8057de285c7
author Sean Callanan <scallanan@apple.com> Fri Dec 21 22:27:55 2012 +0000
committer Sean Callanan <scallanan@apple.com> Fri Dec 21 22:27:55 2012 +0000
tree 3014c24ccf9ede840ddf39b93433b451a31fd27d
parent aa93c931a4c1275b2fecec23ef34f231afda4773

Added support for the modulus operator (%) to
the IR interpreter.

<rdar://problem/12921700>


git-svn-id: https://llvm.org/svn/llvm-project/lldb/trunk@170934 91177308-0d34-0410-b5e6-96231b3b80d8

source/Expression/IRInterpreter.cpp

diff --git a/source/Expression/IRInterpreter.cpp b/source/Expression/IRInterpreter.cpp
index 626e270..5fddc5c 100644
--- a/source/Expression/IRInterpreter.cpp
+++ b/source/Expression/IRInterpreter.cpp
@@ -1048,9 +1048,11 @@
             case Instruction::Mul:
             case Instruction::Ret:
             case Instruction::SDiv:
+            case Instruction::SRem:
             case Instruction::Store:
             case Instruction::Sub:
             case Instruction::UDiv:
+            case Instruction::URem:
             case Instruction::ZExt:
                 break;
             }
@@ -1135,6 +1137,8 @@
         case Instruction::Mul:
         case Instruction::SDiv:
         case Instruction::UDiv:
+        case Instruction::SRem:
+        case Instruction::URem:
             {
                 const BinaryOperator *bin_op = dyn_cast<BinaryOperator>(inst);
                 
@@ -1192,6 +1196,12 @@
                 case Instruction::UDiv:
                     result = L.GetRawBits64(0) / R.GetRawBits64(1);
                     break;
+                case Instruction::SRem:
+                    result = L % R;
+                    break;
+                case Instruction::URem:
+                    result = L.GetRawBits64(0) % R.GetRawBits64(1);
+                    break;
                 }
                                 
                 frame.AssignValue(inst, result, llvm_module);