Eliminate all remaining tabs and trailing spaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22523 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/Sparc/FPMover.cpp b/lib/Target/Sparc/FPMover.cpp
index 27be440..44cdef4 100644
--- a/lib/Target/Sparc/FPMover.cpp
+++ b/lib/Target/Sparc/FPMover.cpp
@@ -53,19 +53,19 @@
return new FPMover (tm);
}
-static void doubleToSingleRegPair(unsigned doubleReg, unsigned &singleReg1,
+static void doubleToSingleRegPair(unsigned doubleReg, unsigned &singleReg1,
unsigned &singleReg2) {
- const unsigned EvenHalvesOfPairs[] = {
- V8::F0, V8::F2, V8::F4, V8::F6, V8::F8, V8::F10, V8::F12, V8::F14,
- V8::F16, V8::F18, V8::F20, V8::F22, V8::F24, V8::F26, V8::F28, V8::F30
+ const unsigned EvenHalvesOfPairs[] = {
+ V8::F0, V8::F2, V8::F4, V8::F6, V8::F8, V8::F10, V8::F12, V8::F14,
+ V8::F16, V8::F18, V8::F20, V8::F22, V8::F24, V8::F26, V8::F28, V8::F30
};
- const unsigned OddHalvesOfPairs[] = {
- V8::F1, V8::F3, V8::F5, V8::F7, V8::F9, V8::F11, V8::F13, V8::F15,
- V8::F17, V8::F19, V8::F21, V8::F23, V8::F25, V8::F27, V8::F29, V8::F31
+ const unsigned OddHalvesOfPairs[] = {
+ V8::F1, V8::F3, V8::F5, V8::F7, V8::F9, V8::F11, V8::F13, V8::F15,
+ V8::F17, V8::F19, V8::F21, V8::F23, V8::F25, V8::F27, V8::F29, V8::F31
};
- const unsigned DoubleRegsInOrder[] = {
- V8::D0, V8::D1, V8::D2, V8::D3, V8::D4, V8::D5, V8::D6, V8::D7, V8::D8,
- V8::D9, V8::D10, V8::D11, V8::D12, V8::D13, V8::D14, V8::D15
+ const unsigned DoubleRegsInOrder[] = {
+ V8::D0, V8::D1, V8::D2, V8::D3, V8::D4, V8::D5, V8::D6, V8::D7, V8::D8,
+ V8::D9, V8::D10, V8::D11, V8::D12, V8::D13, V8::D14, V8::D15
};
for (unsigned i = 0; i < sizeof(DoubleRegsInOrder)/sizeof(unsigned); ++i)
if (DoubleRegsInOrder[i] == doubleReg) {
diff --git a/lib/Target/Sparc/SparcV8ISelPattern.cpp b/lib/Target/Sparc/SparcV8ISelPattern.cpp
index e557afc..346f058 100644
--- a/lib/Target/Sparc/SparcV8ISelPattern.cpp
+++ b/lib/Target/Sparc/SparcV8ISelPattern.cpp
@@ -119,7 +119,7 @@
std::vector<SDOperand>
V8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
{
- static const unsigned IncomingArgRegs[] =
+ static const unsigned IncomingArgRegs[] =
{ V8::I0, V8::I1, V8::I2, V8::I3, V8::I4, V8::I5 };
std::vector<SDOperand> ArgValues;
@@ -154,8 +154,8 @@
case MVT::i8:
case MVT::i16:
case MVT::i32:
- argt = DAG.getCopyFromReg(AddLiveIn(MF, IncomingArgRegs[ArgNo],
- getRegClassFor(MVT::i32)),
+ argt = DAG.getCopyFromReg(AddLiveIn(MF, IncomingArgRegs[ArgNo],
+ getRegClassFor(MVT::i32)),
VT, DAG.getRoot());
if (VT != MVT::i32)
argt = DAG.getNode(ISD::TRUNCATE, VT, argt);
@@ -198,7 +198,7 @@
V8TargetLowering::LowerCallTo(SDOperand Chain,
const Type *RetTy, bool isVarArg,
unsigned CallingConv, bool isTailCall,
- SDOperand Callee, ArgListTy &Args,
+ SDOperand Callee, ArgListTy &Args,
SelectionDAG &DAG) {
//FIXME
return std::make_pair(Chain, Chain);
@@ -243,7 +243,7 @@
// Clear state used for selection.
ExprMap.clear();
}
-
+
virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF);
unsigned SelectExpr(SDOperand N);
@@ -347,7 +347,7 @@
case MVT::f64: Opc = V8::LDFSRrr;
case MVT::f32: Opc = V8::LDDFrr;
default:
- Node->dump();
+ Node->dump();
assert(0 && "Bad type!");
break;
}
@@ -374,7 +374,7 @@
SDOperand Chain = N.getOperand(0);
Select(Chain);
unsigned r = dyn_cast<RegSDNode>(Node)->getReg();
-
+
BuildMI(BB, V8::ORrr, 2, Result).addReg(r).addReg(V8::G0);
return Result;
}
@@ -411,7 +411,7 @@
Tmp2 = SelectExpr(N.getOperand(1));
BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
return Result;
-
+
}
return 0;
}
@@ -488,7 +488,7 @@
Tmp1 = SelectExpr(Value);
Tmp2 = SelectExpr(Address);
- unsigned VT = opcode == ISD::STORE ?
+ unsigned VT = opcode == ISD::STORE ?
Value.getValueType() : cast<VTSDNode>(Node->getOperand(4))->getVT();
switch(VT) {
default: assert(0 && "unknown Type in store");