Before implementing copyfromreg, we'll implement copytoreg correctly.
This gets us this for the previous testcase:
_test:
lis r2, 0
ori r3, r2, 65535
blr
Note that we actually write to r3 (the return reg) correctly now :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22933 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
index 87943f9..d77578e 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
@@ -36,14 +36,16 @@
MachineBasicBlock *BB;
const TargetMachine &TM;
const TargetInstrInfo &TII;
+ const MRegisterInfo &MRI;
SSARegMap *RegMap;
std::map<SDNode *, unsigned> EmittedOps;
public:
SimpleSched(SelectionDAG &D, MachineBasicBlock *bb)
: DAG(D), BB(bb), TM(D.getTarget()), TII(*TM.getInstrInfo()),
- RegMap(BB->getParent()->getSSARegMap()) {
+ MRI(*TM.getRegisterInfo()), RegMap(BB->getParent()->getSSARegMap()) {
assert(&TII && "Target doesn't provide instr info?");
+ assert(&MRI && "Target doesn't provide register info?");
}
void Run() {
@@ -131,7 +133,9 @@
case ISD::EntryToken: break;
case ISD::CopyToReg: {
unsigned Val = Emit(Op.getOperand(2));
- // FIXME: DO THE COPY NOW.
+ MRI.copyRegToReg(*BB, BB->end(),
+ cast<RegisterSDNode>(Op.getOperand(1))->getReg(), Val,
+ RegMap->getRegClass(Val));
break;
}
}