Changes per review of commit 159787
Mips specific inline asm operand modifier D.
Comment changes and predicate change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159802 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/Mips/MipsAsmPrinter.cpp b/lib/Target/Mips/MipsAsmPrinter.cpp
index 3be0b28..fc47ba5 100644
--- a/lib/Target/Mips/MipsAsmPrinter.cpp
+++ b/lib/Target/Mips/MipsAsmPrinter.cpp
@@ -333,7 +333,6 @@
O << "$0";
return false;
}
- // This will be shared with other cases in succeeding checkins
case 'D': {
// Second part of a double word register operand
if (OpNum == 0)
@@ -343,9 +342,10 @@
return true;
unsigned Flags = FlagsOP.getImm();
unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
+ // Number of registers represented by this operand. We are looking
+ // for 2 for 32 bit mode and 1 for 64 bit mode.
if (NumVals != 2) {
- if (!Subtarget->isGP32bit() && NumVals == 1 && MO.isReg()) {
- // In 64 bit mode long longs are always just a single reg
+ if (Subtarget->isGP64bit() && NumVals == 1 && MO.isReg()) {
unsigned Reg = MO.getReg();
O << '$' << MipsInstPrinter::getRegisterName(Reg);
return false;
@@ -354,7 +354,6 @@
}
unsigned RegOp;
switch(ExtraCode[0]) {
- // This will have other cases in succeeding checkins
case 'D':
RegOp = (!Subtarget->isGP32bit()) ? OpNum : OpNum + 1;
break;
@@ -368,8 +367,8 @@
O << '$' << MipsInstPrinter::getRegisterName(Reg);
return false;
}
- } // switch
- } // if ExtraCode
+ }
+ }
printOperand(MI, OpNum, O);
return false;