diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index e70bb0b..14c4526 100644
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -131,10 +131,10 @@
   computeRegisterProperties();
 
   // ARM does not have f32 extending load.
-  setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
+  setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
 
   // ARM does not have i1 sign extending load.
-  setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
+  setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
 
   // ARM supports all 4 flavors of integer indexed load / store.
   for (unsigned im = (unsigned)ISD::PRE_INC;
diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp
index 8ec3fb5..33445f0 100644
--- a/lib/Target/Alpha/AlphaISelLowering.cpp
+++ b/lib/Target/Alpha/AlphaISelLowering.cpp
@@ -52,15 +52,15 @@
   // We want to custom lower some of our intrinsics.
   setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
 
-  setLoadXAction(ISD::EXTLOAD, MVT::i1,  Promote);
-  setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
+  setLoadExtAction(ISD::EXTLOAD, MVT::i1,  Promote);
+  setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
   
-  setLoadXAction(ISD::ZEXTLOAD, MVT::i1,  Promote);
-  setLoadXAction(ISD::ZEXTLOAD, MVT::i32, Expand);
+  setLoadExtAction(ISD::ZEXTLOAD, MVT::i1,  Promote);
+  setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Expand);
   
-  setLoadXAction(ISD::SEXTLOAD, MVT::i1,  Promote);
-  setLoadXAction(ISD::SEXTLOAD, MVT::i8,  Expand);
-  setLoadXAction(ISD::SEXTLOAD, MVT::i16, Expand);
+  setLoadExtAction(ISD::SEXTLOAD, MVT::i1,  Promote);
+  setLoadExtAction(ISD::SEXTLOAD, MVT::i8,  Expand);
+  setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
 
   //  setOperationAction(ISD::BRIND,        MVT::Other,   Expand);
   setOperationAction(ISD::BR_JT,        MVT::Other, Expand);
diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp
index 33cb9e6..086a25f 100644
--- a/lib/Target/CellSPU/SPUISelLowering.cpp
+++ b/lib/Target/CellSPU/SPUISelLowering.cpp
@@ -131,27 +131,27 @@
   addRegisterClass(MVT::i128, SPU::GPRCRegisterClass);
 
   // SPU has no sign or zero extended loads for i1, i8, i16:
-  setLoadXAction(ISD::EXTLOAD,  MVT::i1, Promote);
-  setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
-  setLoadXAction(ISD::ZEXTLOAD, MVT::i1, Promote);
+  setLoadExtAction(ISD::EXTLOAD,  MVT::i1, Promote);
+  setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
+  setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
   setTruncStoreAction(MVT::i8, MVT::i1, Custom);
   setTruncStoreAction(MVT::i16, MVT::i1, Custom);
   setTruncStoreAction(MVT::i32, MVT::i1, Custom);
   setTruncStoreAction(MVT::i64, MVT::i1, Custom);
   setTruncStoreAction(MVT::i128, MVT::i1, Custom);
 
-  setLoadXAction(ISD::EXTLOAD,  MVT::i8, Custom);
-  setLoadXAction(ISD::SEXTLOAD, MVT::i8, Custom);
-  setLoadXAction(ISD::ZEXTLOAD, MVT::i8, Custom);
+  setLoadExtAction(ISD::EXTLOAD,  MVT::i8, Custom);
+  setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Custom);
+  setLoadExtAction(ISD::ZEXTLOAD, MVT::i8, Custom);
   setTruncStoreAction(MVT::i8  , MVT::i8, Custom);
   setTruncStoreAction(MVT::i16 , MVT::i8, Custom);
   setTruncStoreAction(MVT::i32 , MVT::i8, Custom);
   setTruncStoreAction(MVT::i64 , MVT::i8, Custom);
   setTruncStoreAction(MVT::i128, MVT::i8, Custom);
 
-  setLoadXAction(ISD::EXTLOAD,  MVT::i16, Custom);
-  setLoadXAction(ISD::SEXTLOAD, MVT::i16, Custom);
-  setLoadXAction(ISD::ZEXTLOAD, MVT::i16, Custom);
+  setLoadExtAction(ISD::EXTLOAD,  MVT::i16, Custom);
+  setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Custom);
+  setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Custom);
 
   // SPU constant load actions are custom lowered:
   setOperationAction(ISD::Constant,   MVT::i64, Custom);
diff --git a/lib/Target/IA64/IA64ISelLowering.cpp b/lib/Target/IA64/IA64ISelLowering.cpp
index 3959dc6..1158271 100644
--- a/lib/Target/IA64/IA64ISelLowering.cpp
+++ b/lib/Target/IA64/IA64ISelLowering.cpp
@@ -35,14 +35,14 @@
   // register class for predicate registers
   addRegisterClass(MVT::i1, IA64::PRRegisterClass);
 
-  setLoadXAction(ISD::EXTLOAD          , MVT::i1   , Promote);
+  setLoadExtAction(ISD::EXTLOAD          , MVT::i1   , Promote);
 
-  setLoadXAction(ISD::ZEXTLOAD         , MVT::i1   , Promote);
+  setLoadExtAction(ISD::ZEXTLOAD         , MVT::i1   , Promote);
 
-  setLoadXAction(ISD::SEXTLOAD         , MVT::i1   , Promote);
-  setLoadXAction(ISD::SEXTLOAD         , MVT::i8   , Expand);
-  setLoadXAction(ISD::SEXTLOAD         , MVT::i16  , Expand);
-  setLoadXAction(ISD::SEXTLOAD         , MVT::i32  , Expand);
+  setLoadExtAction(ISD::SEXTLOAD         , MVT::i1   , Promote);
+  setLoadExtAction(ISD::SEXTLOAD         , MVT::i8   , Expand);
+  setLoadExtAction(ISD::SEXTLOAD         , MVT::i16  , Expand);
+  setLoadExtAction(ISD::SEXTLOAD         , MVT::i32  , Expand);
 
   setOperationAction(ISD::BRIND            , MVT::Other, Expand);
   setOperationAction(ISD::BR_JT            , MVT::Other, Expand);
diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp
index dd6b432..6dc237a 100644
--- a/lib/Target/Mips/MipsISelLowering.cpp
+++ b/lib/Target/Mips/MipsISelLowering.cpp
@@ -82,9 +82,9 @@
   addLegalFPImmediate(APFloat(+0.0f));
 
   // Load extented operations for i1 types must be promoted 
-  setLoadXAction(ISD::EXTLOAD,  MVT::i1,  Promote);
-  setLoadXAction(ISD::ZEXTLOAD, MVT::i1,  Promote);
-  setLoadXAction(ISD::SEXTLOAD, MVT::i1,  Promote);
+  setLoadExtAction(ISD::EXTLOAD,  MVT::i1,  Promote);
+  setLoadExtAction(ISD::ZEXTLOAD, MVT::i1,  Promote);
+  setLoadExtAction(ISD::SEXTLOAD, MVT::i1,  Promote);
 
   // Used by legalize types to correctly generate the setcc result. 
   // Without this, every float setcc comes with a AND/OR with the result, 
diff --git a/lib/Target/PIC16/PIC16ISelLowering.cpp b/lib/Target/PIC16/PIC16ISelLowering.cpp
index cdcc252..ace3170 100644
--- a/lib/Target/PIC16/PIC16ISelLowering.cpp
+++ b/lib/Target/PIC16/PIC16ISelLowering.cpp
@@ -60,9 +60,9 @@
   addRegisterClass(MVT::i16, PIC16::PTRRegsRegisterClass);
 
   // Load extented operations for i1 types must be promoted .
-  setLoadXAction(ISD::EXTLOAD, MVT::i1,  Promote);
-  setLoadXAction(ISD::ZEXTLOAD, MVT::i1,  Promote);
-  setLoadXAction(ISD::SEXTLOAD, MVT::i1,  Promote);
+  setLoadExtAction(ISD::EXTLOAD, MVT::i1,  Promote);
+  setLoadExtAction(ISD::ZEXTLOAD, MVT::i1,  Promote);
+  setLoadExtAction(ISD::SEXTLOAD, MVT::i1,  Promote);
 
   setOperationAction(ISD::ADD, MVT::i1, Promote);
   setOperationAction(ISD::ADD, MVT::i8, Legal);
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index 0cb77c0..553ca10 100644
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -53,8 +53,8 @@
   addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
   
   // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
-  setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
-  setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand);
+  setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
+  setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
 
   setTruncStoreAction(MVT::f64, MVT::f32, Expand);
     
diff --git a/lib/Target/Sparc/SparcISelLowering.cpp b/lib/Target/Sparc/SparcISelLowering.cpp
index dc35424..e81688e 100644
--- a/lib/Target/Sparc/SparcISelLowering.cpp
+++ b/lib/Target/Sparc/SparcISelLowering.cpp
@@ -515,9 +515,9 @@
   addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass);
 
   // Turn FP extload into load/fextend
-  setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
+  setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
   // Sparc doesn't have i1 sign extending load
-  setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
+  setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
   // Turn FP truncstore into trunc + store.
   setTruncStoreAction(MVT::f64, MVT::f32, Expand);
 
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 6d3d0b0..19b94df 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -84,7 +84,7 @@
   if (Subtarget->is64Bit())
     addRegisterClass(MVT::i64, X86::GR64RegisterClass);
 
-  setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
+  setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
 
   // We don't accept any truncstore of integer registers.  
   setTruncStoreAction(MVT::i64, MVT::i32, Expand);