commit 04677a3b49b2dfb151c4f77345702da489293627
author Evan Cheng <evan.cheng@apple.com> Mon Mar 19 06:20:37 2007 +0000
committer Evan Cheng <evan.cheng@apple.com> Mon Mar 19 06:20:37 2007 +0000
tree 7fc3345f8069c5424c70238a897a5c75691f3cdc
parent 5d5c93f659dd3f09375ea0fbe5d6c2df64791f73

Recognize target instruction flag 'isReMaterializable'.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35159 91177308-0d34-0410-b5e6-96231b3b80d8

utils/TableGen/CodeGenTarget.cpp

diff --git a/utils/TableGen/CodeGenTarget.cpp b/utils/TableGen/CodeGenTarget.cpp
index d29ce51..a261871 100644
--- a/utils/TableGen/CodeGenTarget.cpp
+++ b/utils/TableGen/CodeGenTarget.cpp
@@ -356,6 +356,7 @@
   isConvertibleToThreeAddress = R->getValueAsBit("isConvertibleToThreeAddress");
   isCommutable = R->getValueAsBit("isCommutable");
   isTerminator = R->getValueAsBit("isTerminator");
+  isReMaterializable = R->getValueAsBit("isReMaterializable");
   hasDelaySlot = R->getValueAsBit("hasDelaySlot");
   usesCustomDAGSchedInserter = R->getValueAsBit("usesCustomDAGSchedInserter");
   hasCtrlDep   = R->getValueAsBit("hasCtrlDep");