- Remove Tilmann's custom truncate lowering: it completely hosed over
DAGcombine's ability to find reasons to remove truncates when they were not
needed. Consequently, the CellSPU backend would produce correct, but _really
slow and horrible_, code.
Replaced with instruction sequences that do the equivalent truncation in
SPUInstrInfo.td.
- Re-examine how unaligned loads and stores work. Generated unaligned
load code has been tested on the CellSPU hardware; see the i32operations.c
and i64operations.c in CodeGen/CellSPU/useful-harnesses. (While they may be
toy test code, it does prove that some real world code does compile
correctly.)
- Fix truncating stores in bug 3193 (note: unpack_df.ll will still make llc
fault because i64 ult is not yet implemented.)
- Added i64 eq and neq for setcc and select/setcc; started new instruction
information file for them in SPU64InstrInfo.td. Additional i64 operations
should be added to this file and not to SPUInstrInfo.td.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61447 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/test/CodeGen/CellSPU/icmp64.ll b/test/CodeGen/CellSPU/icmp64.ll
new file mode 100644
index 0000000..d2b4fc0
--- /dev/null
+++ b/test/CodeGen/CellSPU/icmp64.ll
@@ -0,0 +1,144 @@
+; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
+; RUN: grep ceq %t1.s | count 4
+; RUN: grep cgti %t1.s | count 4
+; RUN: grep gb %t1.s | count 4
+; RUN: grep fsm %t1.s | count 2
+; RUN: grep xori %t1.s | count 1
+; RUN: grep selb %t1.s | count 2
+
+target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
+target triple = "spu"
+
+; $3 = %arg1, $4 = %arg2, $5 = %val1, $6 = %val2
+; $3 = %arg1, $4 = %val1, $5 = %val2
+;
+; i64 integer comparisons:
+define i64 @icmp_eq_select_i64(i64 %arg1, i64 %arg2, i64 %val1, i64 %val2) nounwind {
+entry:
+ %A = icmp eq i64 %arg1, %arg2
+ %B = select i1 %A, i64 %val1, i64 %val2
+ ret i64 %B
+}
+
+define i1 @icmp_eq_setcc_i64(i64 %arg1, i64 %arg2, i64 %val1, i64 %val2) nounwind {
+entry:
+ %A = icmp eq i64 %arg1, %arg2
+ ret i1 %A
+}
+
+define i64 @icmp_ne_select_i64(i64 %arg1, i64 %arg2, i64 %val1, i64 %val2) nounwind {
+entry:
+ %A = icmp ne i64 %arg1, %arg2
+ %B = select i1 %A, i64 %val1, i64 %val2
+ ret i64 %B
+}
+
+define i1 @icmp_ne_setcc_i64(i64 %arg1, i64 %arg2, i64 %val1, i64 %val2) nounwind {
+entry:
+ %A = icmp ne i64 %arg1, %arg2
+ ret i1 %A
+}
+
+;; define i64 @icmp_ugt_select_i64(i64 %arg1, i64 %arg2, i64 %val1, i64 %val2) nounwind {
+;; entry:
+;; %A = icmp ugt i64 %arg1, %arg2
+;; %B = select i1 %A, i64 %val1, i64 %val2
+;; ret i64 %B
+;; }
+;;
+;; define i1 @icmp_ugt_setcc_i64(i64 %arg1, i64 %arg2, i64 %val1, i64 %val2) nounwind {
+;; entry:
+;; %A = icmp ugt i64 %arg1, %arg2
+;; ret i1 %A
+;; }
+;;
+;; define i64 @icmp_uge_select_i64(i64 %arg1, i64 %arg2, i64 %val1, i64 %val2) nounwind {
+;; entry:
+;; %A = icmp uge i64 %arg1, %arg2
+;; %B = select i1 %A, i64 %val1, i64 %val2
+;; ret i64 %B
+;; }
+;;
+;; define i1 @icmp_uge_setcc_i64(i64 %arg1, i64 %arg2, i64 %val1, i64 %val2) nounwind {
+;; entry:
+;; %A = icmp uge i64 %arg1, %arg2
+;; ret i1 %A
+;; }
+;;
+;; define i64 @icmp_ult_select_i64(i64 %arg1, i64 %arg2, i64 %val1, i64 %val2) nounwind {
+;; entry:
+;; %A = icmp ult i64 %arg1, %arg2
+;; %B = select i1 %A, i64 %val1, i64 %val2
+;; ret i64 %B
+;; }
+;;
+;; define i1 @icmp_ult_setcc_i64(i64 %arg1, i64 %arg2, i64 %val1, i64 %val2) nounwind {
+;; entry:
+;; %A = icmp ult i64 %arg1, %arg2
+;; ret i1 %A
+;; }
+;;
+;; define i64 @icmp_ule_select_i64(i64 %arg1, i64 %arg2, i64 %val1, i64 %val2) nounwind {
+;; entry:
+;; %A = icmp ule i64 %arg1, %arg2
+;; %B = select i1 %A, i64 %val1, i64 %val2
+;; ret i64 %B
+;; }
+;;
+;; define i1 @icmp_ule_setcc_i64(i64 %arg1, i64 %arg2, i64 %val1, i64 %val2) nounwind {
+;; entry:
+;; %A = icmp ule i64 %arg1, %arg2
+;; ret i1 %A
+;; }
+;;
+;; define i64 @icmp_sgt_select_i64(i64 %arg1, i64 %arg2, i64 %val1, i64 %val2) nounwind {
+;; entry:
+;; %A = icmp sgt i64 %arg1, %arg2
+;; %B = select i1 %A, i64 %val1, i64 %val2
+;; ret i64 %B
+;; }
+;;
+;; define i1 @icmp_sgt_setcc_i64(i64 %arg1, i64 %arg2, i64 %val1, i64 %val2) nounwind {
+;; entry:
+;; %A = icmp sgt i64 %arg1, %arg2
+;; ret i1 %A
+;; }
+;;
+;; define i64 @icmp_sge_select_i64(i64 %arg1, i64 %arg2, i64 %val1, i64 %val2) nounwind {
+;; entry:
+;; %A = icmp sge i64 %arg1, %arg2
+;; %B = select i1 %A, i64 %val1, i64 %val2
+;; ret i64 %B
+;; }
+;;
+;; define i1 @icmp_sge_setcc_i64(i64 %arg1, i64 %arg2, i64 %val1, i64 %val2) nounwind {
+;; entry:
+;; %A = icmp sge i64 %arg1, %arg2
+;; ret i1 %A
+;; }
+;;
+;; define i64 @icmp_slt_select_i64(i64 %arg1, i64 %arg2, i64 %val1, i64 %val2) nounwind {
+;; entry:
+;; %A = icmp slt i64 %arg1, %arg2
+;; %B = select i1 %A, i64 %val1, i64 %val2
+;; ret i64 %B
+;; }
+;;
+;; define i1 @icmp_slt_setcc_i64(i64 %arg1, i64 %arg2, i64 %val1, i64 %val2) nounwind {
+;; entry:
+;; %A = icmp slt i64 %arg1, %arg2
+;; ret i1 %A
+;; }
+;;
+;; define i64 @icmp_sle_select_i64(i64 %arg1, i64 %arg2, i64 %val1, i64 %val2) nounwind {
+;; entry:
+;; %A = icmp sle i64 %arg1, %arg2
+;; %B = select i1 %A, i64 %val1, i64 %val2
+;; ret i64 %B
+;; }
+;;
+;; define i1 @icmp_sle_setcc_i64(i64 %arg1, i64 %arg2, i64 %val1, i64 %val2) nounwind {
+;; entry:
+;; %A = icmp sle i64 %arg1, %arg2
+;; ret i1 %A
+;; }