commit 06f554d06ab0f9390d04bcbaabb76f572d940249
author Craig Topper <craig.topper@gmail.com> Fri Dec 30 06:23:39 2011 +0000
committer Craig Topper <craig.topper@gmail.com> Fri Dec 30 06:23:39 2011 +0000
tree 57e6926f50790b141be81683d379a4429a7e64ae
parent e6a3a2990e3f783c906e9db58e55439cb06f9fa5

Add disassembler support for VPERMIL2PD and VPERMIL2PS.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147368 91177308-0d34-0410-b5e6-96231b3b80d8

utils/TableGen/X86RecognizableInstr.cpp

diff --git a/utils/TableGen/X86RecognizableInstr.cpp b/utils/TableGen/X86RecognizableInstr.cpp
index b8b282a..385e579 100644
--- a/utils/TableGen/X86RecognizableInstr.cpp
+++ b/utils/TableGen/X86RecognizableInstr.cpp
@@ -559,7 +559,7 @@
   
   bool hasFROperands = false;
   
-  assert(numOperands < X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
+  assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
   
   for (operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
     if (OperandList[operandIndex].Constraints.size()) {
@@ -678,7 +678,7 @@
     // Operand 3 (optional) is an immediate.
 
     if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
-      assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
+      assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
              "Unexpected number of operands for MRMSrcRegFrm with VEX_4V"); 
     else
       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
@@ -699,7 +699,9 @@
     if (HasVEX_4VOp3Prefix)
       HANDLE_OPERAND(vvvvRegister)
 
-    HANDLE_OPTIONAL(immediate)
+    if (!HasMemOp4Prefix)
+      HANDLE_OPTIONAL(immediate)
+    HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
     break;
   case X86Local::MRMSrcMem:
     // Operand 1 is a register operand in the Reg/Opcode field.
@@ -708,7 +710,7 @@
     // Operand 3 (optional) is an immediate.
 
     if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
-      assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
+      assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
              "Unexpected number of operands for MRMSrcMemFrm with VEX_4V"); 
     else
       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
@@ -729,7 +731,9 @@
     if (HasVEX_4VOp3Prefix)
       HANDLE_OPERAND(vvvvRegister)
 
-    HANDLE_OPTIONAL(immediate)
+    if (!HasMemOp4Prefix)
+      HANDLE_OPTIONAL(immediate)
+    HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
     break;
   case X86Local::MRM0r:
   case X86Local::MRM1r: