Remove Streams.h from the targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79853 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/CellSPU/SPUInstrInfo.cpp b/lib/Target/CellSPU/SPUInstrInfo.cpp
index 7e57e35..ecce8e3 100644
--- a/lib/Target/CellSPU/SPUInstrInfo.cpp
+++ b/lib/Target/CellSPU/SPUInstrInfo.cpp
@@ -17,9 +17,9 @@
#include "SPUTargetMachine.h"
#include "SPUGenInstrInfo.inc"
#include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/Support/Streams.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/raw_ostream.h"
using namespace llvm;
@@ -464,7 +464,7 @@
} else if (isCondBranch(LastInst)) {
// Block ends with fall-through condbranch.
TBB = LastInst->getOperand(1).getMBB();
- DEBUG(cerr << "Pushing LastInst: ");
+ DEBUG(errs() << "Pushing LastInst: ");
DEBUG(LastInst->dump());
Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
Cond.push_back(LastInst->getOperand(0));
@@ -485,7 +485,7 @@
// If the block ends with a conditional and unconditional branch, handle it.
if (isCondBranch(SecondLastInst) && isUncondBranch(LastInst)) {
TBB = SecondLastInst->getOperand(1).getMBB();
- DEBUG(cerr << "Pushing SecondLastInst: ");
+ DEBUG(errs() << "Pushing SecondLastInst: ");
DEBUG(SecondLastInst->dump());
Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
Cond.push_back(SecondLastInst->getOperand(0));
@@ -517,7 +517,7 @@
return 0;
// Remove the first branch.
- DEBUG(cerr << "Removing branch: ");
+ DEBUG(errs() << "Removing branch: ");
DEBUG(I->dump());
I->eraseFromParent();
I = MBB.end();
@@ -529,7 +529,7 @@
return 1;
// Remove the second branch.
- DEBUG(cerr << "Removing second branch: ");
+ DEBUG(errs() << "Removing second branch: ");
DEBUG(I->dump());
I->eraseFromParent();
return 2;
@@ -553,14 +553,14 @@
MachineInstrBuilder MIB = BuildMI(&MBB, dl, get(SPU::BR));
MIB.addMBB(TBB);
- DEBUG(cerr << "Inserted one-way uncond branch: ");
+ DEBUG(errs() << "Inserted one-way uncond branch: ");
DEBUG((*MIB).dump());
} else {
// Conditional branch
MachineInstrBuilder MIB = BuildMI(&MBB, dl, get(Cond[0].getImm()));
MIB.addReg(Cond[1].getReg()).addMBB(TBB);
- DEBUG(cerr << "Inserted one-way cond branch: ");
+ DEBUG(errs() << "Inserted one-way cond branch: ");
DEBUG((*MIB).dump());
}
return 1;
@@ -572,9 +572,9 @@
MIB.addReg(Cond[1].getReg()).addMBB(TBB);
MIB2.addMBB(FBB);
- DEBUG(cerr << "Inserted conditional branch: ");
+ DEBUG(errs() << "Inserted conditional branch: ");
DEBUG((*MIB).dump());
- DEBUG(cerr << "part 2: ");
+ DEBUG(errs() << "part 2: ");
DEBUG((*MIB2).dump());
return 2;
}