commit 07a73755d365af178050d3945c9c3dcdf2576ea0
author Nate Begeman <natebegeman@mac.com> Tue Aug 17 07:17:44 2004 +0000
committer Nate Begeman <natebegeman@mac.com> Tue Aug 17 07:17:44 2004 +0000
tree 6620bcd0c011ef28c80faab420dee6052d2ab543
parent 8581ee85b46bc5440a8aae53a0b752771f7b83f4

Re-fix hiding the Frame Pointer from the register allocator in functions
that have a frame pointer.  This change fixes Burg.  In addition, make
the necessary changes to floating point code gen and constant loading after
Chris Lattner's fixes to the asm writer.  These changes fix MallocBench/gs


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15873 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/PowerPC/PPC32ISelSimple.cpp

diff --git a/lib/Target/PowerPC/PPC32ISelSimple.cpp b/lib/Target/PowerPC/PPC32ISelSimple.cpp
index 50fd87b..d4d658b 100644
--- a/lib/Target/PowerPC/PPC32ISelSimple.cpp
+++ b/lib/Target/PowerPC/PPC32ISelSimple.cpp
@@ -618,13 +618,14 @@
     unsigned GlobalBase = makeAnotherReg(Type::IntTy);
     unsigned Reg1 = makeAnotherReg(Type::IntTy);
     unsigned Reg2 = makeAnotherReg(Type::IntTy);
+    unsigned Opcode = (Ty == Type::FloatTy) ? PPC::LFS : PPC::LFD;
     // Move value at base + distance into return reg
     copyGlobalBaseToRegister(MBB, IP, GlobalBase);
     BuildMI(*MBB, IP, PPC::LOADHiAddr, 2, Reg1).addReg(GlobalBase)
       .addConstantPoolIndex(CPI);
     BuildMI(*MBB, IP, PPC::LOADLoDirect, 2, Reg2).addReg(Reg1)
       .addConstantPoolIndex(CPI);
-    BuildMI(*MBB, IP, PPC::LFD, 2, R).addSImm(0).addReg(Reg2);
+    BuildMI(*MBB, IP, Opcode, 2, R).addSImm(0).addReg(Reg2);
   } else if (isa<ConstantPointerNull>(C)) {
     // Copy zero (null pointer) to the register.
     BuildMI(*MBB, IP, PPC::LI, 1, R).addSImm(0);
@@ -1824,16 +1825,10 @@
     const Type *Ty = Op1->getType();
     assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
 
-    unsigned Opcode = OpcodeTab[1][OperatorClass];
-    unsigned Op1Reg = getReg(Op1C, BB, IP);
+    unsigned Opcode = OpcodeTab[Ty == Type::DoubleTy][OperatorClass];
     unsigned Op0Reg = getReg(Op0, BB, IP);
-    if (Ty == Type::DoubleTy) {
-      BuildMI(*BB, IP, Opcode, 2, DestReg).addReg(Op0Reg).addReg(Op1Reg);
-    } else {
-      unsigned TmpReg = makeAnotherReg(Type::DoubleTy);
-      BuildMI(*BB, IP, Opcode, 2, TmpReg).addReg(Op0Reg).addReg(Op1Reg);
-      BuildMI(*BB, IP, PPC::FRSP, 1, DestReg).addReg(TmpReg);
-    }
+    unsigned Op1Reg = getReg(Op1C, BB, IP);
+    BuildMI(*BB, IP, Opcode, 2, DestReg).addReg(Op0Reg).addReg(Op1Reg);
     return;
   }
   
@@ -1851,21 +1846,14 @@
       const Type *Ty = Op0C->getType();
       assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
 
-      unsigned Opcode = OpcodeTab[1][OperatorClass];
+      unsigned Opcode = OpcodeTab[Ty == Type::DoubleTy][OperatorClass];
       unsigned Op0Reg = getReg(Op0C, BB, IP);
       unsigned Op1Reg = getReg(Op1, BB, IP);
-      if (Ty == Type::DoubleTy) {
-        BuildMI(*BB, IP, Opcode, 2, DestReg).addReg(Op0Reg).addReg(Op1Reg);
-      } else {
-        unsigned TmpReg = makeAnotherReg(Type::DoubleTy);
-        BuildMI(*BB, IP, Opcode, 2, TmpReg).addReg(Op0Reg).addReg(Op1Reg);
-        BuildMI(*BB, IP, PPC::FRSP, 1, DestReg).addReg(TmpReg);
-      }
+      BuildMI(*BB, IP, Opcode, 2, DestReg).addReg(Op0Reg).addReg(Op1Reg);
       return;
     }
 
   unsigned Opcode = OpcodeTab[Op0->getType() != Type::FloatTy][OperatorClass];
-  //unsigned Opcode = OpcodeTab[OperatorClass];
   unsigned Op0r = getReg(Op0, BB, IP);
   unsigned Op1r = getReg(Op1, BB, IP);
   BuildMI(*BB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);