Add ADD and SUB to the predicable ARM instructions.
It is not my plan to duplicate the entire ARM instruction set with
predicated versions. We need a way of representing predicated
instructions in SSA form without requiring a separate opcode.
Then the pseudo-instructions can go away.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162061 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/test/CodeGen/ARM/select.ll b/test/CodeGen/ARM/select.ll
index 418d4f3..5575566 100644
--- a/test/CodeGen/ARM/select.ll
+++ b/test/CodeGen/ARM/select.ll
@@ -76,12 +76,11 @@
; block generated, odds are good that we have close to the ideal code for this:
;
; CHECK-NEON: _f8:
+; CHECK-NEON: movw [[R3:r[0-9]+]], #1123
; CHECK-NEON: adr [[R2:r[0-9]+]], LCPI7_0
-; CHECK-NEON-NEXT: movw [[R3:r[0-9]+]], #1123
-; CHECK-NEON-NEXT: adds {{r.*}}, [[R2]], #4
; CHECK-NEON-NEXT: cmp r0, [[R3]]
-; CHECK-NEON-NEXT: it ne
-; CHECK-NEON-NEXT: movne {{r.*}}, [[R2]]
+; CHECK-NEON-NEXT: it eq
+; CHECK-NEON-NEXT: addeq.w {{r.*}}, [[R2]]
; CHECK-NEON-NEXT: ldr
; CHECK-NEON: bx