Replace the LiveRegs SmallSet with a simple counter that keeps
track of the number of live registers, which is all the set was
being used for.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56498 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
index 3b6daf4..ef7e143 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
@@ -39,7 +39,7 @@
/// all nodes to have the same priority.
///
struct VISIBILITY_HIDDEN FastPriorityQueue {
- std::vector<SUnit *> Queue;
+ SmallVector<SUnit *, 16> Queue;
bool empty() const { return Queue.empty(); }
@@ -63,10 +63,10 @@
/// AvailableQueue - The priority queue to use for the available SUnits.
FastPriorityQueue AvailableQueue;
- /// LiveRegs / LiveRegDefs - A set of physical registers and their definition
+ /// LiveRegDefs - A set of physical registers and their definition
/// that are "live". These nodes must be scheduled before any other nodes that
/// modifies the registers can be scheduled.
- SmallSet<unsigned, 4> LiveRegs;
+ unsigned NumLiveRegs;
std::vector<SUnit*> LiveRegDefs;
std::vector<unsigned> LiveRegCycles;
@@ -117,6 +117,7 @@
void ScheduleDAGFast::Schedule() {
DOUT << "********** List Scheduling **********\n";
+ NumLiveRegs = 0;
LiveRegDefs.resize(TRI->getNumRegs(), NULL);
LiveRegCycles.resize(TRI->getNumRegs(), 0);
@@ -178,7 +179,8 @@
// expensive to copy the register. Make sure nothing that can
// clobber the register is scheduled between the predecessor and
// this node.
- if (LiveRegs.insert(I->Reg)) {
+ if (!LiveRegDefs[I->Reg]) {
+ ++NumLiveRegs;
LiveRegDefs[I->Reg] = I->Dep;
LiveRegCycles[I->Reg] = CurCycle;
}
@@ -190,9 +192,10 @@
I != E; ++I) {
if (I->Cost < 0) {
if (LiveRegCycles[I->Reg] == I->Dep->Cycle) {
- LiveRegs.erase(I->Reg);
+ assert(NumLiveRegs > 0 && "NumLiveRegs is already zero!");
assert(LiveRegDefs[I->Reg] == SU &&
"Physical register dependency violated?");
+ --NumLiveRegs;
LiveRegDefs[I->Reg] = NULL;
LiveRegCycles[I->Reg] = 0;
}
@@ -460,7 +463,7 @@
/// whatever is necessary (i.e. backtracking or cloning) to make it possible.
bool ScheduleDAGFast::DelayForLiveRegsBottomUp(SUnit *SU,
SmallVector<unsigned, 4> &LRegs){
- if (LiveRegs.empty())
+ if (NumLiveRegs == 0)
return false;
SmallSet<unsigned, 4> RegAdded;
@@ -469,13 +472,13 @@
I != E; ++I) {
if (I->Cost < 0) {
unsigned Reg = I->Reg;
- if (LiveRegs.count(Reg) && LiveRegDefs[Reg] != I->Dep) {
+ if (LiveRegDefs[Reg] && LiveRegDefs[Reg] != I->Dep) {
if (RegAdded.insert(Reg))
LRegs.push_back(Reg);
}
for (const unsigned *Alias = TRI->getAliasSet(Reg);
*Alias; ++Alias)
- if (LiveRegs.count(*Alias) && LiveRegDefs[*Alias] != I->Dep) {
+ if (LiveRegDefs[*Alias] && LiveRegDefs[*Alias] != I->Dep) {
if (RegAdded.insert(*Alias))
LRegs.push_back(*Alias);
}
@@ -490,13 +493,13 @@
if (!TID.ImplicitDefs)
continue;
for (const unsigned *Reg = TID.ImplicitDefs; *Reg; ++Reg) {
- if (LiveRegs.count(*Reg) && LiveRegDefs[*Reg] != SU) {
+ if (LiveRegDefs[*Reg] && LiveRegDefs[*Reg] != SU) {
if (RegAdded.insert(*Reg))
LRegs.push_back(*Reg);
}
for (const unsigned *Alias = TRI->getAliasSet(*Reg);
*Alias; ++Alias)
- if (LiveRegs.count(*Alias) && LiveRegDefs[*Alias] != SU) {
+ if (LiveRegDefs[*Alias] && LiveRegDefs[*Alias] != SU) {
if (RegAdded.insert(*Alias))
LRegs.push_back(*Alias);
}