Restore the -post-RA-scheduler flag as an override for the target specification. Remove -mattr for setting PostRAScheduler enable and instead use CPU string.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83215 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARM.td b/lib/Target/ARM/ARM.td
index 4174899..8069e2b 100644
--- a/lib/Target/ARM/ARM.td
+++ b/lib/Target/ARM/ARM.td
@@ -43,9 +43,6 @@
def FeatureNEONFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
"true",
"Use NEON for single-precision FP">;
-def FeaturePostRASched : SubtargetFeature<"postrasched", "PostRAScheduler",
- "true",
- "Use Post-Register-Allocation Scheduler">;
//===----------------------------------------------------------------------===//
// ARM Processors supported.
@@ -108,8 +105,7 @@
// V7 Processors.
def : Processor<"cortex-a8", CortexA8Itineraries,
- [ArchV7A, FeatureThumb2, FeatureNEON, FeatureNEONFP,
- FeaturePostRASched]>;
+ [ArchV7A, FeatureThumb2, FeatureNEON, FeatureNEONFP]>;
def : ProcNoItin<"cortex-a9", [ArchV7A, FeatureThumb2, FeatureNEON]>;
//===----------------------------------------------------------------------===//
diff --git a/lib/Target/ARM/ARMSubtarget.cpp b/lib/Target/ARM/ARMSubtarget.cpp
index b46bd0c..704cf7a 100644
--- a/lib/Target/ARM/ARMSubtarget.cpp
+++ b/lib/Target/ARM/ARMSubtarget.cpp
@@ -93,6 +93,11 @@
if (isTargetDarwin())
IsR9Reserved = ReserveR9 | (ARMArchVersion < V6);
+
+ // Set CPU specific features.
+ if (CPUString == "cortex-a8") {
+ PostRAScheduler = true;
+ }
}
/// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.