Rename the new unsigned and signed keywords to nuw and nsw,
which stand for no-unsigned-wrap and no-signed-wrap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76810 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/docs/LangRef.html b/docs/LangRef.html
index bf98e04..57aace8 100644
--- a/docs/LangRef.html
+++ b/docs/LangRef.html
@@ -2601,9 +2601,9 @@
<h5>Syntax:</h5>
<pre>
<result> = add <ty> <op1>, <op2> <i>; yields {ty}:result</i>
- <result> = signed add <ty> <op1>, <op2> <i>; yields {ty}:result</i>
- <result> = unsigned add <ty> <op1>, <op2> <i>; yields {ty}:result</i>
- <result> = unsigned signed add <ty> <op1>, <op2> <i>; yields {ty}:result</i>
+ <result> = nuw add <ty> <op1>, <op2> <i>; yields {ty}:result</i>
+ <result> = nsw add <ty> <op1>, <op2> <i>; yields {ty}:result</i>
+ <result> = nuw nsw add <ty> <op1>, <op2> <i>; yields {ty}:result</i>
</pre>
<h5>Overview:</h5>
@@ -2623,9 +2623,10 @@
<p>Because LLVM integers use a two's complement representation, this instruction
is appropriate for both signed and unsigned integers.</p>
-<p>If the <tt>signed</tt> and/or <tt>unsigned</tt> keywords are present,
- the result value of the <tt>add</tt> is undefined if signed and/or unsigned
- overflow, respectively, occurs.</p>
+<p><tt>nuw</tt> and <tt>nsw</tt> stand for "No Unsigned Wrap"
+ and "No Signed Wrap", respectively. If the <tt>nuw</tt> and/or
+ <tt>nsw</tt> keywords are present, the result value of the <tt>add</tt>
+ is undefined if unsigned and/or signed overflow, respectively, occurs.</p>
<h5>Example:</h5>
<pre>
@@ -2673,10 +2674,10 @@
<h5>Syntax:</h5>
<pre>
- <result> = sub <ty> <op1>, <op2> <i>; yields {ty}:result</i>
- <result> = signed sub <ty> <op1>, <op2> <i>; yields {ty}:result</i>
- <result> = unsigned sub <ty> <op1>, <op2> <i>; yields {ty}:result</i>
- <result> = unsigned signed sub <ty> <op1>, <op2> <i>; yields {ty}:result</i>
+ <result> = sub <ty> <op1>, <op2> <i>; yields {ty}:result</i>
+ <result> = nuw sub <ty> <op1>, <op2> <i>; yields {ty}:result</i>
+ <result> = nsw sub <ty> <op1>, <op2> <i>; yields {ty}:result</i>
+ <result> = nuw nsw sub <ty> <op1>, <op2> <i>; yields {ty}:result</i>
</pre>
<h5>Overview:</h5>
@@ -2702,9 +2703,10 @@
<p>Because LLVM integers use a two's complement representation, this instruction
is appropriate for both signed and unsigned integers.</p>
-<p>If the <tt>signed</tt> and/or <tt>unsigned</tt> keywords are present,
- the result value of the <tt>sub</tt> is undefined if signed and/or unsigned
- overflow, respectively, occurs.</p>
+<p><tt>nuw</tt> and <tt>nsw</tt> stand for "No Unsigned Wrap"
+ and "No Signed Wrap", respectively. If the <tt>nuw</tt> and/or
+ <tt>nsw</tt> keywords are present, the result value of the <tt>sub</tt>
+ is undefined if unsigned and/or signed overflow, respectively, occurs.</p>
<h5>Example:</h5>
<pre>
@@ -2759,10 +2761,10 @@
<h5>Syntax:</h5>
<pre>
- <result> = mul <ty> <op1>, <op2> <i>; yields {ty}:result</i>
- <result> = signed mul <ty> <op1>, <op2> <i>; yields {ty}:result</i>
- <result> = unsigned mul <ty> <op1>, <op2> <i>; yields {ty}:result</i>
- <result> = unsigned signed mul <ty> <op1>, <op2> <i>; yields {ty}:result</i>
+ <result> = mul <ty> <op1>, <op2> <i>; yields {ty}:result</i>
+ <result> = nuw mul <ty> <op1>, <op2> <i>; yields {ty}:result</i>
+ <result> = nsw mul <ty> <op1>, <op2> <i>; yields {ty}:result</i>
+ <result> = nuw nsw mul <ty> <op1>, <op2> <i>; yields {ty}:result</i>
</pre>
<h5>Overview:</h5>
@@ -2787,9 +2789,10 @@
be sign-extended or zero-extended as appropriate to the width of the full
product.</p>
-<p>If the <tt>signed</tt> and/or <tt>unsigned</tt> keywords are present,
- the result value of the <tt>mul</tt> is undefined if signed and/or unsigned
- overflow, respectively, occurs.</p>
+<p><tt>nuw</tt> and <tt>nsw</tt> stand for "No Unsigned Wrap"
+ and "No Signed Wrap", respectively. If the <tt>nuw</tt> and/or
+ <tt>nsw</tt> keywords are present, the result value of the <tt>mul</tt>
+ is undefined if unsigned and/or signed overflow, respectively, occurs.</p>
<h5>Example:</h5>
<pre>
diff --git a/lib/AsmParser/LLLexer.cpp b/lib/AsmParser/LLLexer.cpp
index 313213c..e047002 100644
--- a/lib/AsmParser/LLLexer.cpp
+++ b/lib/AsmParser/LLLexer.cpp
@@ -501,8 +501,8 @@
KEYWORD(deplibs);
KEYWORD(datalayout);
KEYWORD(volatile);
- KEYWORD(signed);
- KEYWORD(unsigned);
+ KEYWORD(nuw);
+ KEYWORD(nsw);
KEYWORD(exact);
KEYWORD(align);
KEYWORD(addrspace);
diff --git a/lib/AsmParser/LLParser.cpp b/lib/AsmParser/LLParser.cpp
index 9f708a8..bb92b16 100644
--- a/lib/AsmParser/LLParser.cpp
+++ b/lib/AsmParser/LLParser.cpp
@@ -2045,26 +2045,9 @@
ID.Kind = ValID::t_Constant;
return false;
}
- case lltok::kw_signed: {
+ case lltok::kw_nuw: {
Lex.Lex();
- bool AlsoUnsigned = EatIfPresent(lltok::kw_unsigned);
- if (Lex.getKind() != lltok::kw_add &&
- Lex.getKind() != lltok::kw_sub &&
- Lex.getKind() != lltok::kw_mul)
- return TokError("expected 'add', 'sub', or 'mul'");
- bool Result = LLParser::ParseValID(ID);
- if (!Result) {
- cast<OverflowingBinaryOperator>(ID.ConstantVal)
- ->setHasNoSignedOverflow(true);
- if (AlsoUnsigned)
- cast<OverflowingBinaryOperator>(ID.ConstantVal)
- ->setHasNoUnsignedOverflow(true);
- }
- return Result;
- }
- case lltok::kw_unsigned: {
- Lex.Lex();
- bool AlsoSigned = EatIfPresent(lltok::kw_signed);
+ bool AlsoSigned = EatIfPresent(lltok::kw_nsw);
if (Lex.getKind() != lltok::kw_add &&
Lex.getKind() != lltok::kw_sub &&
Lex.getKind() != lltok::kw_mul)
@@ -2079,6 +2062,23 @@
}
return Result;
}
+ case lltok::kw_nsw: {
+ Lex.Lex();
+ bool AlsoUnsigned = EatIfPresent(lltok::kw_nuw);
+ if (Lex.getKind() != lltok::kw_add &&
+ Lex.getKind() != lltok::kw_sub &&
+ Lex.getKind() != lltok::kw_mul)
+ return TokError("expected 'add', 'sub', or 'mul'");
+ bool Result = LLParser::ParseValID(ID);
+ if (!Result) {
+ cast<OverflowingBinaryOperator>(ID.ConstantVal)
+ ->setHasNoSignedOverflow(true);
+ if (AlsoUnsigned)
+ cast<OverflowingBinaryOperator>(ID.ConstantVal)
+ ->setHasNoUnsignedOverflow(true);
+ }
+ return Result;
+ }
case lltok::kw_exact: {
Lex.Lex();
if (Lex.getKind() != lltok::kw_sdiv)
@@ -2609,8 +2609,8 @@
return ParseStore(Inst, PFS, true);
else
return TokError("expected 'load' or 'store'");
- case lltok::kw_signed: {
- bool AlsoUnsigned = EatIfPresent(lltok::kw_unsigned);
+ case lltok::kw_nuw: {
+ bool AlsoSigned = EatIfPresent(lltok::kw_nsw);
if (Lex.getKind() == lltok::kw_add ||
Lex.getKind() == lltok::kw_sub ||
Lex.getKind() == lltok::kw_mul) {
@@ -2618,16 +2618,16 @@
KeywordVal = Lex.getUIntVal();
bool Result = ParseArithmetic(Inst, PFS, KeywordVal, 0);
if (!Result) {
- cast<OverflowingBinaryOperator>(Inst)->setHasNoSignedOverflow(true);
- if (AlsoUnsigned)
- cast<OverflowingBinaryOperator>(Inst)->setHasNoUnsignedOverflow(true);
+ cast<OverflowingBinaryOperator>(Inst)->setHasNoUnsignedOverflow(true);
+ if (AlsoSigned)
+ cast<OverflowingBinaryOperator>(Inst)->setHasNoSignedOverflow(true);
}
return Result;
}
return TokError("expected 'add', 'sub', or 'mul'");
}
- case lltok::kw_unsigned: {
- bool AlsoSigned = EatIfPresent(lltok::kw_signed);
+ case lltok::kw_nsw: {
+ bool AlsoUnsigned = EatIfPresent(lltok::kw_nuw);
if (Lex.getKind() == lltok::kw_add ||
Lex.getKind() == lltok::kw_sub ||
Lex.getKind() == lltok::kw_mul) {
@@ -2635,9 +2635,9 @@
KeywordVal = Lex.getUIntVal();
bool Result = ParseArithmetic(Inst, PFS, KeywordVal, 1);
if (!Result) {
- cast<OverflowingBinaryOperator>(Inst)->setHasNoUnsignedOverflow(true);
- if (AlsoSigned)
- cast<OverflowingBinaryOperator>(Inst)->setHasNoSignedOverflow(true);
+ cast<OverflowingBinaryOperator>(Inst)->setHasNoSignedOverflow(true);
+ if (AlsoUnsigned)
+ cast<OverflowingBinaryOperator>(Inst)->setHasNoUnsignedOverflow(true);
}
return Result;
}
diff --git a/lib/AsmParser/LLToken.h b/lib/AsmParser/LLToken.h
index b78a09d..c8cdff6 100644
--- a/lib/AsmParser/LLToken.h
+++ b/lib/AsmParser/LLToken.h
@@ -51,8 +51,8 @@
kw_deplibs,
kw_datalayout,
kw_volatile,
- kw_signed,
- kw_unsigned,
+ kw_nuw,
+ kw_nsw,
kw_exact,
kw_align,
kw_addrspace,
diff --git a/lib/VMCore/AsmWriter.cpp b/lib/VMCore/AsmWriter.cpp
index 6e84af3..d9d8cc8 100644
--- a/lib/VMCore/AsmWriter.cpp
+++ b/lib/VMCore/AsmWriter.cpp
@@ -856,9 +856,9 @@
if (const OverflowingBinaryOperator *OBO =
dyn_cast<OverflowingBinaryOperator>(U)) {
if (OBO->hasNoUnsignedOverflow())
- Out << "unsigned ";
+ Out << "nuw ";
if (OBO->hasNoSignedOverflow())
- Out << "signed ";
+ Out << "nsw ";
} else if (const SDivOperator *Div = dyn_cast<SDivOperator>(U)) {
if (Div->isExact())
Out << "exact ";
diff --git a/test/Assembler/flags-reversed.ll b/test/Assembler/flags-reversed.ll
index b63ac84..d66095a 100644
--- a/test/Assembler/flags-reversed.ll
+++ b/test/Assembler/flags-reversed.ll
@@ -3,16 +3,16 @@
@addr = external global i64
define i64 @add_both_reversed_ce() {
-; CHECK: ret i64 unsigned signed add (i64 ptrtoint (i64* @addr to i64), i64 91)
- ret i64 signed unsigned add (i64 ptrtoint (i64* @addr to i64), i64 91)
+; CHECK: ret i64 nuw nsw add (i64 ptrtoint (i64* @addr to i64), i64 91)
+ ret i64 nsw nuw add (i64 ptrtoint (i64* @addr to i64), i64 91)
}
define i64 @sub_both_reversed_ce() {
-; CHECK: ret i64 unsigned signed sub (i64 ptrtoint (i64* @addr to i64), i64 91)
- ret i64 signed unsigned sub (i64 ptrtoint (i64* @addr to i64), i64 91)
+; CHECK: ret i64 nuw nsw sub (i64 ptrtoint (i64* @addr to i64), i64 91)
+ ret i64 nsw nuw sub (i64 ptrtoint (i64* @addr to i64), i64 91)
}
define i64 @mul_both_reversed_ce() {
-; CHECK: ret i64 unsigned signed mul (i64 ptrtoint (i64* @addr to i64), i64 91)
- ret i64 signed unsigned mul (i64 ptrtoint (i64* @addr to i64), i64 91)
+; CHECK: ret i64 nuw nsw mul (i64 ptrtoint (i64* @addr to i64), i64 91)
+ ret i64 nsw nuw mul (i64 ptrtoint (i64* @addr to i64), i64 91)
}
diff --git a/test/Assembler/flags-signed.ll b/test/Assembler/flags-signed.ll
index 136dd57..62c38a9 100644
--- a/test/Assembler/flags-signed.ll
+++ b/test/Assembler/flags-signed.ll
@@ -3,16 +3,16 @@
@addr = external global i64
define i64 @add_signed_ce() {
-; CHECK: ret i64 signed add (i64 ptrtoint (i64* @addr to i64), i64 91)
- ret i64 signed add (i64 ptrtoint (i64* @addr to i64), i64 91)
+; CHECK: ret i64 nsw add (i64 ptrtoint (i64* @addr to i64), i64 91)
+ ret i64 nsw add (i64 ptrtoint (i64* @addr to i64), i64 91)
}
define i64 @sub_signed_ce() {
-; CHECK: ret i64 signed sub (i64 ptrtoint (i64* @addr to i64), i64 91)
- ret i64 signed sub (i64 ptrtoint (i64* @addr to i64), i64 91)
+; CHECK: ret i64 nsw sub (i64 ptrtoint (i64* @addr to i64), i64 91)
+ ret i64 nsw sub (i64 ptrtoint (i64* @addr to i64), i64 91)
}
define i64 @mul_signed_ce() {
-; CHECK: ret i64 signed mul (i64 ptrtoint (i64* @addr to i64), i64 91)
- ret i64 signed mul (i64 ptrtoint (i64* @addr to i64), i64 91)
+; CHECK: ret i64 nsw mul (i64 ptrtoint (i64* @addr to i64), i64 91)
+ ret i64 nsw mul (i64 ptrtoint (i64* @addr to i64), i64 91)
}
diff --git a/test/Assembler/flags-unsigned.ll b/test/Assembler/flags-unsigned.ll
index 1526db0..cd051af 100644
--- a/test/Assembler/flags-unsigned.ll
+++ b/test/Assembler/flags-unsigned.ll
@@ -3,16 +3,16 @@
@addr = external global i64
define i64 @add_unsigned_ce() {
-; CHECK: ret i64 unsigned add (i64 ptrtoint (i64* @addr to i64), i64 91)
- ret i64 unsigned add (i64 ptrtoint (i64* @addr to i64), i64 91)
+; CHECK: ret i64 nuw add (i64 ptrtoint (i64* @addr to i64), i64 91)
+ ret i64 nuw add (i64 ptrtoint (i64* @addr to i64), i64 91)
}
define i64 @sub_unsigned_ce() {
-; CHECK: ret i64 unsigned sub (i64 ptrtoint (i64* @addr to i64), i64 91)
- ret i64 unsigned sub (i64 ptrtoint (i64* @addr to i64), i64 91)
+; CHECK: ret i64 nuw sub (i64 ptrtoint (i64* @addr to i64), i64 91)
+ ret i64 nuw sub (i64 ptrtoint (i64* @addr to i64), i64 91)
}
define i64 @mul_unsigned_ce() {
-; CHECK: ret i64 unsigned mul (i64 ptrtoint (i64* @addr to i64), i64 91)
- ret i64 unsigned mul (i64 ptrtoint (i64* @addr to i64), i64 91)
+; CHECK: ret i64 nuw mul (i64 ptrtoint (i64* @addr to i64), i64 91)
+ ret i64 nuw mul (i64 ptrtoint (i64* @addr to i64), i64 91)
}
diff --git a/test/Assembler/flags.ll b/test/Assembler/flags.ll
index 317bc0c..a0c2abc 100644
--- a/test/Assembler/flags.ll
+++ b/test/Assembler/flags.ll
@@ -2,39 +2,39 @@
@addr = external global i64
-define i64 @add_signed(i64 %x, i64 %y) {
-; CHECK: %z = signed add i64 %x, %y
- %z = signed add i64 %x, %y
- ret i64 %z
-}
-
-define i64 @sub_signed(i64 %x, i64 %y) {
-; CHECK: %z = signed sub i64 %x, %y
- %z = signed sub i64 %x, %y
- ret i64 %z
-}
-
-define i64 @mul_signed(i64 %x, i64 %y) {
-; CHECK: %z = signed mul i64 %x, %y
- %z = signed mul i64 %x, %y
- ret i64 %z
-}
-
define i64 @add_unsigned(i64 %x, i64 %y) {
-; CHECK: %z = unsigned add i64 %x, %y
- %z = unsigned add i64 %x, %y
+; CHECK: %z = nuw add i64 %x, %y
+ %z = nuw add i64 %x, %y
ret i64 %z
}
define i64 @sub_unsigned(i64 %x, i64 %y) {
-; CHECK: %z = unsigned sub i64 %x, %y
- %z = unsigned sub i64 %x, %y
+; CHECK: %z = nuw sub i64 %x, %y
+ %z = nuw sub i64 %x, %y
ret i64 %z
}
define i64 @mul_unsigned(i64 %x, i64 %y) {
-; CHECK: %z = unsigned mul i64 %x, %y
- %z = unsigned mul i64 %x, %y
+; CHECK: %z = nuw mul i64 %x, %y
+ %z = nuw mul i64 %x, %y
+ ret i64 %z
+}
+
+define i64 @add_signed(i64 %x, i64 %y) {
+; CHECK: %z = nsw add i64 %x, %y
+ %z = nsw add i64 %x, %y
+ ret i64 %z
+}
+
+define i64 @sub_signed(i64 %x, i64 %y) {
+; CHECK: %z = nsw sub i64 %x, %y
+ %z = nsw sub i64 %x, %y
+ ret i64 %z
+}
+
+define i64 @mul_signed(i64 %x, i64 %y) {
+; CHECK: %z = nsw mul i64 %x, %y
+ %z = nsw mul i64 %x, %y
ret i64 %z
}
@@ -57,38 +57,38 @@
}
define i64 @add_both(i64 %x, i64 %y) {
-; CHECK: %z = unsigned signed add i64 %x, %y
- %z = unsigned signed add i64 %x, %y
+; CHECK: %z = nuw nsw add i64 %x, %y
+ %z = nuw nsw add i64 %x, %y
ret i64 %z
}
define i64 @sub_both(i64 %x, i64 %y) {
-; CHECK: %z = unsigned signed sub i64 %x, %y
- %z = unsigned signed sub i64 %x, %y
+; CHECK: %z = nuw nsw sub i64 %x, %y
+ %z = nuw nsw sub i64 %x, %y
ret i64 %z
}
define i64 @mul_both(i64 %x, i64 %y) {
-; CHECK: %z = unsigned signed mul i64 %x, %y
- %z = unsigned signed mul i64 %x, %y
+; CHECK: %z = nuw nsw mul i64 %x, %y
+ %z = nuw nsw mul i64 %x, %y
ret i64 %z
}
define i64 @add_both_reversed(i64 %x, i64 %y) {
-; CHECK: %z = unsigned signed add i64 %x, %y
- %z = signed unsigned add i64 %x, %y
+; CHECK: %z = nuw nsw add i64 %x, %y
+ %z = nsw nuw add i64 %x, %y
ret i64 %z
}
define i64 @sub_both_reversed(i64 %x, i64 %y) {
-; CHECK: %z = unsigned signed sub i64 %x, %y
- %z = signed unsigned sub i64 %x, %y
+; CHECK: %z = nuw nsw sub i64 %x, %y
+ %z = nsw nuw sub i64 %x, %y
ret i64 %z
}
define i64 @mul_both_reversed(i64 %x, i64 %y) {
-; CHECK: %z = unsigned signed mul i64 %x, %y
- %z = signed unsigned mul i64 %x, %y
+; CHECK: %z = nuw nsw mul i64 %x, %y
+ %z = nsw nuw mul i64 %x, %y
ret i64 %z
}
@@ -105,18 +105,18 @@
}
define i64 @add_both_ce() {
-; CHECK: ret i64 unsigned signed add (i64 ptrtoint (i64* @addr to i64), i64 91)
- ret i64 signed unsigned add (i64 ptrtoint (i64* @addr to i64), i64 91)
+; CHECK: ret i64 nuw nsw add (i64 ptrtoint (i64* @addr to i64), i64 91)
+ ret i64 nsw nuw add (i64 ptrtoint (i64* @addr to i64), i64 91)
}
define i64 @sub_both_ce() {
-; CHECK: ret i64 unsigned signed sub (i64 ptrtoint (i64* @addr to i64), i64 91)
- ret i64 signed unsigned sub (i64 ptrtoint (i64* @addr to i64), i64 91)
+; CHECK: ret i64 nuw nsw sub (i64 ptrtoint (i64* @addr to i64), i64 91)
+ ret i64 nsw nuw sub (i64 ptrtoint (i64* @addr to i64), i64 91)
}
define i64 @mul_both_ce() {
-; CHECK: ret i64 unsigned signed mul (i64 ptrtoint (i64* @addr to i64), i64 91)
- ret i64 unsigned signed mul (i64 ptrtoint (i64* @addr to i64), i64 91)
+; CHECK: ret i64 nuw nsw mul (i64 ptrtoint (i64* @addr to i64), i64 91)
+ ret i64 nuw nsw mul (i64 ptrtoint (i64* @addr to i64), i64 91)
}
define i64 @sdiv_exact_ce() {