Add target independent MachineInstr's to represent subreg insert/extract in MBB's. PR1350
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40518 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/Target.td b/lib/Target/Target.td
index 1583a93..84f6227 100644
--- a/lib/Target/Target.td
+++ b/lib/Target/Target.td
@@ -321,6 +321,18 @@
let Namespace = "TargetInstrInfo";
let hasCtrlDep = 1;
}
+def EXTRACT_SUBREG : Instruction {
+ let OutOperandList = (ops variable_ops);
+ let InOperandList = (ops variable_ops);
+ let AsmString = "";
+ let Namespace = "TargetInstrInfo";
+}
+def INSERT_SUBREG : Instruction {
+ let OutOperandList = (ops variable_ops);
+ let InOperandList = (ops variable_ops);
+ let AsmString = "";
+ let Namespace = "TargetInstrInfo";
+}
//===----------------------------------------------------------------------===//
// AsmWriter - This class can be implemented by targets that need to customize