Re-apply 68552.
Tested by bootstrapping llvm-gcc and using that to build llvm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68645 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/X86/X86InstrInfo.h b/lib/Target/X86/X86InstrInfo.h
index 3bbb51e..e09769e 100644
--- a/lib/Target/X86/X86InstrInfo.h
+++ b/lib/Target/X86/X86InstrInfo.h
@@ -243,7 +243,7 @@
};
}
-const int X86AddrNumOperands = 4;
+const int X86AddrNumOperands = 5;
inline static bool isScale(const MachineOperand &MO) {
return MO.isImm() &&
@@ -251,7 +251,7 @@
MO.getImm() == 4 || MO.getImm() == 8);
}
-inline static bool isMem(const MachineInstr *MI, unsigned Op) {
+inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) {
if (MI->getOperand(Op).isFI()) return true;
return Op+4 <= MI->getNumOperands() &&
MI->getOperand(Op ).isReg() && isScale(MI->getOperand(Op+1)) &&
@@ -262,6 +262,13 @@
MI->getOperand(Op+3).isJTI());
}
+inline static bool isMem(const MachineInstr *MI, unsigned Op) {
+ if (MI->getOperand(Op).isFI()) return true;
+ return Op+5 <= MI->getNumOperands() &&
+ MI->getOperand(Op+4).isReg() &&
+ isLeaMem(MI, Op);
+}
+
class X86InstrInfo : public TargetInstrInfoImpl {
X86TargetMachine &TM;
const X86RegisterInfo RI;