Use predication instead of pseudo-opcodes when folding into MOVCC.
Now that it is possible to dynamically tie MachineInstr operands,
predicated instructions are possible in SSA form:
%vreg3<def> = SUBri %vreg1, -2147483647, pred:14, pred:%noreg, %opt:%noreg
%vreg4<def,tied1> = MOVCCr %vreg3<tied0>, %vreg1, %pred:12, pred:%CPSR
Becomes a predicated SUBri with a tied imp-use:
SUBri %vreg1, -2147483647, pred:13, pred:%CPSR, opt:%noreg, %vreg1<imp-use,tied0>
This means that any instruction that is safe to move can be folded into
a MOVCC, and the *CC pseudo-instructions are no longer needed.
The test case changes reflect that Thumb2SizeReduce recognizes the
predicated instructions. It didn't understand the pseudos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163274 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/test/CodeGen/ARM/select.ll b/test/CodeGen/ARM/select.ll
index 5575566..62708ed 100644
--- a/test/CodeGen/ARM/select.ll
+++ b/test/CodeGen/ARM/select.ll
@@ -80,7 +80,7 @@
; CHECK-NEON: adr [[R2:r[0-9]+]], LCPI7_0
; CHECK-NEON-NEXT: cmp r0, [[R3]]
; CHECK-NEON-NEXT: it eq
-; CHECK-NEON-NEXT: addeq.w {{r.*}}, [[R2]]
+; CHECK-NEON-NEXT: addeq{{.*}} [[R2]], #4
; CHECK-NEON-NEXT: ldr
; CHECK-NEON: bx
diff --git a/test/CodeGen/ARM/select_xform.ll b/test/CodeGen/ARM/select_xform.ll
index cfc0e70..7507808 100644
--- a/test/CodeGen/ARM/select_xform.ll
+++ b/test/CodeGen/ARM/select_xform.ll
@@ -9,7 +9,7 @@
; T2: t1:
; T2: mvn r0, #-2147483648
-; T2: addle.w r1, r1
+; T2: addle r1, r0
; T2: mov r0, r1
%tmp1 = icmp sgt i32 %c, 10
%tmp2 = select i1 %tmp1, i32 0, i32 2147483647
@@ -23,7 +23,7 @@
; ARM: mov r0, r1
; T2: t2:
-; T2: suble.w r1, r1, #10
+; T2: suble r1, #10
; T2: mov r0, r1
%tmp1 = icmp sgt i32 %c, 10
%tmp2 = select i1 %tmp1, i32 0, i32 10
@@ -37,7 +37,7 @@
; ARM: mov r0, r3
; T2: t3:
-; T2: andge.w r3, r3, r2
+; T2: andge r3, r2
; T2: mov r0, r3
%cond = icmp slt i32 %a, %b
%z = select i1 %cond, i32 -1, i32 %x
@@ -51,7 +51,7 @@
; ARM: mov r0, r3
; T2: t4:
-; T2: orrge.w r3, r3, r2
+; T2: orrge r3, r2
; T2: mov r0, r3
%cond = icmp slt i32 %a, %b
%z = select i1 %cond, i32 0, i32 %x
@@ -81,7 +81,7 @@
; T2: t6:
; T2-NOT: movge
-; T2: eorlt.w r3, r3, r2
+; T2: eorlt r3, r2
%cond = icmp slt i32 %a, %b
%tmp1 = select i1 %cond, i32 %c, i32 0
%tmp2 = xor i32 %tmp1, %d
@@ -200,7 +200,7 @@
; T2: t13
; T2: cmp r1, #10
-; T2: addgt.w r0, r0, #1
+; T2: addgt r0, #1
%cmp = icmp sgt i32 %a, 10
%conv = zext i1 %cmp to i32
%add = add i32 %conv, %c
@@ -216,7 +216,7 @@
; T2: t14
; T2: cmp r1, #10
-; T2: subgt.w r0, r0, #1
+; T2: subgt r0, #1
%cmp = icmp sgt i32 %a, 10
%conv = sext i1 %cmp to i32
%add = add i32 %conv, %c
diff --git a/test/CodeGen/Thumb2/thumb2-select_xform.ll b/test/CodeGen/Thumb2/thumb2-select_xform.ll
index ead198f..ed4d26d 100644
--- a/test/CodeGen/Thumb2/thumb2-select_xform.ll
+++ b/test/CodeGen/Thumb2/thumb2-select_xform.ll
@@ -5,7 +5,7 @@
; CHECK: mvn r0, #-2147483648
; CHECK: cmp r2, #10
; CHECK: it le
-; CHECK: addle.w r1, r1, r0
+; CHECK: addle r1, r0
; CHECK: mov r0, r1
%tmp1 = icmp sgt i32 %c, 10
%tmp2 = select i1 %tmp1, i32 0, i32 2147483647
@@ -30,7 +30,7 @@
; CHECK: t3
; CHECK: cmp r2, #10
; CHECK: it le
-; CHECK: suble.w r1, r1, #10
+; CHECK: suble r1, #10
; CHECK: mov r0, r1
%tmp1 = icmp sgt i32 %c, 10
%tmp2 = select i1 %tmp1, i32 0, i32 10