commit 09fdc7baae1b6905fe18df48e2278e74d4e39ccd
author Hal Finkel <hfinkel@anl.gov> Fri Jun 08 15:38:25 2012 +0000
committer Hal Finkel <hfinkel@anl.gov> Fri Jun 08 15:38:25 2012 +0000
tree b1a2aadea993ad0d4664fd42e934a9cf05e7238b
parent daa03ec60475a641bcc66799764977f79997ca45

Disable the PPC CTR-Loops pass by default.

The pass itself works well, but the something in the Machine* infrastructure
does not understand terminators which define registers. Without the ability
to use the block-placement pass, etc. this causes performance regressions (and
so is turned off by default). Turning off the analysis turns off the problems
with the Machine* infrastructure.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158206 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/PowerPC/PPCInstrInfo.cpp

diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp
index d652282..8b868e6 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -40,6 +40,10 @@
 
 using namespace llvm;
 
+static cl::
+opt<bool> EnableCTRLoopAnal("enable-ppc-ctrloop-analysis", cl::Hidden,
+            cl::desc("Enable analysis for CTR loops (experimental)"));
+
 PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
   : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
     TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
@@ -229,6 +233,8 @@
                LastInst->getOpcode() == PPC::BDNZ) {
       if (!LastInst->getOperand(0).isMBB())
         return true;
+      if (!EnableCTRLoopAnal)
+        return true;
       TBB = LastInst->getOperand(0).getMBB();
       Cond.push_back(MachineOperand::CreateImm(1));
       Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
@@ -238,6 +244,8 @@
                LastInst->getOpcode() == PPC::BDZ) {
       if (!LastInst->getOperand(0).isMBB())
         return true;
+      if (!EnableCTRLoopAnal)
+        return true;
       TBB = LastInst->getOperand(0).getMBB();
       Cond.push_back(MachineOperand::CreateImm(0));
       Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
@@ -274,6 +282,8 @@
     if (!SecondLastInst->getOperand(0).isMBB() ||
         !LastInst->getOperand(0).isMBB())
       return true;
+    if (!EnableCTRLoopAnal)
+      return true;
     TBB = SecondLastInst->getOperand(0).getMBB();
     Cond.push_back(MachineOperand::CreateImm(1));
     Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
@@ -286,6 +296,8 @@
     if (!SecondLastInst->getOperand(0).isMBB() ||
         !LastInst->getOperand(0).isMBB())
       return true;
+    if (!EnableCTRLoopAnal)
+      return true;
     TBB = SecondLastInst->getOperand(0).getMBB();
     Cond.push_back(MachineOperand::CreateImm(0));
     Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,

lib/Target/PowerPC/PPCTargetMachine.cpp

diff --git a/lib/Target/PowerPC/PPCTargetMachine.cpp b/lib/Target/PowerPC/PPCTargetMachine.cpp
index 6f7fc4b..bcab83c 100644
--- a/lib/Target/PowerPC/PPCTargetMachine.cpp
+++ b/lib/Target/PowerPC/PPCTargetMachine.cpp
@@ -23,8 +23,8 @@
 using namespace llvm;
 
 static cl::
-opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
-                        cl::desc("Disable CTR loops for PPC"));
+opt<bool> EnableCTRLoops("enable-ppc-ctrloops", cl::Hidden,
+                        cl::desc("Enable CTR loops for PPC"));
 
 extern "C" void LLVMInitializePowerPCTarget() {
   // Register the targets
@@ -103,9 +103,10 @@
 }
 
 bool PPCPassConfig::addPreRegAlloc() {
-  if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None) {
+  // FIXME: Once this can be enabled by default, this condition should read:
+  // if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
+  if (EnableCTRLoops)
     PM->add(createPPCCTRLoops());
-  }
 
   return false;
 }