implement shl and sra
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30191 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 892c297..c40521b 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -113,6 +113,18 @@
"and $dst, $a, $b",
[(set IntRegs:$dst, (and IntRegs:$a, IntRegs:$b))]>;
+
+// All arm data processing instructions have a shift. Maybe we don't have
+// to implement this
+def SHL : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
+ "mov $dst, $a, lsl $b",
+ [(set IntRegs:$dst, (shl IntRegs:$a, IntRegs:$b))]>;
+
+def SRA : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
+ "mov $dst, $a, asr $b",
+ [(set IntRegs:$dst, (sra IntRegs:$a, IntRegs:$b))]>;
+
+
def eor_rr : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
"eor $dst, $a, $b",
[(set IntRegs:$dst, (xor IntRegs:$a, IntRegs:$b))]>;