Spelling fix: extened->extended. Trailing whitespace in same function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172793 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index a1b2b2a..5999b15 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -16967,29 +16967,30 @@
TargetLowering::DAGCombinerInfo &DCI,
const X86Subtarget *Subtarget) {
EVT VT = N->getValueType(0);
-
+
if (!VT.isVector())
return SDValue();
SDValue In = N->getOperand(0);
EVT InVT = In.getValueType();
DebugLoc dl = N->getDebugLoc();
- unsigned ExtenedEltSize = VT.getVectorElementType().getSizeInBits();
+ unsigned ExtendedEltSize = VT.getVectorElementType().getSizeInBits();
// Split SIGN_EXTEND operation to use vmovsx instruction when possible
if (InVT == MVT::v8i8) {
- if (ExtenedEltSize > 16 && !Subtarget->hasInt256())
+ if (ExtendedEltSize > 16 && !Subtarget->hasInt256())
In = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, In);
- if (ExtenedEltSize > 32)
+ if (ExtendedEltSize > 32)
In = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i32, In);
return DAG.getNode(ISD::SIGN_EXTEND, dl, VT, In);
}
if ((InVT == MVT::v4i8 || InVT == MVT::v4i16) &&
- ExtenedEltSize > 32 && !Subtarget->hasInt256()) {
+ ExtendedEltSize > 32 && !Subtarget->hasInt256()) {
In = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, In);
return DAG.getNode(ISD::SIGN_EXTEND, dl, VT, In);
}
+
if (!DCI.isBeforeLegalizeOps())
return SDValue();