Improve ext/trunc patterns on PPC64.
The PPC64 backend had patterns for i32 <-> i64 extensions and truncations that
would leave self-moves in the final assembly. Replacing those patterns with ones
based on the SUBREG builtins yields better-looking code.
Thanks to Jakob and Owen for their suggestions in this matter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158283 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/PowerPC/PPCInstr64Bit.td b/lib/Target/PowerPC/PPCInstr64Bit.td
index 30699d2..3d4068a 100644
--- a/lib/Target/PowerPC/PPCInstr64Bit.td
+++ b/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -287,14 +287,6 @@
let PPC970_Unit = 1 in { // FXU Operations.
-// Copies, extends, truncates.
-def OR4To8 : XForm_6<31, 444, (outs G8RC:$rA), (ins GPRC:$rS, GPRC:$rB),
- "or $rA, $rS, $rB", IntGeneral,
- []>;
-def OR8To4 : XForm_6<31, 444, (outs GPRC:$rA), (ins G8RC:$rS, G8RC:$rB),
- "or $rA, $rS, $rB", IntGeneral,
- []>;
-
def LI8 : DForm_2_r0<14, (outs G8RC:$rD), (ins symbolLo64:$imm),
"li $rD, $imm", IntGeneral,
[(set G8RC:$rD, immSExt16:$imm)]>;
@@ -726,11 +718,12 @@
// Extensions and truncates to/from 32-bit regs.
def : Pat<(i64 (zext GPRC:$in)),
- (RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>;
+ (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPRC:$in, sub_32),
+ 0, 32)>;
def : Pat<(i64 (anyext GPRC:$in)),
- (OR4To8 GPRC:$in, GPRC:$in)>;
+ (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPRC:$in, sub_32)>;
def : Pat<(i32 (trunc G8RC:$in)),
- (OR8To4 G8RC:$in, G8RC:$in)>;
+ (EXTRACT_SUBREG G8RC:$in, sub_32)>;
// Extending loads with i64 targets.
def : Pat<(zextloadi1 iaddr:$src),
diff --git a/test/CodeGen/PowerPC/ctrloops.ll b/test/CodeGen/PowerPC/ctrloops.ll
index f7bd354..4b6f7b9 100644
--- a/test/CodeGen/PowerPC/ctrloops.ll
+++ b/test/CodeGen/PowerPC/ctrloops.ll
@@ -20,6 +20,7 @@
for.end: ; preds = %for.body
ret void
; CHECK: @test1
+; CHECK-NOT: or 3, 3, 3
; CHECK: mtctr
; CHECK-NOT: addi
; CHECK-NOT: cmplwi