commit 0a783f783ca05c961234385f5b269d4cf03dbbdb
author Reid Spencer <rspencer@reidspencer.com> Thu Nov 02 01:53:59 2006 +0000
committer Reid Spencer <rspencer@reidspencer.com> Thu Nov 02 01:53:59 2006 +0000
tree 70d2d2b4be7b0f5624d954fd3c482eca33c7f43e
parent 0ac6757586b80d0c82a6651780dcd9b09df251b0

For PR950:
Replace the REM instruction with UREM, SREM and FREM.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31369 91177308-0d34-0410-b5e6-96231b3b80d8

tools/llvm2cpp/CppWriter.cpp

diff --git a/tools/llvm2cpp/CppWriter.cpp b/tools/llvm2cpp/CppWriter.cpp
index 089f1ca..f74294f 100644
--- a/tools/llvm2cpp/CppWriter.cpp
+++ b/tools/llvm2cpp/CppWriter.cpp
@@ -776,7 +776,9 @@
         case Instruction::UDiv:   Out << "getUDiv"; break;
         case Instruction::SDiv:   Out << "getSDiv"; break;
         case Instruction::FDiv:   Out << "getFDiv"; break;
-        case Instruction::Rem:    Out << "getRem"; break;
+        case Instruction::URem:   Out << "getURem"; break;
+        case Instruction::SRem:   Out << "getSRem"; break;
+        case Instruction::FRem:   Out << "getFRem"; break;
         case Instruction::And:    Out << "getAnd"; break;
         case Instruction::Or:     Out << "getOr"; break;
         case Instruction::Xor:    Out << "getXor"; break;
@@ -1026,7 +1028,9 @@
     case Instruction::UDiv:
     case Instruction::SDiv:
     case Instruction::FDiv:
-    case Instruction::Rem:
+    case Instruction::URem:
+    case Instruction::SRem:
+    case Instruction::FRem:
     case Instruction::And:
     case Instruction::Or:
     case Instruction::Xor:
@@ -1040,7 +1044,9 @@
         case Instruction::UDiv:Out << "Instruction::UDiv"; break;
         case Instruction::SDiv:Out << "Instruction::SDiv"; break;
         case Instruction::FDiv:Out << "Instruction::FDiv"; break;
-        case Instruction::Rem: Out << "Instruction::Rem"; break;
+        case Instruction::URem:Out << "Instruction::URem"; break;
+        case Instruction::SRem:Out << "Instruction::SRem"; break;
+        case Instruction::FRem:Out << "Instruction::FRem"; break;
         case Instruction::And: Out << "Instruction::And"; break;
         case Instruction::Or:  Out << "Instruction::Or";  break;
         case Instruction::Xor: Out << "Instruction::Xor"; break;